DOCSLIB.ORG

14. Programmable Logic Devices Overview

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
14. Programmable Logic Devices Overview 14. Programmable Logic Devices Institute of Microelectronic Systems Overview • Introduction • Programming Technologies • Basic Programmable Logic Device (PLD) Concepts • Complex PLD • Field Programmable Gate Array (FPGA) • CAD (Computer Aided Design) for FPGAs • Design flow for Xilinx FPGAs • Economical Considerations • Logic design Alternatives Institute of Microelectronic 14: PLDs Systems 2 Introduction •A Programmable Logic Device is an integrated circuit with internal logic gates and interconnects. These gates can be connected to obtain the required logic configuration. • The term “programmable” means changing either hardware or software configuration of an internal logic and interconnects. • The configuration of the internal logic is done by the user. • PROM, EPROM, PAL, GAL etc. are examples of Programmable Logic Devices. Institute of Microelectronic 14: PLDs Systems 3 Programming Technologies Programmable Logic Device can be programmed in two ways: 1. Mask programming (in some few cases) 2. Field programming (typical) 1.) Mask programming: programming of device is done in the mask level. + good timing performance due to internal connections hardwired during manufacture + cheap at high volume production - programmed by manufacturer - development cycle = weeks or months - not re-programmable Institute of Microelectronic 14: PLDs Systems 4 Programming Technologies (II) 2.) Field programming: Programming of device is done by the user. The programming technologies are of two types Permanent type (Non-volatile): • Fuse (normal on) - ‘CLOSE (intact)’ ‘OPEN (blown)’ • Anti-fuse (normal off) - just the opposite of a FUSE • EPROM • EEPROM Nonpermanent type (Volatile): • driving n-MOS pass transistor by SRAM •NOTE: -When power of device is switched off then the content of SRAM is lost. Institute of Microelectronic 14: PLDs Systems 5 Basic PLD Concepts 1.) PLA (Programmable Logic Array): • array of AND and OR gates are programmable • product term sharing: every product term of the AND array can be connected to the input of any OR gate • unidirectional input/output pins Figure 1: PLA device Institute of Microelectronic 14: PLDs Systems 6 Basic PLD Concepts (II) 2.) Memory based: Device with fixed AND array and programmable OR array • output of OR gate has fixed connection with input of AND gates • PROM, EPROM and EEPROM are memory based PLD device 3.) PAL/GAL(Programmable Array Logic/ Gate Array Logic): AND array is programmable and OR array has fix connection with outputs of AND gates. PAL/GAL devices may have bi-directional I/O pins. There are three different types of PAL/GAL devices • combinational PAL devices are used for the implementation of logic function • sequential PAL devices are used for the implementation of sequential logic (finite state machines) • arithmetic PAL devices sum of product terms may be combined by XOR gates at the input of the macrocell D flip-flop Institute of Microelectronic 14: PLDs Systems 7 Basic PLD Concepts (IV) Additional features of PAL/GAL devices • PAL: - EPROM - based programming Technology • GAL: - has array of programmable AND gates and OLMC (Output Logic Macro Cell) - EEPROM - based programming Technology - programmable output polarity - device can be configured as dedicated input and output mode Institute of Microelectronic 14: PLDs Systems 8 Figure 2: Combinational PAL device, AMD PAL16L8 Institute of Microelectronic 14: PLDs Systems 9 Figure 3: Sequential PAL devices, AMD PAL16R8 Institute of Microelectronic 14: PLDs Systems 10 Figure 4: Arithmetic PAL device, AMD PAL16A4 Institute of Microelectronic 14: PLDs Systems 11 • GAL16V8 has 8 configurable OLMC (Output Logic Macro Cell) • each OLMC has programmable XOR to get active low or high output signal • there is a feedback from output to input Figure 5: GAL device, GAL 16V8 Institute of Microelectronic 14: PLDs Systems 12 Complex PLD (CPLD) • is combination of multiple PAL or GAL type devices on a single chip • CPLD architectures consists of - Macrocells - configurable flip-flop (D, T, JK or SR) - Output enable/clock select - Feedback select • CPLD has predictable time delay because of hierarchical inter-connection • easy to route, very fast turnaround • performance independent of netlist • devices is erasable and programmable with non-volatile EPROM or EEPROM configuration • wide designer acceptance • has more logic density than any classical PLDs device • relatively mature technology, but some innovation still ongoing Institute of Microelectronic 14: PLDs Systems 13 Complex PLD (II) Figure 6: Complex PLD device Altera EP1800 Institute of Microelectronic 14: PLDs Systems 14 Erasable CPLD • EP1800 is erasable PLD device and has 48 macrocells, 16 dedicated input pins and 48 I/O pins. • device is divided into four quadrants, each contains 12 macrocells and has local bus with 24 lines and a local clock • out of 12 microcells, 8 are “local” macrocells and 4 are “global” macrocells Figure 8: Global macrocell Figure 7: Local macrocell Institute of Microelectronic 14: PLDs Systems 15 Erasable CPLD (II) • global bus has 64 lines and runs through all of the four quadrants (true and complement signals of 12 inputs (=24 lines) + true and complement of 4 clocks (=8 lines) + true and complement of I/O pins of the 4 global macro cells in each quadrant (=32 lines) • macrocells: combinational or registered data output; the flip-flop is configurable as D, T, JK or SR type. Figure 10: Asynchronous clock, Figure 9: Synchronous clock, output permanently enabled output enable by product term Institute of Microelectronic 14: PLDs Systems 16 Electrically Erasable PLD • MAX 7000 is EEPROM based programmable logic device • it’s architecture includes following elements, - Logic Array Blocks (LABs) - Macrocells - Programmable Interconnect Array (PIA) - I/O control blocks • Pin to pin delay is about 5 ns • predictable delay because of hierarchical routing structure of PIA Figure 11: Block diagram of Altera MAX 7000 family Institute of Microelectronic 14: PLDs Systems 17 Electrically Erasable PLD (II) • each Logic Array Block (LAB) has 16 macrocells • each macrocell consists of logic array, product term select matrix and programmable register • the product term select matrix allocates product terms from logic array to use them as either primary logic inputs to OR and XOR gate or secondary inputs to clear, preset, clock and clock enable control function for the register of macrocell Figure 12: MAX 7000 device, macrocell Institute of Microelectronic 14: PLDs Systems 18 Electrically Erasable PLD (III) • logic is routed among LABs via the PIA. • dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device • only the signals required by each LAB are actually routed from the PIA into the LAB Figure 13: • selecting of signal from PIA MAX 7000 device, programmable to LAB is done by an Interconnect Array (PIA) EEPROM cell Institute of Microelectronic 14: PLDs Systems 19 Field Programmable Gate Array • FPGA is a general purpose, multi-level programmable logic device • FPGA is composed of, - logic blocks to implement combinational and sequential logic circuit - programmable interconnect wire to connect input and output of logic blocks - I/O blocks logic blocks at periphery of device for the external connection •“The routing resources are both the greatest strength and weakness of the FPGA’s” Institute of Microelectronic 14: PLDs Systems 20 Field Programmable Gate Array (II) Figure 14: Symmetrical array architecture of FPGAs Institute of Microelectronic 14: PLDs Systems 21 Field Programmable Gate Array (III) • There are four main categories of FPGAs available commercially, - symmetrical array - row - based - hierarchical PLD - sea of gates • They are differ to each other on their interconnection and how they are programmed Figure 15: Category of different FPGA Institute of Microelectronic 14: PLDs Systems 22 Programming Technologies • Currently, there are four programming technologies for FPGAs, - static RAM cells - anti fuse - EPROM transistor - EEPROM transistor Static RAM programming technology: b) transmission a) pass-transister c) multiplexer gate Figure 16: SRAM based programming technology Institute of Microelectronic 14: PLDs Systems 23 SRAM Programming technology • completely reusable - no limit concerning re-programmability • pass gate closes when a “1” is stored in the SRAM cell • allows iterative prototyping • volatile memory - power must be maintained • large area - five transistor SRAM cell plus pass gate • memory cells distributed throughout the chip • fast re-programmability (tens of milliseconds) • only standard CMOS process required Institute of Microelectronic 14: PLDs Systems 24 Anti-fuse Programming •An anti-fuse is the opposite of normal fuse. • Anti-fuse are made with a modified CMOS process having an extra step • This step creates a very thin insulating layer which separates two conducting layers • That thin insulating layer is fused by applying a high voltage across the conducting layer • Such high voltage can be destructive for CMOS logic circuit • Non-volatile (Permanent) • Requires extra programming circuitry, including a programming transistor Institute of Microelectronic 14: PLDs Systems 25 Actel PLICE Anti-fuse programming technology • The Actel PLICE anti-fuse consists of a layer of positively doped silicon (n+ diffusion), a layer of dielectric (Oxygen-Nitrogen-Oxygen) and a layer of polysilicon • it is programmed by placing a relatively high voltage (18V) across the anti-
Load more

Recommended publications
  • COMBINATIONAL CIRCUITS Combinational Plds Basic Configuration of Three Plds (Programmable Logic Devices)
    COMBINATIONAL CIRCUITS Combinational PLDs Basic Configuration of three PLDs (Programmable Logic Devices) Boolean variables Fixed Programmable INPUTS AND array OUTPUTS OR array (decoder) Programmable Read-Only Memory (PROM) Programmable INPUTS Fixed OUTPUTS AND array OR array Programmable Array Logic (PAL) Programmable INPUTS Programmable AND array OR array OUTPUTS (Field) Programmable Logic Array (PLA) 1 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Two-level AND-OR Arrays (Programmable Logic Devices) F (C,B, A) = CBA + CB A A AND B + V B C A C B F C F AND F + V 1 B OR C Multiple functions Simplified equivalent circuit for two-level AND-OR array 2 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Field-programmable AND and OR Arrays (Programmable Logic Devices) Field-programmable logic elements are devices that contain uncommitted AND/OR arrays that are (programmed) configured by the designer. + V + V A A F (C,B, A) F (C,B, A) = CBA B B C C Unprogrammed AND array Fuse can be "blown" by passing a high current through it. 3 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Field-programmable AND and OR Arrays (Programmable Logic Devices) F (P1 ,P2 ,P3 ) = P1 + P3 P1 P1 P2 P2 P3 P3 F F (P1 ,P2 ,P3 ) Unprogrammed OR array Programmed OR array P1 P2 P3 P1 + P3 4 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Output Polarity Options (Programmable Logic Devices) I1 Ik Active high Active low Complementary outputs Programmable polarity P P 1 m + V 5 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Bidirectional Pins and Feed back Lines (Programmable Logic Devices) I1 Ik Feedback IOm Three-state driver 6 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs PLA (Programmable Logic Array) (Programmable Logic Devices) If we use ROM to implement the Boolean function we will waste the silicon area.
    [Show full text]
  • Configurable RISC-V Softcore Processor for FPGA Implementation
    1 Configurable RISC-V softcore processor for FPGA implementation Joao˜ Filipe Monteiro Rodrigues, Instituto Superior Tecnico,´ Universidade de Lisboa Abstract—Over the past years, the processor market has and development of several programming tools. The RISC-V been dominated by proprietary architectures that implement Foundation controls the RISC-V evolution, and its members instruction sets that require licensing and the payment of fees to are responsible for promoting the adoption of RISC-V and receive permission so they can be used. ARM is an example of one of those companies that sell its microarchitectures to participating in the development of the new ISA. In the list of the manufactures so they can implement them into their own members are big companies like Google, NVIDIA, Western products, and it does not allow the use of its instruction set Digital, Samsung, or Qualcomm. (ISA) in other implementations without licensing. The RISC-V The main goal of this work is the development of a RISC- instruction set appeared proposing the hardware and software V softcore processor to be implemented in an FPGA, using development without costs, through the creation of an open- source ISA. This way, it is possible that any project that im- a non-RISC-V core as the base of this architecture. The plements the RISC-V ISA can be made available open-source or proposed solution is focused on solving the problems and even implemented in commercial products. However, the RISC- limitations identified in the other RISC-V cores that were V solutions that have been developed do not present the needed analyzed in this thesis, especially in terms of the adaptability requirements so they can be included in projects, especially the and flexibility, allowing future modifications according to the research projects, because they offer poor documentation, and their performances are not suitable.
    [Show full text]
  • VLSI Design: a New Approach
    International Journal of Information Theory Volume 1, Issue 1, 2011, pp-01-04 Available online at: http://www.bioinfo.in/contents.php?id=103 VLSI Design: A New Approach M.B. Swami and V.P. Pawar Department of Physics/Electronics/Computer Science, Maharashtra Udyagiri Mahavidyalaya, Udgir, India e-mail: [email protected] Abstract—This paper presents the different • Cores such as PCI are available and able to Programmable Logic Array is an important building circuit integrate with relative ease Getting started in of VLSI chips and some of the FPGA architectures have FPGA design is easy. evolved from the basic Programmable Logic Array The tools are cheap (and sometimes free) for low- architectures. In this paper the new concepts of Verilog Hardware Description language is included in VLSI Design. end devices and affordable for the high end. Modern Keywords: Programmable Logic Array, FPGA, Verilog. HDL (hardware design language) environments are very powerful for creating and verifying a design. There I. INTRODUCTION is plenty of documentation available for using different vendor’s FPGA design tools and exploiting features of Very-large-scale integration (VLSI) is the process of different FPGAs. creating integrated circuits by combining thousands of Even with modern tools, the fundamentals of transistor-based circuits into a single chip. digital design still remain intact and must be Implementation is based on FPGA design flow with understood. If the fundamentals are ignored, there is a Xilinx tools which will help you to design complex good chance that your design will not work consistently digital systems using HDL and also to get experience of and will probably exhibit intermittent modes of processor and controller implementations on FPGAs.
    [Show full text]
  • Introduction to ASIC Design
    ’14EC770 : ASIC DESIGN’ An Introduction Application - Specific Integrated Circuit Dr.K.Kalyani AP, ECE, TCE. 1 VLSI COMPANIES IN INDIA • Motorola India – IC design center • Texas Instruments – IC design center in Bangalore • VLSI India – ASIC design and FPGA services • VLSI Software – Design of electronic design automation tools • Microchip Technology – Offers VLSI CMOS semiconductor components for embedded systems • Delsoft – Electronic design automation, digital video technology and VLSI design services • Horizon Semiconductors – ASIC, VLSI and IC design training • Bit Mapper – Design, development & training • Calorex Institute of Technology – Courses in VLSI chip design, DSP and Verilog HDL • ControlNet India – VLSI design, network monitoring products and services • E Infochips – ASIC chip design, embedded systems and software development • EDAIndia – Resource on VLSI design centres and tutorials • Cypress Semiconductor – US semiconductor major Cypress has set up a VLSI development center in Bangalore • VDAT 2000 – Info on VLSI design and test workshops 2 VLSI COMPANIES IN INDIA • Sandeepani – VLSI design training courses • Sanyo LSI Technology – Semiconductor design centre of Sanyo Electronics • Semiconductor Complex – Manufacturer of microelectronics equipment like VLSIs & VLSI based systems & sub systems • Sequence Design – Provider of electronic design automation tools • Trident Techlabs – Power systems analysis software and electrical machine design services • VEDA IIT – Offers courses & training in VLSI design & development • Zensonet Technologies – VLSI IC design firm eg3.com – Useful links for the design engineer • Analog Devices India Product Development Center – Designs DSPs in Bangalore • CG-CoreEl Programmable Solutions – Design services in telecommunications, networking and DSP 3 Physical Design, CAD Tools. • SiCore Systems Pvt. Ltd. 161, Greams Road, ... • Silicon Automation Systems (India) Pvt. Ltd. ( SASI) ... • Tata Elxsi Ltd.
    [Show full text]
  • FPGA Architecture: Survey and Challenges Full Text Available At
    Full text available at: http://dx.doi.org/10.1561/1000000005 FPGA Architecture: Survey and Challenges Full text available at: http://dx.doi.org/10.1561/1000000005 FPGA Architecture: Survey and Challenges Ian Kuon University of Toronto Toronto, ON Canada [email protected] Russell Tessier University of Massachusetts Amherst, MA USA [email protected] Jonathan Rose University of Toronto Toronto, ON Canada [email protected] Boston – Delft Full text available at: http://dx.doi.org/10.1561/1000000005 Foundations and Trends R in Electronic Design Automation Published, sold and distributed by: now Publishers Inc. PO Box 1024 Hanover, MA 02339 USA Tel. +1-781-985-4510 www.nowpublishers.com [email protected] Outside North America: now Publishers Inc. PO Box 179 2600 AD Delft The Netherlands Tel. +31-6-51115274 The preferred citation for this publication is I. Kuon, R. Tessier and J. Rose, FPGA Architecture: Survey and Challenges, Foundations and Trends R in Elec- tronic Design Automation, vol 2, no 2, pp 135–253, 2007 ISBN: 978-1-60198-126-4 c 2008 I. Kuon, R. Tessier and J. Rose All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, mechanical, photocopying, recording or otherwise, without prior written permission of the publishers. Photocopying. In the USA: This journal is registered at the Copyright Clearance Cen- ter, Inc., 222 Rosewood Drive, Danvers, MA 01923. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by now Publishers Inc for users registered with the Copyright Clearance Center (CCC).
    [Show full text]
  • The Basics of Logic Design
    C APPENDIX The Basics of Logic Design C.1 Introduction C-3 I always loved that C.2 Gates, Truth Tables, and Logic word, Boolean. Equations C-4 C.3 Combinational Logic C-9 Claude Shannon C.4 Using a Hardware Description IEEE Spectrum, April 1992 Language (Shannon’s master’s thesis showed that C-20 the algebra invented by George Boole in C.5 Constructing a Basic Arithmetic Logic the 1800s could represent the workings of Unit C-26 electrical switches.) C.6 Faster Addition: Carry Lookahead C-38 C.7 Clocks C-48 AAppendixC-9780123747501.inddppendixC-9780123747501.indd 2 226/07/116/07/11 66:28:28 PPMM C.8 Memory Elements: Flip-Flops, Latches, and Registers C-50 C.9 Memory Elements: SRAMs and DRAMs C-58 C.10 Finite-State Machines C-67 C.11 Timing Methodologies C-72 C.12 Field Programmable Devices C-78 C.13 Concluding Remarks C-79 C.14 Exercises C-80 C.1 Introduction This appendix provides a brief discussion of the basics of logic design. It does not replace a course in logic design, nor will it enable you to design signifi cant working logic systems. If you have little or no exposure to logic design, however, this appendix will provide suffi cient background to understand all the material in this book. In addition, if you are looking to understand some of the motivation behind how computers are implemented, this material will serve as a useful intro- duction. If your curiosity is aroused but not sated by this appendix, the references at the end provide several additional sources of information.
    [Show full text]
  • RESEARCH INSIGHTS – Hardware Design: FPGA Security Risks
    RESEARCH INSIGHTS Hardware Design: FPGA Security Risks www.nccgroup.trust CONTENTS Author 3 Introduction 4 FPGA History 6 FPGA Development 10 FPGA Security Assessment 12 Conclusion 17 Glossary 18 References & Further Reading 19 NCC Group Research Insights 2 All Rights Reserved. © NCC Group 2015 AUTHOR DUNCAN HURWOOD Duncan is a senior consultant at NCC Group, specialising in telecom, embedded systems and application review. He has over 18 years’ experience within the telecom and security industry performing almost every role within the software development cycle from design and development to integration and product release testing. A dedicated security assessor since 2010, his consultancy experience includes multiple technologies, languages and platforms from web and mobile applications, to consumer devices and high-end telecom hardware. NCC Group Research Insights 3 All Rights Reserved. © NCC Group 2015 GLOSSARY AES Advanced encryption standard, a cryptography OTP One time programmable, allowing write once cipher only ASIC Application-specific integrated circuit, non- PCB Printed circuit board programmable hardware logic chip PLA Programmable logic array, forerunner of FPGA Bitfile Binary instruction file used to program FPGAs technology CLB Configurable logic block, an internal part of an PUF Physically unclonable function FPGA POWF Physical one-way function CPLD Complex programmable logic device PSoC Programmable system on chip, an FPGA and EEPROM Electronically erasable programmable read- other hardware on a single chip only memory
    [Show full text]
  • Full-Custom Ics Standard-Cell-Based
    Full-Custom ICs Design a chip from scratch. Engineers design some or all of the logic cells, circuits, and the chip layout specifi- cally for a full-custom IC. Custom mask layers are created in order to fabricate a full-custom IC. Advantages: complete flexibility, high degree of optimization in performance and area. Disadvantages: large amount of design effort, expensive. 1 Standard-Cell-Based ICs Use predesigned, pretested and precharacterized logic cells from standard-cell li- brary as building blocks. The chip layout (defining the location of the building blocks and wiring between them) is customized. As in full-custom design, all mask layers need to be customized to fabricate a new chip. Advantages: save design time and money, reduce risk compared to full-custom design. Disadvantages: still incurs high non-recurring-engineering (NRE) cost and long manufacture time. 2 D A B C A B B D C D A A B B Cell A Cell B Cell C Cell D Feedthrough Cell Standard-cell-based IC design. 3 Gate-Array Parts of the chip are pre-fabricated, and other parts are custom fabricated for a particular customer’s circuit. Idential base cells are pre-fabricated in the form of a 2-D array on a gate-array (this partially finished chip is called gate-array template). The wires between the transistors inside the cells and between the cells are custom fabricated for each customer. Custom masks are made for the wiring only. Advantages: cost saving (fabrication cost of a large number of identical template wafers is amortized over different customers), shorter manufacture lead time.
    [Show full text]
  • Xilinx Vivado – „EDK” Embedded Development) 4
    EFOP-3.4.3-16-2016-00009 A fels őfokú oktatás min őségének és hozzáférhet őségének együttes javítása a Pannon Egyetemen EMBEDDED SYSTEM DEVELOPMENT (MISAM154R) Created by Zsolt Voroshazi, PhD [email protected] Updated: 02 March. 2020. 2. FPGAS & PLATFORMS Embedded Systems Topics covered 1. Introduction – Embedded Systems 2. FPGAs, Digilent ZyBo development platform 3. Embedded System - Firmware development environment (Xilinx Vivado – „EDK” Embedded Development) 4. Embedded System - Software development environment (Xilinx VITIS – „SDK”) 5. Embedded Base System Build (and Board Bring-Up) 6. Adding Peripherals (from IP database) to BSB 7. Adding Custom (=own) Peripherals to BSB 8. Design and Development of Complex IP cores and applications (e.g. camera/video/ audio controllers) 3 Further references • XILINX official website: http://www.xilinx.com • EE Journal – Electronic Engineering: http://www.eejournal.com/design/embedded • EE Times - News: http://www.eetimes.com/design/embedded 4 PLD & FPGA CIRCUITS General description PAST … • Before ’80s, designing logic networks for digital circuits, modern development tools were not yet available as today. • The design of high complexity (multi I/O) logical combination and sequential networks was therefore slow and cumbersome, often coupled with paper- based design, multiple manual checks, and calculations. • We could not talk about advanced design and simulation tools (CAD) either, so there was a high probability of error in a prototype design. 6 … AND PRESENT • Today, all of these are available in an automated way (EDA - Electronic Design Automation), which, in addition to the use of Programmable Logic Devices (PLD), is relatively fast for both Printed Circuit Boards (PCB) and Application-specific Integrated Circuits and Processors (ASIC / ASSP).
    [Show full text]
  • CPLD and FPGA Architectures
    ECE 428 Programmable ASIC Design CPLD and FPGA Architectures Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901 3-1 Definitions Field Programmable Device (FPD): — a general term that refers to any type of integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs. Programming of such a device often involves placing the chip into a special programming unit, but some chips can also be configured “in-system”. Another name for FPDs is programmable logic devices (PLDs). Source: S. Brown and J. Rose, FPGA and CPLD Architectures: A Tutorial, IEEE Design and Test of Computer, 1996 3-2 Classifications PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND- plane and an OR-plane, where both levels are programmable PAL — a Programmable Array Logic (PAL) is a relatively small FPD that has a programmable AND-plane followed by a fixed OR-plane SPLD — refers to any type of Simple PLD, usually either a PLA or PAL CPLD — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip. FPGA — a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity. 3-3 PLA Programmable AND Plane Programmable OR Plane Programmable Node Un-programmed Connect Disconnect X Y O1 O2 O3 O4 X XY Y XY XY XY XX YY 3-4 PLA Programmable AND Plane Programmable OR Plane YZ XZ XYZ XY XY Z XY+YZ ?? XZ+XYZ 3-5 PAL Programmable AND Plane Fix OR Plane X Y O1 O2 O3 O4 3-6 PAL with Logic Expanders Programmable AND Plane Fix OR Plane ? Logic expanders 3-7 PLA v.s.
    [Show full text]
  • Stratix II Vs. Virtex-4 Power Comparison & Estimation Accuracy
    White Paper Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy Introduction This document compares power consumption and power estimation accuracy for Altera® Stratix® II FPGAs and Xilinx Virtex-4 FPGAs. The comparison addresses all components of power: core dynamic power, core static power, and I/O power. This document uses bench-measured results to compare actual dynamic power consumption. To compare power estimation accuracy, the analysis uses the vendor-recommended power estimation software tools. The summary of these comparisons are: Altera’s Quartus® II PowerPlay power analyzer tool is accurate (to within 20%), while Xilinx’s tools are significantly less accurate. Stratix II devices exhibit lower dynamic power than Virtex-4 devices, resulting in total device power that is equal. Having an accurate FPGA power estimate is important to avoid surprises late in the design and prototyping phase. Inaccurate estimates can be costly and cause design issues, including: board re-layout, changes to power-management circuitry, changes cooling solution, unreliable FPGA operation, undue heating of other components, and changes to the FPGA design. Furthermore, without accurate power estimates, it is impossible for the designer and FPGA CAD software to optimize design power. This white paper contains the following sections: Components of total device power Power estimation and measurement methodology Core dynamic power comparison – power tool accuracy and bench measurements Core Static power comparison I/O power comparison Total device power summary For competitive comparisons on performance and density between Stratix II and Virtex-4 devices, refer to the following white papers from the Altera web site: Stratix II vs.
    [Show full text]
  • Logic Directory Programmable
    coverstory By Brian Dipert, Technical Editor Programmable-Programmable- he umbrella term “logic devices” subdivides into several categories: discrete logic, simple and logiclogic Tcomplex PLDs, FPGAs, and standard- and cus- tom-cell ASICs. FPGAs, SPLDs/PALs, and CPLDs are all programmable-logic devices, although their inter- nal architecture implementations differ. Programmable-logic devices are the fastest growing segment of the logic-device family, for two funda- directorydirectory mental reasons. For one thing, their ever-increasing per-device logic-gate count “gathers up”functions that might otherwise spread over a number of discrete-log- ic and memory chips, improving end-system size, power consumption, performance, reliability, and cost. Equally important, you can in a matter of seconds or THE SECOND ANNUAL EDN PLD minutes configure and, in many cases, reconfigure these devices at your workstation or in the system-as- DIRECTORY HIGHLIGHTS THE sembly line. This capability provides powerful flexi- bility to react to last-minute design changes, to pro- ARCHITECTURES AVAILABLE FOR YOUR totype ideas before implementation, and to meet time-to-market deadlines driven by both customer NEXT DESIGN. FIND OUT WHAT’S NEW, need and competitive pressures. Programmable-logic devices lack the long lead- WHAT’S OBSOLETE, AND WHAT’S times, up-front NRE charges, minimum-order quan- tities, and inventory complexity of ASICs. As per-gate EVOLVEDEVOLVED ININ PALS,PALs, PLDS,PLDS, ANDAND FPGAFPGAS.S. cost decreases and the number of gates per component increases, programmable-logic devices are making sig- nificant inroads into gate-array-ASIC territory. Sys- AND CHECK THIS OUT: tem designers and manufacturers are only beginning WE’VE POSTED COMPREHENSIVE to explore and exploit in-system reprogrammability, either to correct errors and upgrade functions once the TABLES OF DEVICES AND FEATURES end system is in users’ hands or to use a fixed number IN THE WEB VERSION OF THIS of logic gates to implement multiple functions.
    [Show full text]