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14. Programmable Logic Devices Institute of Microelectronic Systems Overview • Introduction • Programming Technologies • Basic Programmable Logic Device (PLD) Concepts • Complex PLD • Field Programmable Gate Array (FPGA) • CAD (Computer Aided Design) for FPGAs • Design flow for Xilinx FPGAs • Economical Considerations • Logic design Alternatives Institute of Microelectronic 14: PLDs Systems 2 Introduction •A Programmable Logic Device is an integrated circuit with internal logic gates and interconnects. These gates can be connected to obtain the required logic configuration. • The term “programmable” means changing either hardware or software configuration of an internal logic and interconnects. • The configuration of the internal logic is done by the user. • PROM, EPROM, PAL, GAL etc. are examples of Programmable Logic Devices. Institute of Microelectronic 14: PLDs Systems 3 Programming Technologies Programmable Logic Device can be programmed in two ways: 1. Mask programming (in some few cases) 2. Field programming (typical) 1.) Mask programming: programming of device is done in the mask level. + good timing performance due to internal connections hardwired during manufacture + cheap at high volume production - programmed by manufacturer - development cycle = weeks or months - not re-programmable Institute of Microelectronic 14: PLDs Systems 4 Programming Technologies (II) 2.) Field programming: Programming of device is done by the user. The programming technologies are of two types Permanent type (Non-volatile): • Fuse (normal on) - ‘CLOSE (intact)’ ‘OPEN (blown)’ • Anti-fuse (normal off) - just the opposite of a FUSE • EPROM • EEPROM Nonpermanent type (Volatile): • driving n-MOS pass transistor by SRAM •NOTE: -When power of device is switched off then the content of SRAM is lost. Institute of Microelectronic 14: PLDs Systems 5 Basic PLD Concepts 1.) PLA (Programmable Logic Array): • array of AND and OR gates are programmable • product term sharing: every product term of the AND array can be connected to the input of any OR gate • unidirectional input/output pins Figure 1: PLA device Institute of Microelectronic 14: PLDs Systems 6 Basic PLD Concepts (II) 2.) Memory based: Device with fixed AND array and programmable OR array • output of OR gate has fixed connection with input of AND gates • PROM, EPROM and EEPROM are memory based PLD device 3.) PAL/GAL(Programmable Array Logic/ Gate Array Logic): AND array is programmable and OR array has fix connection with outputs of AND gates. PAL/GAL devices may have bi-directional I/O pins. There are three different types of PAL/GAL devices • combinational PAL devices are used for the implementation of logic function • sequential PAL devices are used for the implementation of sequential logic (finite state machines) • arithmetic PAL devices sum of product terms may be combined by XOR gates at the input of the macrocell D flip-flop Institute of Microelectronic 14: PLDs Systems 7 Basic PLD Concepts (IV) Additional features of PAL/GAL devices • PAL: - EPROM - based programming Technology • GAL: - has array of programmable AND gates and OLMC (Output Logic Macro Cell) - EEPROM - based programming Technology - programmable output polarity - device can be configured as dedicated input and output mode Institute of Microelectronic 14: PLDs Systems 8 Figure 2: Combinational PAL device, AMD PAL16L8 Institute of Microelectronic 14: PLDs Systems 9 Figure 3: Sequential PAL devices, AMD PAL16R8 Institute of Microelectronic 14: PLDs Systems 10 Figure 4: Arithmetic PAL device, AMD PAL16A4 Institute of Microelectronic 14: PLDs Systems 11 • GAL16V8 has 8 configurable OLMC (Output Logic Macro Cell) • each OLMC has programmable XOR to get active low or high output signal • there is a feedback from output to input Figure 5: GAL device, GAL 16V8 Institute of Microelectronic 14: PLDs Systems 12 Complex PLD (CPLD) • is combination of multiple PAL or GAL type devices on a single chip • CPLD architectures consists of - Macrocells - configurable flip-flop (D, T, JK or SR) - Output enable/clock select - Feedback select • CPLD has predictable time delay because of hierarchical inter-connection • easy to route, very fast turnaround • performance independent of netlist • devices is erasable and programmable with non-volatile EPROM or EEPROM configuration • wide designer acceptance • has more logic density than any classical PLDs device • relatively mature technology, but some innovation still ongoing Institute of Microelectronic 14: PLDs Systems 13 Complex PLD (II) Figure 6: Complex PLD device Altera EP1800 Institute of Microelectronic 14: PLDs Systems 14 Erasable CPLD • EP1800 is erasable PLD device and has 48 macrocells, 16 dedicated input pins and 48 I/O pins. • device is divided into four quadrants, each contains 12 macrocells and has local bus with 24 lines and a local clock • out of 12 microcells, 8 are “local” macrocells and 4 are “global” macrocells Figure 8: Global macrocell Figure 7: Local macrocell Institute of Microelectronic 14: PLDs Systems 15 Erasable CPLD (II) • global bus has 64 lines and runs through all of the four quadrants (true and complement signals of 12 inputs (=24 lines) + true and complement of 4 clocks (=8 lines) + true and complement of I/O pins of the 4 global macro cells in each quadrant (=32 lines) • macrocells: combinational or registered data output; the flip-flop is configurable as D, T, JK or SR type. Figure 10: Asynchronous clock, Figure 9: Synchronous clock, output permanently enabled output enable by product term Institute of Microelectronic 14: PLDs Systems 16 Electrically Erasable PLD • MAX 7000 is EEPROM based programmable logic device • it’s architecture includes following elements, - Logic Array Blocks (LABs) - Macrocells - Programmable Interconnect Array (PIA) - I/O control blocks • Pin to pin delay is about 5 ns • predictable delay because of hierarchical routing structure of PIA Figure 11: Block diagram of Altera MAX 7000 family Institute of Microelectronic 14: PLDs Systems 17 Electrically Erasable PLD (II) • each Logic Array Block (LAB) has 16 macrocells • each macrocell consists of logic array, product term select matrix and programmable register • the product term select matrix allocates product terms from logic array to use them as either primary logic inputs to OR and XOR gate or secondary inputs to clear, preset, clock and clock enable control function for the register of macrocell Figure 12: MAX 7000 device, macrocell Institute of Microelectronic 14: PLDs Systems 18 Electrically Erasable PLD (III) • logic is routed among LABs via the PIA. • dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device • only the signals required by each LAB are actually routed from the PIA into the LAB Figure 13: • selecting of signal from PIA MAX 7000 device, programmable to LAB is done by an Interconnect Array (PIA) EEPROM cell Institute of Microelectronic 14: PLDs Systems 19 Field Programmable Gate Array • FPGA is a general purpose, multi-level programmable logic device • FPGA is composed of, - logic blocks to implement combinational and sequential logic circuit - programmable interconnect wire to connect input and output of logic blocks - I/O blocks logic blocks at periphery of device for the external connection •“The routing resources are both the greatest strength and weakness of the FPGA’s” Institute of Microelectronic 14: PLDs Systems 20 Field Programmable Gate Array (II) Figure 14: Symmetrical array architecture of FPGAs Institute of Microelectronic 14: PLDs Systems 21 Field Programmable Gate Array (III) • There are four main categories of FPGAs available commercially, - symmetrical array - row - based - hierarchical PLD - sea of gates • They are differ to each other on their interconnection and how they are programmed Figure 15: Category of different FPGA Institute of Microelectronic 14: PLDs Systems 22 Programming Technologies • Currently, there are four programming technologies for FPGAs, - static RAM cells - anti fuse - EPROM transistor - EEPROM transistor Static RAM programming technology: b) transmission a) pass-transister c) multiplexer gate Figure 16: SRAM based programming technology Institute of Microelectronic 14: PLDs Systems 23 SRAM Programming technology • completely reusable - no limit concerning re-programmability • pass gate closes when a “1” is stored in the SRAM cell • allows iterative prototyping • volatile memory - power must be maintained • large area - five transistor SRAM cell plus pass gate • memory cells distributed throughout the chip • fast re-programmability (tens of milliseconds) • only standard CMOS process required Institute of Microelectronic 14: PLDs Systems 24 Anti-fuse Programming •An anti-fuse is the opposite of normal fuse. • Anti-fuse are made with a modified CMOS process having an extra step • This step creates a very thin insulating layer which separates two conducting layers • That thin insulating layer is fused by applying a high voltage across the conducting layer • Such high voltage can be destructive for CMOS logic circuit • Non-volatile (Permanent) • Requires extra programming circuitry, including a programming transistor Institute of Microelectronic 14: PLDs Systems 25 Actel PLICE Anti-fuse programming technology • The Actel PLICE anti-fuse consists of a layer of positively doped silicon (n+ diffusion), a layer of dielectric (Oxygen-Nitrogen-Oxygen) and a layer of polysilicon • it is programmed by placing a relatively high voltage (18V) across the anti-
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