Philips Semiconductors
12C Specific information Programming the 12C Interface
EMBEDDED SYSTEMS
Whenintedigent devices need to communicate
MitchellKahn
he Inter-Integrated Circuit Bus group. I took excepuon (although not (“1% Bus” for short) IS a two- verballv!) to his suggestIon. .A weekend wire, synchronous, serial inter- of intense hacking later, I presented the face designed pnmanly for first prototype of the driver. My reward? commumcation between intel- 1got to write a generic version of the Tligent IC devices. The 1% bus offers sev- dnver for general distnbutlon. eral advantages over ,.traditlonal” seri- al interfaces such as LMicrowlre and Design Tmde-offs RS-232. Among the advanced features Three distmct tasks are mvolved m im- of 1% are multimaster operauon, auto- plementmg the 12C protocol: watching matic baud-rate adjustment, and .‘plug- the bus, waltmg for a spectiic amount Jnd-play ’ network extensions. of time, and driving the bus. This be- ,Mention the 1% bus to a group of came apparent when I flowcharted 1 Amencan engmeers and you’ll likely get byte of a typical bus transaction: see hit with an abundance of blank stares. Figure 1. The time delays associated I say Amencan engmeers because un- with creatmg the bus waveforms would tll recently the 12C bus was pnmanly a normally have been relegated to the European phenomenon. Withm the last 8OCl86EB’s on-chip timers. I could not, year, however, Interest m I‘C in the however. assume that the end users of Unite ,d States has risen dramatIcally. my code would be able to spare a urner Embe tdded systems designers are real- for the software 12C prt. I had to forego zmg the cost. soace. and Dower sav- the elegance (and to some extent ac- mgs-afforded by’robust se&l mterchip economic sense to route a full-speed curacvj of the on-chip timers for the protocols. parallel bus to a slow penpherai. sledgehammer approach of software The idea of serial Interconnect be- Unfortunately for most serlal-bus- timing loops. Luchlv, the IlC protocol tween integrated clrcults IS not new. capable devices, the choice of a bus IS extremely forglvmg with regard to Many semconductor vendors offer de- protocol wdl dictate the CPU architec- ummg accuracv. The declslon to use as- vtces desIgned to ?alk” via serial links ture. For example, onlv two CPU ar- sembly tnstead of a high-level language with other processor. Current exampies chltectures implement an on-chip 1% stemmed drectly from the need to con- include Microwire (Xatlonai Semcon- port. If your choice of architecture pre- trol program-execunon time. I had ne;- ductor), SPI (~Motorolaj, and most re- cludes use of these architectures, then ther the tme nor the m&anon to hand- cently Echelon’s INeuron chps. In all cas- your only opuon IS to tmpiement the tune high-level code. es, the goal is the same: to reduce the protocol in software. Havmg made the decision to use as- wiring and pmcount necessary for a par- The sobare lmpiementatlon of the sembly language, I faced mv neaxt prob- allel data bus. It simply does not make 1% protocol discussed m this article lem: Could I make the code portable? came about as a result of an ~mphclt Intel offers a plethora ot CPU and em- Mitch 1s a senior strategzc development challenge during a staff meetmg. One bedded-controller architectures. Would enguzeer for Intel and can be contact- of our managers proposed that we hire it be possible to make the code some- ed at 5000 W Chandler Blud.. Cban- a consultant to write a software 1% driv- what portable between disparate as- dler AZ 85226 or at mkabn@sedona. er tar the Intel 8OCl86EB embedded sembiv languages? I found mv answer zntel.com processor. Being somewhat new to the m the use of macros.
69 Dr Dobb j-journal. _fune 1992 Philips Semiconductors
l*C Specific information Programming the i*C Interface
comes to i960 programng, I hJd no protocol. Code not d1rectiy mvoived m AH the basic bu1ldmg blocks of thj problems portmg the core macros. lm&ng the acnons of a hardware 1% I? protocol (watching, welting, and dc port was not wntten as macros. For ex- In9 can be compartmentalized into dk Hardware Dependencies ample. the code necessarv to access the tmct macros. The algorithms that makl A few word5 about the target hardware stack frame IS not written as a macro, up the IlC driver are written with thesg are 1n order before I discuss the code. whereas the code needed to toggle the macros as the fmmework. You don Any 1mplementatlon of the I?C protocol clock line is. Thus was done to Isolate need co understand the mtncac1es of thg requires two open-drain (or open-col- Architecturedependent code sequences I? protocol to port these routines- lector), bidirectional port pins for the from the more generic 1% funcuons. you just need to know how to makf Serial Clock (SCLJ and Serial Data CSDA) lMacros were also not used for ‘.gray ar- your CPU watch, Walt. and do. lines. The code 1n this article was de- eas” such as the shtimg of serial data. For example, a 4,7_uS delay IS a corn s1gned for the 8OCl86EB embedded pr@ which IS both architecture dependent mon event during a transfer. The macn cessor, which has two open-dram ports and physical m nature. The 1% func- %Wazt_4_ i_u.S implements lust such on-chip. The two pms, ~2.6 ECL) and tions that passed the litmus test fell m- delay by usmg the 8086 LOOP instruc P2.7 (SDA), are part of a larger &bit to the three aforementioned categories t1on with a couple of NOPs for tunmg port. Processon wIthout opendram I/O of watchmg, waiting, and domg. see Example l(a). Total execuuon t1mf ports can easdy implement I’C wKh the The .walting” macros provide a fixed- LSreadily calculated from mstrucuon m addition of an eZxtemal open-collector mm~mum time delay They are impie- ing tables. The same macro IS ported t( Iacch. mented usmg a simple LOOP $ delay. the 1960 architecture 1n Example l(b: Two spec1aMuncuon registers, P2PIN The LOOP instructIon decrements the Although I am a neophyte when I and P2LTCH. are used to read and wnce CX register, then branches to the target the state of the port pms. The 8OCl86EB (in thus case 1t.self3 tf the result 1s non- I I allows the spec1aMunct:on registers to zero. The delay 1s (n-1)*15+5 clocks, I Drive SCl_ Low I be located anywhere m either memo- where n 1s the starting value in the CX , ry or I/O space. For this 1mplementa- register. All the delays were calculated non, I chose to leave the registers 1n assuming a ~~-MHZ clock rate (62.5 I/O space, even though this iimted my nanoseconds per clock). The code still choice of instructions. The 80186 ar- works at lower CPU speeds because the chitecture does not provide for read- 1% protocol only specifies mmimum modify-wnte instructIons 1n I/O space tlmmgs. In fact, the delay macros are (an AND to I/O, for example): 1t can only ~‘accurate enough.” providing tlm- Assert Nth Data only load and store (IN and OUT?. So mgs as close as I could get to the spec- 51t on SDA 1 why did I iirmt myself? Agam, I had to ified minimum without undue tunmg. assume the lowest common denoml- The “watching” macros are ‘spin-on- nator for our customers when design- bit” polling loops. These pieces of code Wad 2.35 pS 1ng my code. wait for a transItion on the appropnate +7I. , 12C line to occur before allowing execu- Buildingthe Fmmewark t1on to contmue. There are two polling Early on 1n development. I decided to macros for each of the two I’C sIgna parution my code macros according to lines; one for high-to-low transitions and physical processes mvolved in the 12C one for low-to-high transitions. The
%*DEFINE(Wait_4_i’_uS)i IIWV cx, 5 ; 4 clocks loop $ ; 4*15+5 = 65 clocks nOP ; 3 clocks noP ; 3 clocks ; total = 75 clocks ; 15 * 62.5ns = 4.69uS (close enough)
0-4
No defme(Waltz_4_7_uS,’
lda 0x17, r4 # instruction nay be Issued in parallel # so assume no clocks. Ob: cmpdeco 0, r4 # compare and decrement counter in r4 bne.t Ob I if !=O branch back (predict taken # brancn)
# ?he cmpdeco and bne.t Cogecher take 3 # clocks In parallel Cnmum. # # 0x17 (25 decxml) l 3 = 75 clocks # at 16MHz :h~s 1s 4.69uS
Example 1: cu) 8OCl8G tmplementatzon oj.4 7_US utazt macro: (b) 8096OCA implementation of 4 7-1~5 wazt macro
70 Llr Dobbs Journals June 1992 Philips Semiconductors
12C Specific information Programming the 12C Interface
106~ and master receive functions (List- The inner loop IS responsible for polling of the SCL line that gives rise I ing Two, page 1081, as they represent transmitung the 8 bits of each data byte. an importanc feature of 12C: automatit the needs of most 12C users. The slave Each transmitted bit generates the ap- bit-by-bit baud-rate adjustment. Any df procedure is long and intricate and will propriate data (SDA) and clock (SCL) vice on the IzC bus may hoid the clot not be described here. waveforms whiIe checking for both se- line low m order to stall the bus fc An 12C master transmission proceeds rial wait states and potential bus colli- more rime (a serial wait state). The otl a.5follows: sions. A bus collision occurs when two er devices on the bus are then force masters attempt to gain control of the to poll the SCL line uric11 the slow d< I. The master polls the bus to see if it vice releases control of the clock. is in use. The %Get_SDA_&t macro also fal 2. The master generates a start condi- lh-ee distinct tasks under the category of “watching.” 11 tion on the bus. function is simply to return the state c 3. The master broadcasts the slave ad- are involved in the SDA line without waiting for a trar dress and expects an acknowledge sition. %Get_SDA_Bit LS used pnmanl (ACK) from the addressed slave. to pull the serial data off the bus whe 4. The master transrmts 0 or more bytes implementing the the clock is valid. of data, expecting an ACK following The .‘domg” macros control the stat each byte. of the clock and data lines. As with th 5. The master generates a stop condi- polling macros. there are four types- tion and releases the bus. watching the bus, one for each transition of the XL c SDA lines. The .‘domg ’ macros ar The stack frame for the master trans- waitingfor a specijiic named to reflect the physical operation mit procedure, I~CXA.A~~, includes a they perform. For example, %Drzve far pointer to the message for transrms- amount of time, and SCL_Low always drives the SCL line t sion, the byte count for the message, a low state. %Relea.se_SCL_Higb,on th and the slave address. Far pointers and other hand, relinquishes control of th far procedure calls are used in all the driving the bus SCL line, which may then be pulIed hig procedures. No attempt was made to or driven low by another device on th conform to a specific high-level lan- bus. A read-modify-write operation I guage caUing convention, although such bus simultaneously. The 12C protocol usedfor the bit manipulation so mat th a conversion would be trivial. The pro- handles collisions with the simple rule: other 6 bits of Port 2 are not affecte cedures save only the state of the mcxd- “He who transmits the first 0 on the SDA by the 12C operations. shed segment registers. line wins the bus.” To ensure that we The master transmit procedure per- (the master transmit procedure) own the Getting on the Bus forms error checking on the passed pa- bus, the SDA line is checked whenev- Three procedures were created usm rameters before attempting to send the er transmitting a 1. If a 0 is present, then the macro framework. I’ll describe or message. The maximum message length a collision has occurred (because an- ly the master transmit (Listing One, pag is set at 64 Kbytes by the segmentation other master is pulling the line low), of the 80186 memory space. This re- and the transfer must be aborted. strictton could be removed by mciud- Control is turned over to the outer ing code to handle segment boundanes. loop after the 8 bits of data (or address) The transmit procedure also checks the have been transmitted. The outer loop direction bit tn the slave address to en- immediately checks for an acknowledge sure that a reception was not erro- from the addressed slave. The transfer neously indicated. Errors are reported is aborted if an acknowledge is not re- back to the calling procedure through ceived. At the end of the ACK bit the the AK regrster. (The exact code is in message length counter IS decremented. Listing One.) Control is returned to the inner loop if The first step in sending a message is more data remains, otherwrse a stop con- getting on the 12C bus. The macro dition is generated and the master mu-is- oM~ec~_~or_Br&+-ee simply polls the rmt procedure terminates. bus to determme if any transactions are Registers are used for tntermediate re- in progress. If so, the transmit proce- sult storage throughout the body of the dure aborts with the appropriate error procedure. For example, the AH reg- code. If the bus is free, a start condition ister is used to hold the current value IS generated, The start condition is de- (either address or data) bemg shifted fined as a high-to-low transition of SDA onto the SDA line. This elimmates the with SCL high followed by a 4.7_uS need for local data storage within the pause. These waveforms are easily gen- procedure. erated with the %Dnve_SDA_Low and % WaU_4_ 7-d macros. On the Receiving End All communication on the Ik bus be- The steps involved in an I’C master re- tween the stop and start condiuons, in- ceive transaction are almost identical to cluding addresstng and data, takes place those in transmission: I stop I as an &bit data value followed by an acknowledge bit. This lead to the nat- 1. The master the bus to see tf it Figure 2: Flowcba??jx- PC transmrt ural nested loop structure for the body is in use. procedure. of the procedure: see Figure 2. 2. The master generates a start condi-
71 L3 Dobbk Journal June 1992 Philips Semiconductors
12C Specific information Programming the 12C Interface
non on the bu5 &Ion hss heen generated. 5ee Fqglre for example, replxx the tmimg loop5 j The ma5ter broxica5ts the 5iave ad- 3 The 5b~ve -1ddresa IS tran5mltted u5- \vlth umed uxemipt5 That wry, the CPL’ dress md aspects XI ‘\CK from th mg one iteration ot the rran5mlt proce- could perform useful work durmg the .iddre55ed slave dure5 outer loop Control 15 pa\5ed to pxi5es .&iong the 5ame ime5. the paus- + The master recene5 0 or more bvte the receive loop once the 5lave dcknow- es could be scheduled using a real- ot dam and \ends
the bdst bake bv not 5endmg an ,\Ch b. I &er that of the trdnsmlt procedure. The hgh-level language calling 5tructure. 5 The ma5ter generace J \cop cond I- Inner loop controls the Ltockmg of the The u5e of tImed mtemlpts Jdd5 an non &md reiea5e5 the bus SCL line and the 5hlhq ot rhe 5txxdl do- order of magnitude to the complextv ta otf the SDA lme Into the CPU Eight of the code, but n,ould be worth It for
.I far pointer to the receive butfer I51 LteKlhons ot the mer loop are performed high-pertormance. real-time 5ystems. pasxcion the stack to the ma5ter rc ro receive each bvte The outer loop cetve procedure. The remainder ot th >tores the received bate II-I the buffer. Conclusion pammeter5--slave addres5 and me> decrements the byte count, then sencL> 1% IS not the onlv game m town when sage count-xe ldentlcai between th an XK to the slave. The la5t data byte In comes to serial protocols. HopeMy, ~0 procedures The received me55ag IS sqgaited by not 5endq an ACK some ot the technques presented here length 15 fiixed At 6+ Kbvtes. +qun bt wil carry over Into the development of c3use of 5egmentation The error-chech Using the Procedures other ,xmuiated” senai protocols, such mg, bus-a~~aMxi~tv >ensmg, Jnd \tan Ll5tmg Three (page 110) \hows J short JS those targeted at the home-automd- condltlon generJtlon sectIons ot th progrxn that u5e5 both the ma5ter trxx- tlon market. Who knows, maybe some- receive procedure xe lifted verbxlr rnlt and tnaster receive procedure5 The dav J snippet of mv code mdv find 1t.5 from the tran5mlt code cxil to procedure IX_XMT dlspiavs tie way Into a trulv Intelligent dishwasher. The structure of the receive proce lvord ‘WS-” on a four-character. 5ev- I’ll be waltmg dure differs 5hghtly once the start con en-segment dl5piav controlled bv the %A1064 1% compatible dispiav driver. References The time of dav IS read tram the Z2C Bus SpeczJic~~twz. PhIlips Corpora- Start fYFS%3 real-time clock by the cait to tion cundated) Byte = l*C address, I procedure IX_RECV Please note that Interrupts must be di5abled durtng the execution ot both procedures. .&n mterruptlon at an m- oppomme time cwhen the ma5ter IS not In control of the clock) could cause the bus to hxq It you need to service m- terrupts perIodically, then enable them Reprinted with permission of Dr. only when the clock 15 driven low. Dobbk Journal, 1992 These procedure5 have heen rested Entweccmfeflts copyright * 1992 on a wide armv ot 1% device5 mngmg by M6T Pubitsh#ng, IX unless otnelwlae notao o” 3peclflC artIclea. trom senat EEPROMs to vow svnthe- All rights resected. slzer5. .So compatlbllitv problems have heen seen to date.
Enhancing the Code l’w kIcked around many &25 for en- hxxxng the 1% procedures. ‘t’ou could.
All the basic No ACK Send ACK building block oj*
1 Byte ++ the 12Cprotocol N=l (watching, waiting, and doin& can be stop compatimentalized Philips Semiconductors 93 aNorth American PhIlIps Company 811 E. Arquas Avenue Figure 3: Flowchar? Jor IX receufe into distinct macros P 0. Box 3409 procedure SurtnVvale, Callfornta 94088-3409
72 l*C Specific information Exploring l*C
erial data buses are a well- proven tool in embedded systems. When you are com- municating with slow per- The choice of bus ipheral devices, serial buses areS often often more convenient and less and protocol expensive than parallel buses. Addi- tionally, a serial interface featuring a dependsat least as UART or similar intermediary chip can also serve to isolate the CPU from much on the noise and line glitches that might bring down the house if they were to occur on system’s software the prczessor bus. Peripherals can usu- ally be controlled over a much greater as it does on the distance by a serial bus. The serial ap- proach offers greater resilience and manufacturer’s noise immunity. The price you pay for the conve- data sheets. nience is a slower transmission rate and, possibly, the need for added interface serial buses. Both buses are popular, but circuitry at higher voltages. Many pr- each exhibits severly constrained per- ipheral devices, however, are not in con- formance in large networks. SPI, as em- stant communication with the CPU and bodied in the Motorola 6800 family, are not greatly affected by a slower bus. was designed primarily for one-on-one On the hardware side, any added inter- exchanges between two devices. Simi- face circuitry required for serial-bus larly, the multidrop approach used in support is frequently compensated for various 805 I family members as well as by the resulting simplicity and tighter in the 68HC 11 and various UART pinout of the serial peripherals. chips hnds its broadest expression in RS485/422 halfduplex transmissions. CHOOSlN6THE PROPERROUll Multidrop has no deterministic arbitra- aving decided that a serial bus tion scheme between multiple masters, makes sense for your applica- leaving it mainly suitable for single- H tion, your next task is to select master multiple-slave situations. (For the most appropriate bus and protocol. more on multidrop, see Jack Woehr’s Here, as with rapid transit, your choice article, “Multidrop Processing, ” Em- should be determined by your destina- bedded Systems Programming, March tion. Contrary to what some people may 1990, pp 58-67-ed.) A different ap- tell you, the choice of bus and protocol proach is to use a three-wire protocol depends at least as much on the nature called MicroWire, available from Na- of the system’s software as it does on the tional Semiconductor in Santa Clara. manufacturer’s data sheets. Calif., which is fine for use with addres- Consider, for example, the serial-pe- sable peripherals, but requires an indi- ripheral interface (SPI) and multidrop vidual chip select for each device ad-
73 lips Semiconductors
l*C Specific information Exploring l*C Exploriizg 2 IC
dressed. The added wiring offers no up a multtple-master. multiple-slave advantage to developers, and the bus of- commumcattons bus wtth conflict arbi- fers nothing towards achievmg multi- tration. usmg only twtsted-patr wirmg pie-mastermg capabilities. to connect the processors and peripher- Open-collector One of the more versattle options als. Philips/Signettcs has moved tosup- available to developers IS the PC bus port this protocol (which is quote popu- configuration promulgated by Philips/Signetics m lar in Europe) with a large assortment Sunnyvale. Calif. IT allows you to set of interesting doodads. and is actively means that the output stage can Figure 1 only pull the node Generation of acknowledge. to ground.
encouragmg other manufacturers to jotn m the fun. If your next design fea- tures a mrcroprocessor that supports ---v- --- PC or you are prepared to implement _.- - B - - - - PC in software using a PIA as this arti- cle illustrates. your reward could be a decreased chip count and lower power consumption-along wtth a comfort- able distributed-programming model for peripheral devices. PC is more flexible than the proto- cols noted above. since only two wires are required to service a large network of addressable masters and addressable slaves. A third wire may be added if in- terrupt service is required. though Phi- lips/Signetrcs mrcroprocessors featur- ing PC support feature on-chip cir- cuttry and are capable of interruptmg the processor upon receipt of a valid address.
HOW 1% WORKS he PC bus consists of two lines: serial clock (SCL) and serial T data (SDA). The beauty of the PC bus is that each of these lines is bi- directional. Bidirectional means that everything on the bus 1s equal, unlike most other serial-peripheral busses such as SPI or MicroWire, which have dedi- cated inputs and outputs. Each PC transaction line (SCL and SDA) is an open collector of output and input. The
74 Philips Semiconductors
l*C Specific information Exploring l*C
pullup reststor is external. ed the IX bus using a couple of the pins Programmmg bulietm board service at Open-collector (actually, they are on an 8255 peripheral L/O chtp. Conse- (415) 905-2689-ed.1 CMOS. so &open dram” is more appro- quently, the bufk of the example appii- By definition. a slave can be any pro- priate) contiguratron means that the cation code 1s simple setup and house- cessor or peripheral that responds to the output stage can only pull the node to keeping routines. (Steven R. Wheeler’s master. Slaves all have unique, 7-bit ad- ground. A passive resistor pulls the node example appiicatlon iistmg was a bit dresses that are based on the device type high, which means that any number of too long to run in this issue. interested and the wiring of address pins on the open collector outputs can be connected readers may download It ,fi-om the li- chip. All I*C peripherals have the top together with no deiiterious results. be- brar,v 12 of CLMFORUM on Compu- nibble of an address built in. For the cause tt IS impossible to pull more cur- Serve or j-om the Embedded Systems PCFgj74 I/O-port expanders we’re us- rent through the reststor than any one output will produce. Tying outputs to- gether will produce disastrous results if the same procedure is tried with stan- dard TTL outputs. If some of the out- Figure 2 Start and stop conditions. puts go high and some are low. the cur- rent IS unlimited and the logic level of the output ~111be in an indetermmate SDA state. Tying open-collector outputs to- gether is also known as “wtre ORmg”be- SCL cause if either A or B goes low, so does the single-output line. Start stop The PC bus speed is specified at a maximum SCL rate of 1OOkHz SCL, which, admittedly, is not blazingly fast. The speed limit stems from the meager ability of a pullup resistor to source cur- rent to a long distributed line of pert- pherals. The lo-microsecond period al- lows plenty of time to charge the parasitic capacitance of the wires. (The maximum spectfied wtre capacttance ts 400 pF.1
PUITING IT TOGETHER Ithough FC supports multi- ple-master operation, here we A use single-master, single-slave transactions to keep the example code simple. The master. as you might imag- me, IS defined as the unit that initiates the data transfer and generates the SCL srgnal. (In a multimaster system, each master would be responstble for generating its own SCL signal.) In our exampIe. based strongly on the destgn of one of our company’s smgle-board com- puters, the processor doesn’t directly support I’C. Instead, we’ve implement-
75 Philips Semiconductors
l*C Specific information Exploring l*C Expbriig IC2
ing as examples, the address is OlOOxxx. simple definition of the start of an PC purpose integrated circuits using PC in- The xxx indicates the address selected transaction-SDA goes from high to clude LCD drivers, digital-toanalog by the state of the three address pins on low when the clock is high. converters, SRAMs, EEPROMs, and a the peripheral. The end of a transaction is equally RAM clock/calender. PC serial transactions are always simple to detect: SDA goes from low to PC is very popular in Europe, where eight bits of data from the transmitter high when SCL is high. This cycle Philips has been aggressively marketing followed by a ninth ACK bit from the re- leaves SDA and SCL in the high state, this flexible method of extending pe- ceiver. The first step in any PC data which is necessary if any other open- ripheral support to control projects, and transfer is to send the address of the collector PC peripheral wants access to it is currently catching fire on this side slave on the SDA line. This act might the bus. Figure 2 illustrates the start of the Atlantic. It seems reasonable to seem confusing, since we seem to be and stop conditions of an FC bus expect that, given the burden of printed- mixing 7-bit addresses with g-bit data. transaction. wire requirements for embedded sys- In practice, it’s quite easy to work with: tems based on increasingly wider chip addresses are always seven bits long, ADDITIDNAL DESIGN RDDTES buses, more and more designers seeking and the eighth bit is used to determine syou’ve seen, the PC protocol economy of means will be attracted to whether the operation is a read or a is easy to work with and rela- the economy of PC. write. For example, upon transmitting A tively simple to implement, 01ooo0O1 to the PCF8574, the slave, as- even if you’re not using a processor that suming it exists on the bus and is directly implements it. If you’re not strapped to address Ooo, will respond planning to use Philips/Signetics mi- Steven Sarns is the president of Vesta with a low on the SDA line after the croprocessors with onboard PC support Technology in Wheat Ridge, Cola, He master has finished with its last (eighth) (such as the 68070 or various members is a member of Mensa, Intertel, and the data bit. The master leaves the line of the 805 1 family), you can still use the Michigan Society of Professional En- high. If it doesn’t find a slave with ad- wide variety of available peripheral gineers. Sarns is also a founding mem- dress 10000, the data line ~111 remain chips. ber of the Denver chapter of the Forth high and a failed communication at- The number of integrated circuits Interest Group. tempt can be detected. using the PC serial bus is increasing all If a slave is connected, it begins put- the time. Application-oriented inte- Jack Woehr is a senior project manager ting data on the SDA line as soon as it grated circuits that support PC include at Vesta Technology Inc, in Wheat has detected that the eighth bit is set a voice sythesizer, a transc&er for IR Ridge, Colo. He is a Chapter Coordin- (which is a read request). The SDA line remote control, several digital tuning atorfor the Forth Interest Group and is is driven to the data level when the SCL circuits for computer-controlled televi- currently a member of the X3Jl4 Tech- line is low. Data is read when SCL is sion, several audio processors, PLL fre- nical committeefor ANS Forth. He can high, so SDA must not change when quency synthesizers, tone generators, be reached by E-mail as [email protected] SCL is high. This protocol leads to a and frequency synthesizers. General- .ca.us or as VESTA on GEnie.
Reprinted with permission from EMBEDDED SYSTEMS PROGRAMMING, September 1991 0 I991 MILLER FREEMAN PUBLICATIONS 76 Philips Semiconductors
l*C Specific information Bit-Banging Serial Ports
Bit-Banging Serial Posts
hey say that necesstty IS to be transmitted. the mother of inventron. The method presented here provides and it certainly seems to an array of structures (in the cede or be the case in embedded The shift (or PROM space) that defines the transmit systems work. No sooner sequence bit by bit and uses a pointer to doT you accomplish the tmposstble in one rotate) operation this array as the only controlling eie- project than your boss or customer asks merit. This means that only two bytes of you to do it agam, only faster and is the first thing scarce internal RAM is used. cheaper this time. Even when you’re working with low-cost mtcrocontrollers. that comes to there’s still that mcenttve to make things cheaper through magtc software. mind when you’re Performmg mrracies through soft- ware trickery IS a skill that a11 embed- designing code to ded developers must cultivate. An op- portumty for me to practice such tricks provide a serial came m the form of a project using the Signettcs 8x75 I mtcrocontroller. The data output. 8x75 1is an 805 1dertvattve that has no internal serial port-no attachment of My project was required to operate SBUF shift registers to RxD and TxD. dt 9600 baud. This rate gives a per-bit no diverston of timers to baud rate pac- time of 104 mtcroseconds. or IO4 cycles mg, no serial interrupts. But the chip is if you’re using a 12-AMHz part. The ap- low-prtced and offers a small-fcotprmt, plication in question had plenty of other and hence IS desirable in many applica- acttvtties as well as a sertal port (such as ttons. Where the price or size outweighs reading a serial analog-to-digital con- the need for a simple sertai port, one verter. performing averages. and so on ), must be butlt out of firmware by appro- so it was imperative that the sertal port priatelycontrolling a single bit m a port. handling take an absolute munmum of The practice is affecttonateiy known as ttme. Since I chose to execute in a tixed- tibu-bangmg.” time ioop (to avotd interrupt overhead), The approach I’ll describe here has rt was dfso a godi that the code take a the advantages of being simple and fast. fixed amount of time regardless of the There is no transmtt state-machine, no current transmrt state. spectai provtston for start and stop bits. 2nd it takes less than two dozen ma- THE STRUCTUREPOINTER SOLUTION chine cycles for each bit. It has a further enerally, the shift (or rotate) Advantage that the data doesn’t need to operation is the first thing that be specrafly orgamzed for transmtttmg. G comes to mind when you’re de- That 1s. the bits that are adjacent m the signing code to provtde a sertai data out- transmit data stream don’t need to be put-the format of the data suggests adjacent when they are stored m mem- such a scheme. With this approach. ory. This soiutton IS for a transmttter however. special states and a counter are only, but I have used a stmtlar procedure needed to provide the start and stop bits for receiving. dnd to sequence through the set of bytes
77 Philips Semiconductors
i*C Specific information Bit-Banging Serial Ports
The structures are referenced con- ated by changing the pointer to point to for the work described here. The 8x75 1 secutlvely. Each gves the source of a bit the first structure. Start and stop bits does not support external RAM. so the to be transmitted and a flag to indicate are not distinguished from data bits. small model is used. (If the transmit whether the pointer should be increased The bit update prtion of the code is data resided in external RAM. the algo- to point to a new bit. The transmission is constant-time, and the pointer update rithm could be applied, but would be terminated by having a structure that can be easily padded if necessary to expected to take a little longer to refers to an *idle” bit and does not in- achieve this part of the goal. execute.) crease the pointer. Transmission is initi- Franklin’s C5l compiler was used THE DECLARATIONS he structure that provides indi- T vidual bit definitions is: // tranat bit-reference structure struct BR ; unsigned char Index : unsigned char mask : unsigned char bump :
No memory is allocated by this defini- tion-it is essentially a typedef. The ac- tual allocation and initialization are provided by the definition (in a header file, send _ seq.h, in this case) of the Bit- Refarray:
code struct BR BitRef[41] = ’ 1 ;
wherethedetails will be given in a mo- ment. The pointer is defined as:
I/ pointer to BitRef structure array data struct BR code *BR_ptr
In Franklin’s C5 I, the declaration tokens are interpreted as follows. In the struct BRdeclaration. the token code as- signs the BitRef array to program mem- ory (which is then accessed with themovc instruction).Inthe *BR_ptrdeciaratIon, the token codeimpliesthatBR_ptrisex- cluslvelyapointertotheprogramspace. so~trequiresonlytwo bytes to becom- pletely defined. The token data causes the compder to store the pointer value m
7a Philips Semiconductors
l*C Specific information Bit-Banging Serial Ports
internal RL41M.(Since I was using the The *bump” ISa flag that continues small model, this would have been the the transmtsston. When rt IS finally 0, default storage anyway.) the serial output sequence ~111stop. The Index entry in each structure al- lows the serial bit to be selected from an 3 , b01000000, 1. I/ 0 fixed THE CODE array of bytes called transmlt[4] in my 3 b10000000 1. /I 1 stop bit he code fragment that accom- case. The transmtt array can. if desired, 3 b10000000 0 /I 1 idlebit plishes the transmtssion IS: be set up to literally overlay all of the T internal memory, so that the maximum (a) VansBit = &random access” can be achteved. This (The *‘masks- are given in binary nota- (bit)( transmit[ BLptr-1index ] was not necessary in my c3se. tion. [See “.A Binary Upgrade jbr C, ” 8 BLptr-)mask ) The physical port pm to be exercised pp. 60-62.-Ed.] Because of myassem- (b) if ( BR_ptr-)bump ) ISdefined: bler and hardware background. thts no- BR_ptr++
/* transmit 1s on P3 3 *I The program sequence for sectIon (a) sblt TransBlt = OxB3 looks like this:
THE STRUCTURE INITIAMATION The “bump” is a BR_ptr-1index ach bit to be transmrtted is de- -- looks up current index, then used in fined by an index and mask. flag that continues transmit[index] E These are irntiaiized rn the Bit- -- to get byte with desired bit. Ref structure so that characters can be the transmission. then ANDed with mask formed as desired in the output btt BR_ptr-)mask stream. The index IS the offset wtthin When it finally -- to get zero~nonzero value. which the transmit array. The mittaiizatton n-r (bit)(value 8 value) my case, for a sequence of 40 bits mak- reaches 0, the -- 1s then cast to a bit for output ing up four characters. was: TransBlt = bit serial output -- to port pin, the ultimate goal. code struct BR8itRef[41] = , 11 index mask bump comnent sequeflce will The pointer IS lncrcdsedin (b),depend- tngon the value of BR__Ptr-jbump. 2~s in- 3 b01000000 1. I 0 start bit stop. dicated earlier. this is aiwavs one except in the last structure, so the serial trans- 'I b00000001 , I, /'I 06 tation 1s natural for me tn bit mask mrsston always proceeds to the defined 1 b00000010 I, I/ 07 references.) end. The statement: 1 b00000100 I, f/ 08 The *‘index” refers. as menttoned. to 1 b00001000 1. 1 09 the element of “transmit” in which the BR_ptr = &BitRef[40] 1 b00010000 1. /I 010 bit restdes. Some mitializatton code has 1 b00100000 1. I/ 011 guaranteed that the upper two bits of in lnitiaiization ~111 keep the transmtt- transmlt[3] wtll be IO. so that they can ter offdurmg startup, and: 3 b10000000 I, (1 1 fixed be referred to for start and stop bits and 3 b10000000 1. '1 1 fixed for any tixed-vaiue bits that happen to BR_ptr = BitRef 3 b10000000 I, / 1 stop bit be m the data stream (in my case, the fixed bits are used to indicate data byte IS used to initiate a transmtssron 3 b01000000 I, '/ 0 start bit order). sequence.
79 Philips Semiconductors
12C Specific information Bit-Banging Serial Ports
The previous transmitting code corn- The assembly language code reveals plies. with only a Me manual assls- that the mechamsm is pretty efficient. tance, to: This method is in use in one of my cli- ents’ prducts and has proved effective. TransEit = (bit)( transnnt[ BR_ptr-Findex ] 8 BR_ptr-Unask ) GlT4ANGlNG WGGKS WV DPL.BR_ptr+OlH his bit-banging solution serves MIV 0PH,Bfl_!~tr to provide serial transmission m CLR A T an embedded system that has WC A.@A+DPlR no hardware specifically dedicated to ADD A,ntransmit [he function. Though alternate and KIV RO A more traditional solutions would have h!OV A.&%0 worked. the need for speed encouraged KIV R7.A development of a code-pomter-based INC DPTR solution that works fast enough m this CLR A case and takes up only two internal Mavc A,@A*DPTR RAM bytes for operation. I hope that ANL A.R7 thispresentation will prove to be useful ADD A.nOFFH for you. MOV TransB1t.C If ( BRdtr-)bm ) INC DPTR CLR A Mark Gardner 1s a consultant based in Move A,@A+DPTR Acton, CA. He has been designing JZ XDOII hardware and writingfirmwarefor em- BR_ptr++ bedded svstems for over 15 years. He MOV A.aD3H has an h4S in eiectronx engineering ADD A.BR_ptr+OlH jborn the University of Illinois. WV BR_ptr+OlH,A CLR A ADDC A.BR_ptr For more mformanon. contact: MOV BRatr.A ~cooll PhilipsSemiconductors 81 I E. Arques Avenue P.O. Box 3409 Sunnyvale. CA 94088-3409 (408) 991-352
ReprInted wnh permissIon from EMBEDDED SYSTEMS PROGRAMMING, September 1993 0 1993 MILLER FREEMAN INC. 80