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Philips Semiconductors 12C Specific information Programming the 12C Interface EMBEDDED SYSTEMS Whenintedigent devices need to communicate MitchellKahn he Inter-Integrated Circuit Bus group. I took excepuon (although not (“1% Bus” for short) IS a two- verballv!) to his suggestIon. .A weekend wire, synchronous, serial inter- of intense hacking later, I presented the face designed pnmanly for first prototype of the driver. My reward? commumcation between intel- 1got to write a generic version of the Tligent IC devices. The 1% bus offers sev- dnver for general distnbutlon. eral advantages over ,.traditlonal” serial interfaces such as LMicrowlre and Design Tmde-offs RS-232. Among the advanced features Three distmct tasks are mvolved m im- of 1% are multimaster operauon, auto- plementmg the 12C protocol: watching matic baud-rate adjustment, and .‘plug- the bus, waltmg for a spectiic amount Jnd-play ’ network extensions. of time, and driving the bus. This be- ,Mention the 1% bus to a group of came apparent when I flowcharted 1 Amencan engmeers and you’ll likely get byte of a typical bus transaction: see hit with an abundance of blank stares. Figure 1. The time delays associated I say Amencan engmeers because un- with creatmg the bus waveforms would tll recently the 12C bus was pnmanly a normally have been relegated to the European phenomenon. Withm the last 8OCl86EB’s on-chip timers. I could not, year, however, Interest m I‘C in the however. assume that the end users of Unite ,d States has risen dramatIcally. my code would be able to spare a urner Embe tdded systems designers are real- for the software 12C prt. I had to forego zmg the cost. soace. and Dower sav- the elegance (and to some extent ac- mgs-afforded by’robust se&l mterchip economic sense to route a full-speed curacvj of the on-chip timers for the protocols. parallel bus to a slow penpherai. sledgehammer approach of software The idea of serial Interconnect be- Unfortunately for most serlal-bus- timing loops. Luchlv, the IlC protocol tween integrated clrcults IS not new. capable devices, the choice of a bus IS extremely forglvmg with regard to Many semconductor vendors offer de- protocol wdl dictate the CPU architec- ummg accuracv. The declslon to use as- vtces desIgned to ?alk” via serial links ture. For example, onlv two CPU ar- sembly tnstead of a high-level language with other processor. Current exampies chltectures implement an on-chip 1% stemmed drectly from the need to con- include Microwire (Xatlonai Semcon- port. If your choice of architecture pre- trol program-execunon time. I had ne;- ductor), SPI (~Motorolaj, and most re- cludes use of these architectures, then ther the tme nor the m&anon to hand- cently Echelon’s INeuron chps. In all cas- your only opuon IS to tmpiement the tune high-level code. es, the goal is the same: to reduce the protocol in software. Havmg made the decision to use as- wiring and pmcount necessary for a par- The sobare lmpiementatlon of the sembly language, I faced mv neaxt prob- allel data bus. It simply does not make 1% protocol discussed m this article lem: Could I make the code portable? came about as a result of an ~mphclt Intel offers a plethora ot CPU and em- Mitch 1s a senior strategzc development challenge during a staff meetmg. One bedded-controller architectures. Would enguzeer for Intel and can be contact- of our managers proposed that we hire it be possible to make the code some- ed at 5000 W Chandler Blud.. Cban- a consultant to write a software 1% driv- what portable between disparate as- dler AZ 85226 or at mkabn@sedona. er tar the Intel 8OCl86EB embedded sembiv languages? I found mv answer zntel.com processor. Being somewhat new to the m the use of macros. 69 Dr Dobb j-journal. _fune 1992 Philips Semiconductors l*C Specific information Programming the i*C Interface comes to i960 programng, I hJd no protocol. Code not d1rectiy mvoived m AH the basic bu1ldmg blocks of thj problems portmg the core macros. lm&ng the acnons of a hardware 1% I? protocol (watching, welting, and dc port was not wntten as macros. For ex- In9 can be compartmentalized into dk Hardware Dependencies ample. the code necessarv to access the tmct macros. The algorithms that makl A few word5 about the target hardware stack frame IS not written as a macro, up the IlC driver are written with thesg are 1n order before I discuss the code. whereas the code needed to toggle the macros as the fmmework. You don Any 1mplementatlon of the I?C protocol clock line is. Thus was done to Isolate need co understand the mtncac1es of thg requires two open-drain (or open-col- Architecturedependent code sequences I? protocol to port these routines- lector), bidirectional port pins for the from the more generic 1% funcuons. you just need to know how to makf Serial Clock (SCLJ and Serial Data CSDA) lMacros were also not used for ‘.gray ar- your CPU watch, Walt. and do. lines. The code 1n this article was de- eas” such as the shtimg of serial data. For example, a 4,7_uS delay IS a corn s1gned for the 8OCl86EB embedded pr@ which IS both architecture dependent mon event during a transfer. The macn cessor, which has two open-dram ports and physical m nature. The 1% func- %Wazt_4_ i_u.S implements lust such on-chip. The two pms, ~2.6 ECL) and tions that passed the litmus test fell m- delay by usmg the 8086 LOOP instruc P2.7 (SDA), are part of a larger &bit to the three aforementioned categories t1on with a couple of NOPs for tunmg port. Processon wIthout opendram I/O of watchmg, waiting, and domg. see Example l(a). Total execuuon t1mf ports can easdy implement I’C wKh the The .walting” macros provide a fixed- LSreadily calculated from mstrucuon m addition of an eZxtemal open-collector mm~mum time delay They are impie- ing tables. The same macro IS ported t( Iacch. mented usmg a simple LOOP $ delay. the 1960 architecture 1n Example l(b: Two spec1aMuncuon registers, P2PIN The LOOP instructIon decrements the Although I am a neophyte when I and P2LTCH. are used to read and wnce CX register, then branches to the target the state of the port pms. The 8OCl86EB (in thus case 1t.self3 tf the result 1s non- I I allows the spec1aMunct:on registers to zero. The delay 1s (n-1)*15+5 clocks, I Drive SCl_ Low I be located anywhere m either memo- where n 1s the starting value in the CX , ry or I/O space. For this 1mplementa- register. All the delays were calculated non, I chose to leave the registers 1n assuming a ~~-MHZ clock rate (62.5 I/O space, even though this iimted my nanoseconds per clock). The code still choice of instructions. The 80186 ar- works at lower CPU speeds because the chitecture does not provide for read- 1% protocol only specifies mmimum modify-wnte instructIons 1n I/O space tlmmgs. In fact, the delay macros are (an AND to I/O, for example): 1t can only ~‘accurate enough.” providing tlm- Assert Nth Data only load and store (IN and OUT?. So mgs as close as I could get to the spec- 51t on SDA 1 why did I iirmt myself? Agam, I had to ified minimum without undue tunmg. assume the lowest common denoml- The “watching” macros are ‘spin-on- nator for our customers when design- bit” polling loops. These pieces of code Wad 2.35 pS 1ng my code. wait for a transItion on the appropnate +7I. , 12C line to occur before allowing execu- Buildingthe Fmmewark t1on to contmue. There are two polling Early on 1n development. I decided to macros for each of the two I’C sIgna parution my code macros according to lines; one for high-to-low transitions and physical processes mvolved in the 12C one for low-to-high transitions. The %*DEFINE(Wait_4_i’_uS)i IIWV cx, 5 ; 4 clocks loop $ ; 4*15+5 = 65 clocks nOP ; 3 clocks noP ; 3 clocks ; total = 75 clocks ; 15 * 62.5ns = 4.69uS (close enough) 0-4 No defme(Waltz_4_7_uS,’ lda 0x17, r4 # instruction nay be Issued in parallel # so assume no clocks. Ob: cmpdeco 0, r4 # compare and decrement counter in r4 bne.t Ob I if !=O branch back (predict taken # brancn) # ?he cmpdeco and bne.t Cogecher take 3 # clocks In parallel Cnmum. # # 0x17 (25 decxml) l 3 = 75 clocks # at 16MHz :h~s 1s 4.69uS Example 1: cu) 8OCl8G tmplementatzon oj.4 7_US utazt macro: (b) 8096OCA implementation of 4 7-1~5 wazt macro 70 Llr Dobbs Journals June 1992 Philips Semiconductors 12C Specific information Programming the 12C Interface 106~ and master receive functions (List- The inner loop IS responsible for polling of the SCL line that gives rise I ing Two, page 1081, as they represent transmitung the 8 bits of each data byte. an importanc feature of 12C: automatit the needs of most 12C users. The slave Each transmitted bit generates the ap- bit-by-bit baud-rate adjustment. Any df procedure is long and intricate and will propriate data (SDA) and clock (SCL) vice on the IzC bus may hoid the clot not be described here. waveforms whiIe checking for both se- line low m order to stall the bus fc An 12C master transmission proceeds rial wait states and potential bus colli- more rime (a serial wait state). The otl a.5follows: sions.

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