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Resonance-Enhanced Waveguide-Coupled Silicon-Germanium Detector L
Resonance-enhanced waveguide-coupled silicon-germanium detector L. Alloatti and R. J. Ram Citation: Applied Physics Letters 108, 071105 (2016); doi: 10.1063/1.4941995 View online: http://dx.doi.org/10.1063/1.4941995 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/108/7?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Waveguide-coupled detector in zero-change complementary metal–oxide–semiconductor Appl. Phys. Lett. 107, 041104 (2015); 10.1063/1.4927393 Efficient evanescent wave coupling conditions for waveguide-integrated thin-film Si/Ge photodetectors on silicon- on-insulator/germanium-on-insulator substrates J. Appl. Phys. 110, 083115 (2011); 10.1063/1.3642943 Metal-semiconductor-metal Ge photodetectors integrated in silicon waveguides Appl. Phys. Lett. 92, 151114 (2008); 10.1063/1.2909590 Guided-wave near-infrared detector in polycrystalline germanium on silicon Appl. Phys. Lett. 87, 203507 (2005); 10.1063/1.2131175 Back-side-illuminated high-speed Ge photodetector fabricated on Si substrate using thin SiGe buffer layers Appl. Phys. Lett. 85, 3286 (2004); 10.1063/1.1805706 Reuse of AIP Publishing content is subject to the terms at: https://publishing.aip.org/authors/rights-and-permissions. IP: 18.62.22.131 On: Mon, 07 Mar 2016 17:12:57 APPLIED PHYSICS LETTERS 108, 071105 (2016) Resonance-enhanced waveguide-coupled silicon-germanium detector L. Alloattia),b) and R. J. Ram Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA (Received 5 January 2016; accepted 3 February 2016; published online 16 February 2016) A photodiode with 0.55 6 0.1 A/W responsivity at a wavelength of 1176.9 nm has been fabricated in a 45 nm microelectronics silicon-on-insulator foundry process. -
Nanoelectronics the Original Positronic Brain?
Nanoelectronics the Original Positronic Brain? Dan Hammerstrom Department of Electrical and Computer Engineering Portland State University Maseeh College of Engineering 12/13/08 1 and Computer Science Wikipedia: “A positronic brain is a fictional technological device, originally conceived by science fiction writer Isaac Asimov “Its role is to serve as a central computer for a robot, and, in some unspecified way, to provide it with a form of consciousness recognizable to humans” How close are we? You can judge the algorithms, in this talk I will focus on hardware and what the future might hold Maseeh College of Engineering 12/13/08 Hammerstrom 2 and Computer Science Moore’s Law: The number of transistors doubles every 18-24 months No discussion of computing is complete without addressing Moore’s law The semiconductor industry has been following it for almost 30 years It is not really a physical law, but one of faith The fruits of a hyper-competitive $300 billion global industry Then there is Moore’s lesser known 2nd law st The 1 law requires exponentially increasing investment And what I call Moore’s 3rd law st The 1 law results in exponentially increasing design errata Maseeh College of Engineering 12/13/08 Hammerstrom 3 and Computer Science Intel is now manufacturing in their new, innovative 45 nm process Effective gate lengths of 37 nm (HkMG) And they recently announced a 32 nm scaling of the 45 nm process Transistors of this size are no longer acting like ideal switches And there are other problems … 45 nm Transistor -
Which Is the Best Dual-Port SRAM in 45-Nm Process Technology? – 8T, 10T Single End, and 10T Differential –
Which is the Best Dual-Port SRAM in 45-nm Process Technology? – 8T, 10T Single End, and 10T Differential – Hiroki Noguchi†, Shunsuke Okumura†, Yusuke Iguchi†, Hidehiro Fujiwara†, Yasuhiro Morita†, Koji Nii†,††, Hiroshi Kawaguchi†, and Masahiko Yoshimoto† † Kobe University, Kobe, 657-8501 Japan. †† Renesas Technology Corporation, Itami, 664-0005 Japan. Phone: +81-78-803-6234, E-mail: [email protected] read ports. The next section describes their cell topologies. Abstract— This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T II. CELL TOPOLOGIES single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area A. 8T SRAM efficient. However, the readout power becomes large and the (a) cycle time increases due to peripheral circuits. The 10T Precharge Precharge circuit single-end SRAM is our proposed SRAM, in which a dedicated signal MC inverter and transmission gate are appended as a single-end read Bitline leakage port. The readout power of the 10T single-end SRAM is reduced by 75% and the operating frequency is increased by 95%, over the 8T SRAM. On the other hand the 10T differential SRAM can MC Memory cell (MC) operate fastest, because its small differential voltage of 50 mV RWL achieves the high-speed operation. In terms of the power WWL Readout current efficiency, however, the sense amplifier and precharge circuits lead to the power overhead. As a result, the 10T single-end P1 P2 Bitline keeper SRAM always consumes lowest readout power compared to the 8T and the 10T differential SRAM. -
Technology Roadmap for 22Nm CMOS and Beyond
Technology Roadmap for 22nm CMOS and beyond June 1, 2009 IEDST 2009@IIT-Bombay Hiroshi Iwai Tokyo Institute of Technology 1 Outline 1. Scaling 2. ITRS Roadmap 3. Voltage Scaling/ Low Power and Leakage 4. SRAM Cell Scaling 5.Roadmap for further future as a personal view 2 1. Scaling 3 Scaling Method: by R. Dennard in 1974 1 Wdep: Space Charge Region (or Depletion Region) Width 1 1 SDWdep has to be suppressed 1 Otherwise, large leakage Wdep between S and D I Leakage current Potential in space charge region is high, and thus, electrons in source are 0 attracted to the space charge region. 0 V 1 K=0.7 X , Y, Z :K, V :K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V/Na K Wdep I I : K : K 0 0K V 4 Downscaling merit: Beautiful! Geometry & L , W g g K Scaling K : K=0.7 for example Supply voltage Tox, Vdd Id = vsatWgCo (Vg‐Vth) Co: gate C per unit area Drive current I d K –1 ‐1 ‐1 in saturation Wg (tox )(Vg‐Vth)= Wgtox (Vg‐Vth)= KK K=K Id per unit Wg Id/µm 1 Id per unit Wg = Id / Wg= 1 Gate capacitance Cg K Cg = εoεoxLgWg/tox KK/K = K Switching speed τ K τ= CgVdd/Id KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area Achip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/K2 N α/K2 = 1/K2 , when α=1 Power per chip P α fNCV2/2 K‐1(αK‐2)K (K1 )2= α = 1, when α=1 5 k= 0.7 and α =1 k= 0.72 =0.5 and α =1 Single MOFET Vdd 0.7 Vdd 0.5 Lg 0.7 Lg 0.5 Id 0.7 Id 0.5 Cg 0.7 Cg 0.5 P (Power)/Clock P (Power)/Clock 0.73 = 0.34 0.53 = 0.125 τ (Switching time) 0.7 τ (Switching time) 0.5 Chip N (# of Tr) 1/0.72 = 2 N (# of Tr) 1/0.52 = 4 f (Clock) 1/0.7 = 1.4 f (Clock) 1/0.5 = 2 P (Power) 1 P (Power) 1 6 - The concerns for limits of down-scaling have been announced for every generation. -
A Study of the Foundry Industry Dynamics
A Study of the Foundry Industry Dynamics by Sang Jin Oh B.S. Industrial Engineering Seoul National University, 2003 SUBMITTED TO THE MIT SLOAN SCHOOL OF MANAGEMENT IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN MANAGEMENT STUDIES AT THE MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARCHVES JUNE 2010 MASSACHUSETTS INSTiUTE OF TECHNOLOGY © 2010 Sang Jin Oh. All Rights Reserved. The author hereby grants MIT permission to reproduce JUN 082010 and to distribute publicly paper and electronic LIBRARIES copies of this thesis document in whole or in part in any medium now known and hereafter created. Signature of Author Sang Jin Oh Master of Science in Management Studies May 7, 2010 Certified by (7 Michael A. Cusumano SMR Distinguished Professor of Management Thesis Supervisor Accepted by (I Michael A. Cusumano Faculty Director, M.S. in Management Studies Program MIT Sloan School of Management A Study of the Foundry Industry Dynamics By Sang Jin Oh Submitted to the MIT Sloan School of Management On May 7, 2010 In Partial Fulfillment of the Requirements for the Degree of Master of Science in Management Studies Abstract In the process of industrial evolution, it is a general tendency that companies which specialize in a specific value chain have emerged. These companies should construct a business eco-system based on their own platform to compete successfully with vertically integrated companies and other specialized companies. They continue to sustain their competitive advantage only when they share their ability to create value with other eco-system partners. The thesis analyzes the dynamics of the foundry industry. -
AN-Introducing 45Nm Technology in Microwind
Introducing 45 nm technology in Microwind3 MICROWIND APPLICATION NOTE Introducing 45 nm technology in Microwind3 Etienne SICARD Syed Mahfuzul Aziz Professor School of Electrical & Information Engineering INSA-Dgei, 135 Av de Rangueil University of South Australia 31077 Toulouse – France Mawson Lakes, SA 5095, Australia www.microwind.org www.unisa.edu.au email: [email protected] email: [email protected] This paper describes the improvements related to the CMOS 45 nm technology and the implementation of this technology in Microwind3. The main novelties related to the 45 nm technology such as the high-k gate oxide, metal- gate and very low-K interconnect dielectric is described. The performances of a ring oscillator layout and a 6- transistor RAM memory layout are also analyzed. 1. Recent trends in CMOS technology Firstly, we give an overview of the evolution of important parameters such as the integrated circuit (IC) complexity, gate length, switching delay and supply voltage with a prospective vision down to the 22 nm CMOS technology. The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area. Table 1 gives an overview of the key parameters for technological nodes from 180 nm, introduced in 1999, down to 22 nm, which is supposed to be in production around 2011. Demonstration chips using 45-nm technology have been reported starting in 2004. Mass market manufacturing with this technology is scheduled for late 2007. Technology node 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm First production 2001 2003 2005 2007 2009 2011 Effective gate 70 nm 50 nm 35 nm 25 nm 17 nm 12 nm length Gate material Poly Poly Poly Metal Metal Metal Gate dielectric SiO2 SiO2 SiON High K High K High K Kgates/mm2 240 480 900 1500 2800 4500 Memory point (2) 2.4 1.3 0.6 0.3 0.15 0.08 Table 1: Technological evolution and forecast up to 2011 The gate material has long been polysilicon, with silicon dioxide (SiO2) as the insulator between the gate and the channel (Fig. -
The New Era of Scaling in an Soc World
2009 ISSCC The New Era of Scaling in an SoC World Mark Bohr Intel Senior Fellow Logic Technology Development 1 The End of Scaling is Near? “Optical lithography will reach its limits in the range of 0.75-0.50 microns” “Minimum geometries will saturate in the range of 0.3 to 0.5 microns” “X-ray lithography will be needed below 1 micron” “Minimum gate oxide thickness is limited to ~2 nm” “Copper interconnects will never work” “Scaling will end in ~10 years” Perceived barriers are meant to be surmounted, circumvented or tunneled through 2 Outline • Transistor Scaling • Microprocessor Evolution • Vision of the Future 3 Scaling Trends 10 CPU Transistor Count 10 9 2x every 2 years 1 10 7 Microns 0.1 10 5 3 0.01 10 1970 1980 1990 2000 2010 2020 Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor 4 Scaling Trends 10 CPU Transistor Count 10 9 2x every 2 years 1 10 7 Microns 0.1 65nm 10 5 45nm Feature Size 32nm 0.7x every 2 years 3 0.01 10 1970 1980 1990 2000 2010 2020 Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor 5 MOSFET Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W 1/ κ Doping concentration Na κ Voltage V 1/ κ Current I 1/ κ Capacitance εA/t 1/ κ Delay time/circuit VC/I 1/ κ Power dissipation/circuit VI 1/ κ2 Power density VI/A 1 R. Dennard, IEEE JSSC, 1974 Classical MOSFET scaling was first described in 1974 6 30 Years of MOSFET Scaling Dennard 1974 Intel 2005 1 µm Gate Length: 1.0 µm 35 nm Gate Oxide Thickness: 35 nm -
45 Nm Process
INTEL FIRST TO DEMONSTRATE WORKING 45 nm CHIPS New Technology Will Improve Energy Efficiency and Boost Capabilities of Future Intel Platforms Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration January 2006 1 65 nm Status • Announced shipping 65nm for revenue in Oct. 2005 • Two 65nm/300mm fabs shipping in volume (D1D and Fab 12); with two more coming in 2006 • Intel has shipped more than a million dual- core processors made on 65nm process technology • CPU shipment cross-over from 90nm to 65nm projected for Q3/06 2 What are We Announcing Today? • Intel is first to reach an important milestone in the development of 45 nm logic technology • Fully functional 153 Mbit SRAM chips have been made with >1 billion transistors each • The memory cell size on these SRAM chips is 0.346 μm2, almost half the size of the 65 nm cell • This milestone demonstrates that Intel is on track for delivery of its 45 nm logic technology in 2H 2007 3 45 nm Technology Benefits Compared to today’s 65 nm technology, the 45 nm technology will provide the following product benefits: ~2x improvement in transistor density, for either smaller chip size or increased transistor count >20% improvement in transistor switching speed or >5x reduction in leakage power >30% reduction in transistor switching power This process technology will provide the foundation to deliver improved performance/Watt that will enhance the user experience 4 Intel's Logic Technology Evolution Process Name P1262 P1264 P1266 P1268 Lithography 90 nm 65 nm 45 nm 32 nm 1st Production -
Si MOSFET Roadmap for 22Nm and Beyond
Si MOSFET Roadmap for 22nm and beyond December 1６, 2009 Jadavpur University @ Kolkata, India Hiroshi Iwai Tokyo Institute of Technology 1 Outline 1. Scaling 2. ITRS Roadmap 3. Voltage Scaling/ Low Power and Leakage 4. SRAM Cell Scaling 5.Roadmap for further future 2 1. Scaling 3 Scaling Method: by R. Dennard in 1974 1 Wdep: Space Charge Region (or Depletion Region) Width 1 1 SDWdep has to be suppressed 1 Otherwise, large leakage Wdep between S and D I Leakage current Potential in space charge region is high, and thus, electrons in source are 0 attracted to the space charge region. 0 V 1 K=0.7 X , Y, Z :K, V :K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V/Na K Wdep I I : K : K 0 0K V 4 Downscaling merit: Beautiful! Geometry & L , W g g K Scaling K : K=0.7 for example Supply voltage Tox, Vdd Id = vsatWgCo (Vg‐Vth) Co: gate C per unit area Drive current I d K –1 ‐1 ‐1 in saturation Wg (tox )(Vg‐Vth)= Wgtox (Vg‐Vth)= KK K=K Id per unit Wg Id/µm 1 Id per unit Wg = Id / Wg= 1 Gate capacitance Cg K Cg = εoεoxLgWg/tox KK/K = K Switching speed τ K τ= CgVdd/Id KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area Achip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/K2 N α/K2 = 1/K2 , when α=1 Power per chip P α fNCV2/2 K‐1(αK‐2)K (K1 )2= α = 1, when α=1 5 2 Generations k= 0.72 =0.5 and α =1 Single MOFET Vdd 0.5 Lg 0.5 Id 0.5 Cg 0.5 P (Power)/Clock 0.53 = 0.125 τ (Switching time) 0.5 Chip N (# of Tr) 1/0.52 = 4 f (Clock) 1/0.5 = 2 P (Power) 1 6 - The concerns for limits of down-scaling have been announced for every generation. -
Parallel Computing: Multithreading and Multicore We Demand Increasing Performance for Desktop Applications
The Problem Parallel Computing: MultiThreading and MultiCore We demand increasing performance for desktop applications. How can we get that? There are four approaches that we’re going to discuss here: Mike Bailey 1. We can increase the clock speed (the “La-Z-Boy approach”). [email protected] 2. We can combine several separate computer systems, all working together Oregon State University (multiprocessing). 3. We can develop a single chip which contains multiple CPUs on it (multicore). 4. We can look at where the CPU is spending time waiting, and give it something else to do while it’s waiting (multithreading). "If you were plowing a field, which would you rather use – two strong oxen or 1024 chickens?" -- Seymore Cray Oregon State University Oregon State University Computer Graphics Computer Graphics mjb – November 13, 2012 mjb – November 13, 2012 1. Increasing Clock Speed -- Moore’s Law Moore’s Law “Transistor density doubles every 1.5 years.” From 1986 to 2002, processor performance increased an average of 52%/year Fabrication process sizes (“gate pitch”) have fallen from 65 nm to 45 nm to 32 nm to 22 nm Next will be 16 nm ! Note that oftentimes people ( incorrectly ) equivalence this to: “Clock speed doubles every 1.5 years.” Oregon State University Oregon State University Computer Graphics Source: http://www.intel.com/technology/mooreslaw/index.htm Computer Graphics mjb – November 13, 2012 mjb – November 13, 2012 Moore’s Law Clock Speed and Power Consumption From 1986 to 2002, processor performance increased an average of 52%/year which 1981 IBM PC 5 MHz means that it didn’t quite double every 1.5 years, but it did go up by 1.87, which is close. -
A Change of Pace for the Semiconductor Industry?
Technology, Media & Telecommunications A change of pace for the semiconductor industry? pwc A change of pace for the semiconductor industry? Edited by PricewaterhouseCoopers By Werner Ballhaus, Dr Alessandro Pagella and Constantin Vogel All rights reserved. Reproductions, microfilming, storage and processing in electronic media are not permitted without the publisher’s approval. Typesetting Nina Irmer, Digitale Gestaltung & Medienproduktion, Frankfurt am Main Published by Kohlhammer und Wallishauser GmbH, Druckerei und Verlag, Hechingen Printed in Germany © November 2009 PricewaterhouseCoopers refers to the German firm PricewaterhouseCoopers AG Wirtschafts- pruefungsgesellschaft and the other member firms of PricewaterhouseCoopers International Limited, each of which is a separate and independent legal entity. A change of pace for the semiconductor industry? Preface Preface Innovation drives the semiconductor industry, and in turn its chips form the heart of modern industrial societies. Chips are at the essential core of mobile telephones, computers, flat-screen monitors and television sets, a wide range of medical procedures including CT scans, ultrasound and X-rays, and they play an enormous role in today’s sophisticated cars and aircraft. The number of installed semiconductor components expands constantly, so it would be easy to assume that the semiconductor industry is experiencing a golden era. However, despite the increasing demand for chips, hardly any other sector has been hit so hard by the current economic crisis. How will the market for chips develop in the next few years? What business models will prove to be robust during the crisis and beyond? Where are the current opportunities? What are the critical factors of success? This study considers those and other essential questions. -
Intel's Atom Lines 1. Introduction to Intel's Atom Lines 3. Atom-Based Platforms Targeting Entry Level Desktops and Notebook
Intel’s Atom lines • 1. Introduction to Intel’s Atom lines • 2. Intel’s low-power oriented CPU micro-architectures • 3. Atom-based platforms targeting entry level desktops and notebooks • 4. Atom-based platforms targeting tablets • 5. Atom-based platforms targeting smartphones • 6. Intel’s withdrawal from the mobile market • 7. References 1. Introduction to Intel’s Atom lines • 1.1 The rapidly increasing importance of the mobile market space • 1.2 Related terminology • 1.3 Introduction to Intel’s low-power Atom series 1.1 The rapidly increasing importance of the mobile market space 1.1 The rapidly increasing importance of the mobile market space (1) 1.1 The rapidly increasing importance of the mobile market space Diversification of computer market segments in the 2000’s Main computer market segments around 2000 Servers Desktops Embedded computer devices E.g. Intel’s Xeon lines Intel’s Pentium 4 lines ARM’s lines AMD’s Opteron lines AMD’s Athlon lines Major trend in the first half of the 2000’s: spreading of mobile devices (laptops) Main computer market segments around 2005 Servers Desktops Mobiles Embedded computer devices E.g. Intel’s Xeon lines Intel’s Pentium 4 lines Intel’s Celeron lines ARM’s lines AMD’s Opteron lines AMD’s Athlon64 lines AMD’s Duron lines 1.1 The rapidly increasing importance of the mobile market space (2) Yearly worldwide sales and Compound Annual Growth Rates (CAGR) of desktops and mobiles (laptops) around 2005 [1] 350 300 Millions 250 CAGR 17% 200 Mobile 150 100 Desktop CAGR 5% 50 0 2003 2004 2005 2006 2007 2008