25.7 an Integrated Silicon Photonics Technology for O-Band Datacom

An Integrated Silicon Photonics Technology for O-band Datacom

N. B. Feilchenfeld#1, F. G. Anderson#, T. Barwicz, S. Chilstedt#1, Y. Ding#1, J. Ellis-Monaghan#1, D. M. Gill, C. Hedges#1, J. Hofrichter*, F. Horst*, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean#1, M. Nicewicz#1, J. S. Orcutt, B. Porth#1, J. Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci#1, D. Dang#1, T. Doan#1, F. Doany, S. Engelmann, M. Gordon#1, E. Joseph, J. Maling#1, S. Shank#1, X. Tian#1, C. Willets#1, J. Ferrario#1, M. Meghelli, F. Libsch, B. Offrein*, W. M. J. Green, W. Haensch #IBM Systems & Technology Group, Microelectronics Division, 1000 River St., Essex Junction, Vermont 05452, USA IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, USA *IBM Research GmbH, Säumerstrasse 4, CH-8803 Rüeschlikon, Switzerland 1 to GLOBALFOUNDRIES, Essex Junction, Vermont, 05452, USA Tel: (802) 769-7014, Fax: (802) 769-9659, Email: feilchen@us.ibm.com Abstract: A manufacturable platform of CMOS, RF and coupling ratio in a standard optical directional coupler. The opto-electronic devices fully PDK enabled to demonstrate a PDK of this technology also features an electrostatic dis- 4x25 Gb/s reference design is presented. With self-aligned charge (ESD) design kit with fully modeled scalable RC- fiber attach, this technology enables low-cost O-band data- triggered power rail clamps, ESD diodes, ESD gg-NMOS com transceivers. In addition, this technology can offer en- FETs, self-protected FETs, as well as a bipolar ESD clamp. hanced performance and yield in hybrid-assembly for appli- The technology's ESD reference guide helps the user to cations at 25 Gbaud and beyond. choose the desired protection level without adding unneces- Introduction: Monolithic CMOS silicon photonics sary parasitic capacitances and resistances into the signal technology promises single-chip integration benefits of path. unified design verification, wafer-level test and low-cost Shallow assembly [1]. However, to date this approach has not been Trench* Photonic used to manufacture O-band 25 Gb/s coarse wavelength Well Trench Dual Gate Modulator division multiplexed (CWDM) transceivers at the center of Spacer*- Implant standardization for datacom applications. Hybrid integration Halo Modulator promises the advantages of CMOS manufacturing for optical Module components [2], but lacks full electro-optic device and Ge Detector system integration. Here, we present a manufacturable S/D anneal Precision Detector platform of CMOS, RF and optoelectronic devices fully Resistor Implants PDK-enabled to demonstrate a 4x25 Gb/s reference design. Silicide Contact- With self-aligned fiber attach [3,4], this technology enables Thick Al Metals Metal Optical low-cost O-band datacom transceivers. In addition, this Connect technology can offer enhanced performance and yield in hybrid-assembly for applications at 25 Gbaud and beyond. RF CMOS Photonic

Technology features: The 90nm silicon-on-insulator (SOI) Figure 1: CMOS process flow with RF and photonic modules added. Ele- CMOS process is tailored to a manufacturable design point ments of the baseline process that have been optimized for photonic device for applications up to 25 Gbaud with the addition of photon- performance are indicated with * ic and RF process modules (Figure 1). The standard FETs are built in a dual oxide process with parametrics in Table 1, Table 1: FET parametrics for body contacted (BC) and floating body (FB) and used for a standard cell logic library. To enable high- devices for 1.2V (nominal) and 3.3V operation. Ion measured speed analog circuits the gate length of the standard FETs is |VD|=|VG|=1.2V/3.3V, VB=0V (includes self heating); Ioff measured at reduced, and precision polysilicon resistors (8% tolerance), a |VD|=1.2V/3.3V, |VG|=0V, VB=0V. bandgap diode, capacitors and inductors are added with hardware-based RF models. eFuses are also included to ena- Lpoly (nm) Ion (ȝA/ȝm) Ioff (nA/ȝm) ble design customization post-test. In addition to hardware- LVT FB NFET 55 815 100 based models, the PDK includes design rule checking of LVT FB PFET 55 -390 -40 layouts and layout verification tools. The photonics portion RVT FB NFET 55 770 30 of the PDK includes device pcells, routing tools, and models RVT FB PFET 55 -340 -12 which can be employed in industry standard CMOS design environments. The models include parameter statistics RVT BC NFET 55 700 3.5 based on actual process line correlation. Parameters and RVT BC PFET 55 -310 -2 equations used in the models are documented, as is the mod- 3.3V BC NFET 400 550 -0.02 el-to-hardware correlation, shown in Figure 2 for the power 3.3V BC PFET 400 -250 -0.15

Fabrication of CMOS devices and silicon photonic components on the same substrate has been facilitated through the use of an integrated data preparation flow for generation of mask reticles. Control of critical dimensions for both electrical and optical devices has been enabled by data preparation and optical proximity correction (OPC) algorithms spe- cifically refined to be compatible with printing the curved design shapes typically employed in photonic waveguides, simultaneously with the rectilinear shapes found in CMOS devices. Automated electro-optical test: Statistical optical data is obtained for a given device under test (DUT) by arranging the DUT in a cut back measurement, consisting of up to 4 geometrical lengths, Figures 4a-b). The histogram of repre- sentative measurements for both the fully and partially Figure 2: Model-to-hardware correlation for the optical power ratio at the outputs of a standard directional coupler, as a function of geometric coupl- etched silicon optical waveguides over multiple mask de- ing length. Two independent measurements are included signs and wafer lots is shown in Figures 4 c-d). Similar test structures are utilized to characterize modulator VʌL, ther- Manufacturing for photonic device optimization: Since mo-optic phase shifter efficiency, detector responsivity, the active device silicon layer also functions as an optical WDM passbands and crosstalk, directional coupler coupling waveguide, several front-end process steps have been altered length, and other active and passive device parameters. for photonic device performance. Examples include optimiz- ing the STI etch process for more vertical sidewalls, and improving the spacer etches to minimize erosion of the silicon, reducing propagation loss by 1 dB/cm for fully etched waveguides compared to an earlier process. Moreover, a common module for the first level of contact vias was optimized to yield CMOS devices (with silicide) and germanium photodetector (without silicide/germanide). The via etch, wafer cleans, and thermal anneals within this contact module were optimized to maintain CMOS performance and to achieve a low germanium photodetector dark current. In addition, active thermal tuning of the CWDM multiplexer/demultiplexer devices guarantees manufacturability for a wide variety of applications, Figure 3.

Figure 4: (a) Schematic of in-line electro-optical test module with 1x4 optical and 1x25 electrical pad sets for fully automated wafer level testing. (b) Example cut back measurement for the fully etched waveguide device under test (DUT) on five sites. Measurements of propagation loss on (c) 336 fully . etched and (d) 326 partially etched waveguide test structures across 75 wafers in 8 lots, with mean and 3 sigma values as shown. The insets illu- Figure 3: CWDM transmission characteristics after thermal tuning for the strate the cross-section of the SOI waveguide core. (a) first-order multiplexer, and (b) second-order demultiplexer.

IEDM15-653 25.7.2 Optical transmitters: The transmitters (TXs) consist of a Germanium PIN diode: To improve manufacturability of CMOS driver monolithically integrated with a Mach- the germanium rapid-melt regrowth detectors, p+ and n+ Zehnder modulator (MZM), and have shown error free oper- implants are introduced after the source-drain anneal, Figure ation (bit-error rate <10-12) out to 32 Gb/s [5]. The MZM 1. Detector leakage is suppressed below 2 μA at 125 °C and PN-junction phase shifter efficiency-loss figure of merit -0.8V bias, Figure 7a. The electrical diode yield histogram (FOM), Table 2, is a function of n and p doping dose, and is shown in Figure 8 illustrates a 25 °C <1 μA leakage yield of the simple multiplication of the PN-junction optical loss (~9 99.5%. Responsivity across the O-band window demon- dB/cm), as measured by the electro-optic multisite automat- strates TE/TM polarization dependence less than 0.5 dB, in ed tester, and the MZM Vπ*L sensitivity (1.58 V-cm), and is the range of 0.58-0.71 A/W, Figure 7b. This enables directly 14 V-dB with a -0.5 V bias at the nominal conditions. The fiber-coupled receivers. monolithic stand-alone TX in Figure 5a generated the 25.8 Gb/s eye diagram in Figure 5b, and had a ~3.5 dB optical -4 (a)10 (b) insertion loss and 4.5 dB extinction ratio. 50 Gb/s transmitters are enabled using higher order transmission formats -5 10 0.7 such as PAM-4 [6], Figure 6. The monolithic PAM-4 silicon optical TX is based on a segmented Mach-Zehnder modula- -6 tor that performs the optical digital to analog conversion, 10 and operates at bit rates up to 56 Gb/s (28 Gbaud). -7 10 0.6

Table 2: PN-junction phase shifter propagation loss, Vπ-L, and FOM versus Dark Current(A) -8 MZM doping dose, at a -0.5 V bias. * FOM = PN-junction optical loss (as (AResponsivity / W) 1265nm TE TM π 10 measured by the electro-optic automated tester) x V -L sensitivity 1310nm TE TM -9 1350nm TE TM 10 0.5 Prop Loss Vπ-L (V-cm) FOM (V- -1 0 1 -1 -0.5 0 (dB/cm) dB)* Voltage (V) Voltage (V) Nominal 8.9 1.58 14.0 Figure 7: (a) Temperature-dependent dark current curves for 10 germanium MZM Dose photodiodes; (b) Average wavelength- and polarization-dependent respon- 1.3*Nominal 11.1 1.48 16.4 sivity for 4 germanium photodiodes. MZM Dose 180

135

90 Count 45

0 0.0 0.2 0.4 0.6 0.8 1.0 25°C Diode Leakage Current @ 0.8V (μA)

Figure 8: Leakage histogram for germanium detector. Yield for <1 μA leakage is 99.5%, with 992 diodes tested from 19 wafers. Figure 5: (a) Micrograph of standalone monolithic MZM TX, which is equivalent to the design TX 4 shown in Fig. 10. (b) Corresponding 25.8 Polarization management: Adiabatic polarization splitters Gb/s TX optical eye diagram. and rotators (PSR) leverage the available CMOS structural layers for WDM-required polarization diversity. Various implementations exhibit insertion loss between 0.3 and 1.5 dB and cross-talk better than -20 dB. Fiber to chip coupling: V-grooves monolithically integrated on-chip enable self-alignment to within +/- 1.3 um (3ı) [3] of standard cleaved fibers to integrated fiber couplers. The fiber couplers are metamaterial spot-size convertors suspended over a silicon handle undercut to allow mode expan- sion beyond the limited buried oxide thickness, Figure 9. The convertors were shown in [4] to offer a -1.3 dB peak Figure 6: Monolithic PAM-4 transmitter based on a two-segment MZM. coupling efficiency to a standard cleaved fiber with 0.8 dB The 25 Gbaud (50 Gb/s) PAM-4 transmitter eye is shown in the upper right with a 6.0 dB extinction ratio. penalty over a 100 nm bandwidth and all polarizations.

25.7.3 IEDM15-654 Venting hole

Metamaterial Suspended coupler region

Non- Fiber suspended V-groove 30 um region

Figure 9: Top-view optical micrograph of a fiber to chip interface. The metamaterial fiber coupler is embedded in a suspended oxide membrane. Figure 11: Receive side of loopback on-chip link for receivers 1-4 measured Reference design demonstration: A monolithic 4x25 Gb/s independently using channel TX 1 at 25 Gb/s. Due to TE input from the on- chip link, the TM path demux is not illuminated. The waveguide routing reference design was completed with a hardware-verified post-demux balances timing skew between channels. Foundry PDK. Support for industry-standard tools facilitated full circuit simulation for the complete electro-optic system. Conclusions: A monolithic CMOS photonic platform that is The hardware-based device models include temperature and optimized for manufacturable O-band datacom transceivers wavelength dependence. The die was assembled using C4 is presented with 4x25 Gb/s link functionality demonstrated. attach and optical connection via vertical grating couplers The photonics process modules used to construct the photon- for an on-chip loop-back link test. The transmit and receive ic devices are transferable to other CMOS lithographic subsystems, for which a design skew across channels was nodes directly when the SOI thickness is matched, either by included, are shown in Figs. 10 and 11 respectively. Error- the use of an identical SOI starting wafer, or by a hybrid free transmission was verified for the TX1 to RX4 link at 25 substrate construction where the ‘photonic’ silicon thickness Gb/s using a PRBS31 data pattern. is maintained. The integration of the process modules would be unique to each CMOS process flow. Acknowledgements: The authors are grateful for support from the IBM Microelectronics PDK Enablement Group: Andrea Paganini and Yves Ngu (CMOS passive modelers), Jude Hankey and Steven Mixon (DRC), Derrick Kunze (LVS), and Jiansheng (Jason) Xu (PEX), as well as from the IBM Microelectronics Research Laboratory and Central Scientific Services. Tim Buchholtz, Ladd Freitag, Ray Ri- chetta, and the IBM Rochester team are recognized for their contributions to the development of the reference design. The authors also thank Daniel Kuchta for assistance with high-speed characterization, and Yurii Vlasov for his contin- ued support. References [1] S. Assefa, et al., IEDM, 2012, 33.8.1. [2] F. Boeuf, et al., IEDM 2013, 13-353. [3] T. Barwicz, et al., Proc of ECTC 2015, pp. 775-782. [4] T. Barwicz, et al., OFC 2015, Th3F.3. [5] D. M. Gill, et al., CLEO 2015, STuF-3. [6] C Xiong et al., IEEE OI 2015, MC3 Figure 10: Transmit side of loopback on-chip link for transmitters 1-4 measured independently using channel RX 4 at 25 Gb/s.

IEDM15-655 25.7.4