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Tutorial Hardware and Software Architectures for the CELL IBM Systems and Technology Group Tutorial Hardware and Software Architectures for the CELL BROADBAND ENGINE processor Michael Day, Peter Hofstee IBM Systems & Technology Group, Austin, Texas CODES+ISSS Conference, September 2005 © 2005 IBM Corporation IBM Systems and Technology Group Agenda Trends in Processors and Systems Introduction to Cell Challenges to processor performance Cell Broadband Engine Architecture (CBEA) Cell Broadband Engine (CBE) Processor Overview Cell Programming Models Prototype Software Environment TRE Demo 2 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Trends in Microprocessors and Systems 3 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Processor Performance over Time (Game processors take the lead on media performance) Flops (SP) 1000000 100000 10000 Game Processors 1000 PC Processors 100 10 1993 1995 1996 1998 2000 2002 2004 4 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group System Trends toward Integration Memory Northbridge Memory Next-Gen Accel Processor Processor IO Southbridge IO Implied loss of system configuration flexibility Must compensate with generality of acceleration function to maintain market size. 5 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Motivation: Cell Goals Outstanding performance, especially on game/multimedia applications. • Challenges: Memory Wall, Power Wall, Frequency Wall Real time responsiveness to the user and the network. • Challenges: Real-time in an SMP environment, Security Applicable to a wide range of platforms. • Challenge: Maintain programmability while increasing performance Support an introduction in 2005/6. • Challenge: Structure innovation such that 5yr. schedule can be met 6 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Performance Limiters in Conventional Microprocessors Memory Wall • Latency induced bandwidth limitations Power Wall • Must improve efficiency and performance equally Frequency Wall • Diminishing returns from deeper pipelines (can be negative if power is taken into account) 7 STI Technology © 2005 IBM Corporation SystemsIBM and Systems Technology and Technology Group Group Cell 8 STI Technology © 2005 IBM Corporation SystemsIBM and Systems Technology and Technology Group Group Cell History IBM, SCEI/Sony, Toshiba Alliance formed in 2000 Design Center opened in March 2001 Based in Austin, Texas February 7, 2005: First external technical disclosures • Cell Broadband Engine Architecture documentation can be found at: http://www.ibm.com/developerworks/power/cell • Additional publications on Cell can be downloaded from: http://www.ibm.com/chips/techlib/techlib.nsf/products/Cell • A paper on Cell in the upcoming issue of the IBM Journal of Research and Development can be found at: http://www.research.ibm.com/journal/rd/494/kahle.html 9 STI Technology © 2005 IBM Corporation SystemsIBM and Systems Technology and Technology Group Group Cell Highlights Supercomputer on a chip Multi-core microprocessor (9 cores) 3.2 GHz clock frequency 10x performance for many applications Digital home to distributed computing 10 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Introducing Cell Sets a new performance standard • Exploits parallelism while achieving high frequency • Supercomputer attributes with extreme floating point capabilities • Sustains high memory bandwidth with smart DMA controllers Designed for natural human interaction • Photo-realistic effects • Predictable real-time response • Virtualized resources for concurrent activities Designed for flexibility • Wide variety of application domains • Highly abstracted to highly exploitable programming models • Reconfigurable I/O interfaces • Autonomic power management 11 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Microprocessor Architecture Trends Streaming 64b Power Mem. Graphics Processor GPU Processor Contr. NIC Network Synergistic Processor Processor CPU CPU Security Security Processor .. Media . Media Processor Config. … Synergistic IO … Processor Hardwired Programmable Function ASIC Cell 12 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Key Attributes of Cell Cell is Multi-Core • Contains 64-bit Power Architecture TM • Contains 8 Synergistic Processor Elements (SPE) Cell is a Flexible Architecture • Multi-OS support (including Linux) with Virtualization technology • Path for OS, legacy apps, and software development Cell is a Broadband Architecture • SPE is RISC architecture with SIMD organization and Local Store • 128+ concurrent transactions to memory per processor Cell is a Real-Time Architecture • Resource allocation (for Bandwidth Measurement) • Locking Caches (via Replacement Management Tables) Cell is a Security Enabled Architecture • SPE dynamically reconfigurable as secure processors 13 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Cell Architecture is … 64b Power Architecture™ Power Power ISA … ISA MMU/BIU MMU/BIU IO Memory COHERENT BUS transl. Incl. coherence/memory compatible with 32/64b Power Arch. Applications and OS’s 14 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Cell Architecture is … 64b Power Architecture™ Plus Power Power Memory ISA ISA +RMT … +RMT Flow Control (MFC) MMU/BIU MMU/BIU +RMT +RMT IO Memory COHERENT BUS (+RAG) transl. MMU/DMA MMU/DMA +RMT +RMT … LS Alias … Local Store Local Store LS Alias Memory Memory 15 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Cell Architecture is … 64b Power Architecture™+ MFC Plus Power Power Synergistic ISA ISA +RMT … +RMT Processors MMU/BIU MMU/BIU +RMT +RMT IO Memory COHERENT BUS (+RAG) transl. MMU/DMA MMU/DMA Syn. Syn. +RMT +RMT … LS Alias Proc. Proc. … Local Store Local Store ISA ISA LS Alias Memory Memory 16 STI Technology © 2005 IBM Corporation SystemsIBM and Systems Technology and Technology Group Group Cell - Attacking the Performance Walls Multi-Core Non-Homogeneous Architecture • Control Plane vs. Data Plane processors • Attacks Power Wall 3-level Model of Memory • Main Memory, Local Store, Registers • Attacks Memory Wall Large Shared Register File & SW Controlled Branching • Allows deeper pipelines • Attacks Frequency Wall 17 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Frequency Increase vs Power Consumption 3.5 3 2.5 2 Power Frequency Realative 1.5 1 0.5 0 0.9 1 1.1 1.2 1.3 Voltage 18 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Power Efficient Architecture and the CellBE Non-Homogeneous Coherent Multi-Processor • Data-plane/Control-plane specialization • More efficient than homogeneous SMP 3-level model of Memory • Bandwidth without (inefficient) speculation • High-bandwidth .. Low power 19 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Power Efficient Architecture and the SPE Power Efficient ISA allows Simple Control • Single mode architecture • No cache • Branch hint • Large unified register file • Channel Interface Efficient Microarchitecture • Single port local store • Extensive clock gating Efficient implementation • See Cool Chips paper by O. Takahashi et al. and T. Asano et al. 20 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Cell Broadband Engine Components 21 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Cell Processor Components Power Processor Element (PPE): •General Purpose, 64-bit RISC Processor (PowerPC AS 2.0.2) In the Beginning •2-Way Hardware Multithreaded •L1 : 32KB I ; 32KB D – the solitary Power Processor •L2 : 512KB •Coherent load/store •VMX •3+ GHz •Real-time Control •Locking L2 Cache & TLB NCU •Bandwidth Reservation Power Core (PPE) L2 Cache Custom Designed – for high frequency, space and power efficiency 22 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Cell Processor Components EIB data ring for internal communication • Four 16 byte data rings, supporting multiple transfers MIC • 96B/cycle peak bandwidth 96 Byte/Cycle 300+GB/sec @ 3.2 GHz N N • Over 100 outstanding requests • 300+ GByte/sec @ 3.2 GHz N NCU Power Core (PPE) L2 Cache Element Interconnect Bus 23 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Cell Processor Components SPU LocalStore SPU LocalStore SPE provides computational performance • Dual issue, up to 8-way 32-bit SIMD • Dedicated resources: 128 128-bit RF, MFC MFC AUC 256KB Local Store AUC • Each DMA MMU can be dynamically configured to protect resources MIC N N • Dedicated DMA engine: Up to 16 96 Byte/Cycle 300+ GB/sec @ 3.2 GHz outstanding requests N N MFC SPU N Local Store AUC N N NCU AUC Local Store SPU MFC Power Core (PPE) Local Store AUC L2 Cache N MFC SPU SPU MFC N AUC Local Store Element Interconnect Bus N N AUC AUC MFC MFC Local Store Local Store SPU SPU 24 STI Technology © 2005 IBM Corporation IBM Systems and Technology Group Cell Processor Components SPU LocalStore SPU Memory Flow Controller (MFC) and Atomic LocalStore Update Cache (AUC) • 4 line cache for shared memory atomic update primitives MFC •High performance DMA unit MFC AUC •Local Store aliased into PPE system memory AUC •16 element SPE side DMA Command Queue • 8 element PPE side DMA Command Queue MIC N N •DMA List supports 2K entry scatter/gather 96 Byte/Cycle 300+ GB/sec @ 3.2GHz •MFC-MMU controls SPE DMA accesses N N •Compatible with PowerPC Virtual Memory MFC SPU N architecture N •Full memory protection for MFC DMA NCU
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