SPICE Modeling of Resistor Circuits

Total Page:16

File Type:pdf, Size:1020Kb

SPICE Modeling of Resistor Circuits Modular Electronics Learning (ModEL) project * SPICE ckt v1 1 0 dc 12 v2 2 1 dc 15 r1 2 3 4700 r2 3 0 7100 .dc v1 12 12 1 .print dc v(2,3) .print dc i(v2) .end V = I R SPICE Modeling of Resistor Circuits c 2016-2020 by Tony R. Kuphaldt – under the terms and conditions of the Creative Commons Attribution 4.0 International Public License Last update = 3 September 2020 This is a copyrighted work, but licensed under the Creative Commons Attribution 4.0 International Public License. A copy of this license is found in the last Appendix of this document. Alternatively, you may visit http://creativecommons.org/licenses/by/4.0/ or send a letter to Creative Commons: 171 Second Street, Suite 300, San Francisco, California, 94105, USA. The terms and conditions of this license allow for free copying, distribution, and/or modification of all licensed works by the general public. ii Contents 1 Introduction 3 2 Using SPICE 5 2.1 Summary of steps ...................................... 7 2.2 Demonstration on Microsoft Windows .......................... 8 2.3 Demonstration on Linux or CygWin ........................... 13 2.4 Demonstration of NGSPICE interactive mode ...................... 17 2.5 Idiosyncrasies of SPICE .................................. 23 2.5.1 Beginning and ending cards ............................ 23 2.5.2 Node zero ...................................... 24 2.5.3 Current measurement ............................... 24 2.5.4 Open and short circuits .............................. 24 2.5.5 Multiple sources .................................. 25 2.5.6 Multiple inductors/capacitors ........................... 25 3 SPICE component descriptions 27 3.1 Independent voltage sources ................................ 28 3.1.1 Example: DC source ................................ 28 3.1.2 Example: “Dummy” source ............................ 28 3.1.3 Example: AC source ................................ 29 3.1.4 Example: Sinusoidal source ............................ 31 3.1.5 Example: Pulse source ............................... 32 3.2 Independent current sources ................................ 33 3.2.1 Example: DC source ................................ 33 3.2.2 Example: AC source ................................ 33 3.3 Resistors ........................................... 34 3.3.1 Example ....................................... 34 3.4 Capacitors .......................................... 35 3.4.1 Example: Capacitor with initial charge ..................... 35 3.4.2 Example: Uncharged capacitor .......................... 35 3.5 Inductors .......................................... 36 3.5.1 Example: Inductor with initial charge ...................... 36 3.5.2 Example: Uncharged inductor ........................... 36 3.6 Transformers ........................................ 37 iii iv CONTENTS 3.6.1 Example: 2:1 ratio step-down transformer .................... 37 3.7 Transmission lines ..................................... 38 3.8 Linear dependent sources ................................. 39 3.8.1 Example: voltage-controlled voltage source ................... 40 3.8.2 Example: voltage-controlled current source ................... 40 3.9 Nonlinear dependent sources ............................... 41 3.9.1 Example: multiplier ................................ 41 3.10 Diodes ............................................ 42 3.10.1 Example: Generic diode .............................. 42 3.10.2 Example: 1N4001 ................................. 43 3.11 Bipolar Junction Transistors (BJTs) ........................... 44 3.11.1 Example: Generic NPN transistor ........................ 45 3.11.2 Example: 2N2907 ................................. 45 3.12 Junction Field-Effect Transistors (JFETs) ........................ 46 3.12.1 Example: Generic N-channel JFET ........................ 47 3.13 Metal-Oxide Field-Effect Transistors (MOSFETs) .................... 48 3.13.1 Example: Generic N-channel depletion-type MOSFET ............. 49 3.13.2 Example: Generic N-channel enhancement-type MOSFET ........... 49 3.13.3 Example: Generic P-channel depletion-type MOSFET ............. 50 3.13.4 Example: Generic P-channel enhancement-type MOSFET ........... 50 3.14 Subcircuits ......................................... 51 3.14.1 Example: resistor subnetwork ........................... 52 3.14.2 Example: solar cell array ............................. 53 4 SPICE analysis descriptions 55 4.1 DC voltage/current“sweep” analysis ........................... 56 4.1.1 Example: sweep of voltage source ......................... 56 4.1.2 Example: sweep of voltage and current sources ................. 56 4.2 AC frequency “sweep” analysis .............................. 57 4.2.1 Example: linear frequency sweep ......................... 57 4.2.2 Example: decade logarithmic frequency sweep .................. 57 4.2.3 Example: octave logarithmic frequency sweep .................. 57 4.3 Transient analysis ..................................... 58 4.3.1 Example: using initial conditions, beginning at time t = 0 ........... 58 4.3.2 Example: using initial conditions, beginning at non-zero time ......... 58 4.4 Fourier analysis ....................................... 59 4.4.1 Example: analysis of 60 Hz waveform ...................... 59 4.5 Display option: print .................................... 60 4.5.1 Example: printing a DC analysis ......................... 60 4.5.2 Example: printing an AC analysis ........................ 60 4.6 Display option: plot .................................... 61 4.6.1 Example: plotting a DC analysis ......................... 61 4.6.2 Example: plotting an AC analysis ........................ 61 4.6.3 Example: plotting a transient analysis ...................... 62 4.6.4 Example: plotting parametric functions ..................... 62 4.7 Display option: width ................................... 63 CONTENTS v 4.7.1 Example ....................................... 63 5 Primitive circuit examples 65 5.1 DC voltage source with .op analysis ........................... 66 5.2 DC voltage source with single-point .dc sweep analysis ................. 70 5.3 DC current source with single-point .dc sweep analysis ................. 73 5.4 DC voltage source with multi-point .dc sweep analysis ................. 74 5.5 AC voltage source with single-point .ac sweep analysis ................. 77 5.6 AC voltage source with multi-point .ac sweep analysis ................. 78 5.7 Additive AC voltage sources with single-point .ac sweep analysis ........... 82 5.8 Transient analysis of discharging RC circuit ....................... 84 5.9 Transient analysis of a steady sinusoidal voltage source ................. 89 5.10 Transient analysis of a sinusoidal capacitive circuit ................... 92 5.11 Transient analysis of a damped, offset sinusoidal voltage source ............ 95 5.12 Additive AC voltage sources with transient analysis .................. 98 5.13 Solar cell array simulation ................................. 100 5.14 Solar panel array simulation ................................ 102 6 Gallery 107 6.1 Using gallery examples for practice ............................ 108 6.2 Series resistor circuits ................................... 109 6.2.1 One DC current source, three resistors ...................... 110 6.2.2 One DC voltage source, three resistors ...................... 111 6.2.3 One DC voltage source, four resistors ...................... 112 6.2.4 One DC current source, five resistors ....................... 113 6.2.5 One DC voltage source, ten resistors ....................... 114 6.2.6 Three DC voltage sources, four resistors ..................... 116 6.3 Parallel resistor circuits .................................. 117 6.3.1 One DC voltage source, three resistors ...................... 118 6.3.2 One DC current source, three resistors ...................... 119 6.3.3 One DC voltage source, four resistors ...................... 120 6.3.4 One DC current source, five resistors ....................... 122 6.3.5 Three DC current sources, two resistors ..................... 124 6.4 Series-parallel resistor circuits ............................... 125 6.4.1 One DC voltage source, six resistors ....................... 126 6.4.2 One DC current source, six resistors ....................... 128 6.5 Simple multi-source resistor circuits ........................... 130 6.5.1 One voltage, one current .............................. 131 6.5.2 Two currents, one voltage ............................. 132 6.5.3 Two voltages, one current ............................. 133 6.5.4 Two currents, two voltages ............................ 134 A Problem-Solving Strategies 135 B Instructional philosophy 137 CONTENTS 1 C Tools used 143 D Creative Commons License 147 E References 155 F Version history 157 Index 157 2 CONTENTS Chapter 1 Introduction SPICE is a general-purpose computer simulator for electronic circuits, with several “freeware” versions available for academic use. Although its text-based user interface may seem clumsy and archaic at first, it is quite powerful, and also neatly side-steps the many problems students tend to experience with graphic-entry (“WYSIWYG”)1 circuit simulators. Circuits are described to SPICE in the form of a netlist, which is a text-based code listing of each component within the circuit, the “nodes” connecting them to each other, and the types of analyses requested of SPICE to perform on that circuit. A simple three-resistor DC circuit is shown in schematic form below, along with the netlist you would write and input to SPICE instructing it to analyze this
Recommended publications
  • HSPICE Tutorial
    UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments HSPICE Tutorial Contents 1 Introduction 1 2 Windows vs. UNIX 1 2.1 Windows ......................................... ...... 1 2.1.1 ConnectingFromHome .. .. .. .. .. .. .. .. .. .. .. .. ....... 2 2.1.2 RunningHSPICE ................................. ..... 2 2.2 UNIX ............................................ ..... 3 2.2.1 Software...................................... ...... 3 2.2.2 RunningSSH.................................... ..... 4 2.2.3 RunningHSPICE ................................. ..... 4 3 Simulating Circuits in HSPICE and Awaves 5 3.1 HSPICENetlistSyntax ............................. .......... 5 3.2 Examples ........................................ ....... 6 3.2.1 Transient analysis of a simple RC circuit . ............... 6 3.2.2 Operatingpointanalysisforadiode . ............. 7 3.2.3 DCanalysisofadiode............................ ........ 8 3.2.4 ACanalysisofahigh-passfilter. ............ 9 3.2.5 Transferfunctionanalysis . ............ 10 3.2.6 Pole-zeroanalysis. .......... 10 3.2.7 The .measure command................................... 11 3.3 Includinganotherfile. .. .. .. .. .. .. .. .. .. .. .. .. ............ 12 4 Using Awaves 13 4.1 Interfacedescription . ............. 13 4.2 Deletingplots................................... .......... 13 4.3 Printingplots................................... .......... 13 4.4 Makingameasurement .............................. ......... 13 4.5 Zooming........................................
    [Show full text]
  • Nanoelectronic Mixed-Signal System Design
    Nanoelectronic Mixed-Signal System Design Saraju P. Mohanty Saraju P. Mohanty University of North Texas, Denton. e-mail: [email protected] 1 Contents Nanoelectronic Mixed-Signal System Design ............................................... 1 Saraju P. Mohanty 1 Opportunities and Challenges of Nanoscale Technology and Systems ........................ 1 1 Introduction ..................................................................... 1 2 Mixed-Signal Circuits and Systems . .............................................. 3 2.1 Different Processors: Electrical to Mechanical ................................ 3 2.2 Analog Versus Digital Processors . .......................................... 4 2.3 Analog, Digital, Mixed-Signal Circuits and Systems . ........................ 4 2.4 Two Types of Mixed-Signal Systems . ..................................... 4 3 Nanoscale CMOS Circuit Technology . .............................................. 6 3.1 Developmental Trend . ................................................... 6 3.2 Nanoscale CMOS Alternative Device Options ................................ 6 3.3 Advantage and Disadvantages of Technology Scaling . ........................ 9 3.4 Challenges in Nanoscale Design . .......................................... 9 4 Power Consumption and Leakage Dissipation Issues in AMS-SoCs . ................... 10 4.1 Power Consumption in Various Components in AMS-SoCs . ................... 10 4.2 Power and Leakage Trend in Nanoscale Technology . ........................ 10 4.3 The Impact of Power Consumption
    [Show full text]
  • Writing Simple Spice Netlists
    By Joshua Cantrell Page <1> [email protected] Writing Simple Spice Netlists Introduction Spice is used extensively in education and research to simulate analog circuits. This powerful tool can help you avoid assembling circuits which have very little hope of operating in practice through prior computer simulation. The circuits are described using a simple circuit description language which is composed of components with terminals attached to particular nodes. These groups of components attached to nodes are called netlists. Parts of a Spice Netlist A Spice netlist is usually organized into different parts. The very first line is ignored by the Spice simulator and becomes the title of the simulation.1 The rest of the lines can be somewhat scattered assuming the correct conventions are used. For commands, each line must start with a ‘.’ (period). For components, each line must start with a letter which represents the component type (eg., ‘M’ for MOSFET). When a command or component description is continued on multiple lines, a ‘+’ (plus) begins each following line so that Spice knows it belongs to whatever is on the previous line. Any line to be ignored is either left blank, or starts with a ‘*’ (asterik). A simple Spice netlist is shown below: Spice Simulation 1-1 *** MODEL Descriptions *** .model nm NMOS level=2 VT0=0.7 KP=80e-6 LAMBDA=0.01 vdd *** NETLIST Description *** R1 M1 M1 vdd ng 0 0 nm W=3u L=3u in 3µ/3µ + R1 in ng 50 ng 5V - Vdd Vdd vdd 0 5 50Ω Vin in 0 2.5 Vin + *** SIMULATION Commands *** - 2.5V 0 .op .end Figure 1: Schematic of Spice Simulation 1-1 Netlist The first line is the title of the simulation.
    [Show full text]
  • SPICE Netlist Generation for Electrical Parasitic Modeling of Multi-Chip Power Module Designs Peter Tucker University of Arkansas, Fayetteville
    University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Electrical Engineering Theses 5-2013 SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs Peter Tucker University of Arkansas, Fayetteville Follow this and additional works at: http://scholarworks.uark.edu/eleguht Part of the Electrical and Electronics Commons, and the Electronic Devices and Semiconductor Manufacturing Commons Recommended Citation Tucker, Peter, "SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs" (2013). Electrical Engineering Undergraduate Honors Theses. 4. http://scholarworks.uark.edu/eleguht/4 This Thesis is brought to you for free and open access by the Electrical Engineering at ScholarWorks@UARK. It has been accepted for inclusion in Electrical Engineering Undergraduate Honors Theses by an authorized administrator of ScholarWorks@UARK. For more information, please contact [email protected], [email protected]. SPICE NETLIST GENERATION FOR ELECTRICAL PARASITIC MODELING OF MULTI-CHIP POWER MODULE DESIGNS SPICE NETLIST GENERATION FOR ELECTRICAL PARASITIC MODELING OF MULTI-CHIP POWER MODULE DESIGNS An Undergraduate Honors College Thesis in the Department of Electrical Engineering College of Engineering University of Arkansas Fayetteville, AR by Peter Nathaniel Tucker April 2013 ABSTRACT Multi-Chip Power Module (MCPM) designs are widely used in the area of power electronics to control multiple power semiconductor devices in a single package. The work described in this thesis is part of a larger ongoing project aimed at designing and implementing a computer aided drafting tool to assist in analysis and optimization of MCPM designs. This thesis work adds to the software tool the ability to export an electrical parasitic model of a power module layout into a SPICE format that can be run through an external SPICE circuit simulator.
    [Show full text]
  • Simulatorreference.Pdf
    SIMetrix SPICE and Mixed Mode Simulation Simulator Reference Manual Copyright ©1992-2006 Catena Software Ltd. Trademarks PSpice is a trademark of Cadence Design Systems Inc. Star-Hspice is a trademark of Synopsis Inc. Contact Catena Software Ltd., Terence House, 24 London Road, Thatcham, RG18 4LQ, United Kingdom Tel.: +44 1635 866395 Fax: +44 1635 868322 Email: [email protected] Internet http://www.catena.uk.com Copyright © Catena Software Ltd 1992-2006 SIMetrix 5.2 Simulator Reference Manual 1/1/06 Catena Software Ltd. is a member of the Catena group of companies. See http://www.catena.nl Table of Contents Table of Contents Chapter 1 Introduction The SIMetrix Simulator - What is it? ................................10 A Short History of SPICE.................................................10 Chapter 2 Running the Simulator Using the Simulator with the SIMetrix Schematic Editor..12 Adding Extra Netlist Lines ........................................12 Displaying Net and Pin Names.................................12 Editing Device Parameters.......................................13 Editing Literal Values - Using shift-F7 ......................13 Running in non-GUI Mode...............................................14 Overview...................................................................14 Syntax.......................................................................14 Aborting ....................................................................15 Reading Data............................................................16 Configuration
    [Show full text]
  • Standard Cell Library Design and Optimization with CDM for Deeply Scaled Finfet Devices
    Standard Cell Library Design and Optimization with CDM for Deeply Scaled FinFET Devices. by Ashish Joshi, B.E A Thesis In Electrical Engineering Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCES IN ELECTRICAL ENGINEERING Approved Dr. Tooraj Nikoubin Chair of Committee Dr. Brian Nutter Dr. Stephen Bayne Mark Sheridan Dean of the Graduate School May, 2016 © Ashish Joshi, 2016 Texas Tech University, Ashish Joshi, May 2016 ACKNOWLEDGEMENTS I would like to sincerely thank my supervisor Dr. Nikoubin for providing me the opportunity to pursue my thesis under his guidance. He has been a commendable support and guidance throughout the journey and his thoughtful ideas for problems faced really been the tremendous help. His immense knowledge in VLSI designs constitute the rich source that I have been sampling since the beginning of my research. I am especially indebted to my thesis committee members Dr. Bayne and Dr. Nutter. They have been very gracious and generous with their time, ideas and support. I appreciate Dr. Nutter’s insights in discussing my ideas and depth to which he forces me to think. I would like to thank Texas Instruments and my colleagues Mayank Garg, Jun, Alex, Amber, William, Wenxiao, Shyam, Toshio, Suchi at Texas Instruments for providing me the opportunity to do summer internship with them. I continue to be inspired by their hard work and innovative thinking. I learnt a lot during that tenure and it helped me identifying my field of interest. Internship not only helped me with the technical aspects but also build the confidence to accept the challenges and come up with the innovative solutions.
    [Show full text]
  • SPICE Netlist Generation for Electrical Parasitic Modeling of Multi-Chip Power Module Designs Peter Tucker University of Arkansas, Fayetteville
    University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Electrical Engineering Theses 5-2013 SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs Peter Tucker University of Arkansas, Fayetteville Follow this and additional works at: http://scholarworks.uark.edu/eleguht Recommended Citation Tucker, Peter, "SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs" (2013). Electrical Engineering Undergraduate Honors Theses. 4. http://scholarworks.uark.edu/eleguht/4 This Thesis is brought to you for free and open access by the Electrical Engineering at ScholarWorks@UARK. It has been accepted for inclusion in Electrical Engineering Undergraduate Honors Theses by an authorized administrator of ScholarWorks@UARK. For more information, please contact [email protected]. SPICE NETLIST GENERATION FOR ELECTRICAL PARASITIC MODELING OF MULTI-CHIP POWER MODULE DESIGNS SPICE NETLIST GENERATION FOR ELECTRICAL PARASITIC MODELING OF MULTI-CHIP POWER MODULE DESIGNS An Undergraduate Honors College Thesis in the Department of Electrical Engineering College of Engineering University of Arkansas Fayetteville, AR by Peter Nathaniel Tucker April 2013 ABSTRACT Multi-Chip Power Module (MCPM) designs are widely used in the area of power electronics to control multiple power semiconductor devices in a single package. The work described in this thesis is part of a larger ongoing project aimed at designing and implementing a computer aided drafting tool to assist in analysis and optimization of MCPM designs. This thesis work adds to the software tool the ability to export an electrical parasitic model of a power module layout into a SPICE format that can be run through an external SPICE circuit simulator.
    [Show full text]
  • Computer Aided Design of Electronic Devices
    TOMSK POLYTECHNIC UNIVERSITY O.A. Kozhemyak, D.N. Ogorodnikov COMPUTER AIDED DESIGN OF ELECTRONIC DEVICES It is recommended for publishing as a study aid by the Editorial Board of Tomsk Polytechnic University Tomsk Polytechnic University Publishing House 2014 1 UDC 621.38(075.8) BBC 31.2 K58 Kozhemyak O.A. K58 Computer aided design of electronic devices: study aid / O.A. Kozhemyak, D.N. Ogorodnikov; Tomsk Polytechnic University. – Tomsk: TPU Publishing House, 2014. – 130 p. This textbook focuses on the basic notions, history, types, technology and applications of computer-aided design. Methods of electronic devices simulation, automated design of power electronic devices and components, constructive- technological design are considered and discussed. Some features of the popular electronics CADs are also shown. There are a lot of practical examples using CADs of electronics. The textbook is designed at the Department of Industrial and Medical Electronics of TPU. It is intended for students majoring in the specialty „Electronics and Nanoelectronics‟. UDC 621.38(075.8) BBC 31.2 Reviewer Cand.Sc, Head of Laboratory, Tomsk State University of Control Systems and Radioelectronics Aleksandr V. Osipov © STE HPT TPU, 2014 © Kozhemyak O.A., Ogorodnikov D.N., 2014 © Design. Tomsk Polytechnic University Publishing House, 2014 2 Introduction. CAD around Us ........................................................................... 5 What is CAD? ................................................................................................ 5 Overview
    [Show full text]
  • A Short SPICE Tutorial
    A Short SPICE Tutorial Kenneth H. Carpenter Department of Electrical and Computer Engineering Kanas State University September 15, 2003 - November 10, 2004 1 Introduction SPICE is an acronym for “Simulation Program with Integrated Circuit Em- phasis.” There are many versions of this program, but all are based on the work done at the University of California at Berkeley[1], which resulted in two major, final versions: SPICE2G6 and SPICE3F4. Others have enhanced and extended (and fixed bugs) in these to produce new versions. Some of these are commercial; some are free software. In the following tutorial, the “lowest common denominator” of all the SPICE versions is described. That is, the SPICE input files will work with all the versions (known to the au- thor). (Comments on how to extend the input files to take advantage of special features of special versions will be given in a few places.) SPICE uses a modified nodal analysis method[2] to solve electrical cir- cuits. To communicate the topology of the circuit and the circuit values to SPICE one requires an input file containing a netlist. To communicate the analyses one requires from the program one places control lines in the input file. To obtain output from the analyses one places output control lines in the input file. The details of constructing this input file follow. 2 SPICE input file syntax All SPICE circuit simulators require an input file. This input file is an ASCII text file. The input file is line oriented. 1 2.1 Lines in a SPICE input file • The first line of the file is a title to be placed on the output.
    [Show full text]
  • CL User Guide T of C
    Contents Chapter 1 — Introduction ............................................................................ 1-1 What is CircuitLogix?...............................................................................................................1-1 Required Hardware/Software ...................................................................................................1-3 First Time Installation ..............................................................................................................1-3 Multi-user (Project) Installations .............................................................................................1-3 Using On-line Help ..................................................................................................................1-5 Where to go from here .............................................................................................................1-6 Technical Support ....................................................................................................................1-6 Required User Background ......................................................................................................1-6 Chapter 2 — Schematic Capture ................................................................. 2-1 Getting Started—Schematic Example .......................................................................................2-1 The Editing Tools ....................................................................................................................2-4 Placing
    [Show full text]
  • Pspice Tutorial
    PSpice Tutorial (usage of simulator ) × (common sense) ≈ constant L. Pacher SPICE Simulation Program with Integrated Circuits Emphasis Berkeley University open source code (initially coded in FORTRAN, rewritten in C) analog-only circuits simulator command-line tool with a plain text input file (.cir ) ● interpreted 'markup' and programming language (both UNIX and MS-DOS shells) ● input file = netlist + electrical models + analysis statements ● spice < inputFile.cir | more ● plain text output file new SPICE-like commercial versions with graphical interfaces : PSpice, HSpice, LTSpice, Spectre etc. 2 PSpice Personal SPICE the SPICE version for personal computers with MS Windows operating systems analog, digital and mixed-signals simulator initially developed by MicroSim and then bought by OrCAD at present purchased by Cadence Design Systems free versions: ● PSpice Student 9.1 - max. 10 transistors ● OrCAD PCB Designer 16.5 Lite (demo) - max. 20 transistors industry standard PCB development suite 3 Tools overview Capture - schematic entry tool PSpice A/D - analog, digital and mixed-circuits simulator PSpice Advanced Analysis - Monte Carlo, sensitivity/worst case etc. analyses PSpice Model Editor - edit text SPICE models or extract models from data sheets PSpice Stimulus Editor – graphical editor for time-based waveform 4 Getting started Project Manager schematic window log file 5 Working with projects your work is organized into projects ( .opj main file) specify a new folder in C:\pspice\designs with the same name of the
    [Show full text]
  • Table of Contents
    Table of Contents Introduction 4 Preface ............................................................................................................ 4 SwitcherCAD III Overview ............................................................................... 6 Hardware Requirements.................................................................................. 7 Software Installation ........................................................................................ 8 License Agreement/Disclaimer........................................................................ 8 Mode of Operation 10 Overview........................................................................................................ 10 Example Circuits............................................................................................ 10 General Purpose Schematic Driven SPICE .................................................. 11 Externally Generated Netlists........................................................................ 12 Efficiency Report ........................................................................................... 13 Schematic Capture 15 Basic Schematic Editing................................................................................ 15 Label a node name........................................................................................ 19 Schematic Colors .......................................................................................... 20 Placing New Components ............................................................................
    [Show full text]