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Land Grid Array (LGA) Package Rework
Freescale Semiconductor Document Number: AN3241 Application Note Rev. 1.0, 10/2009 Land Grid Array (LGA) Package Rework 1 Introduction Contents 1 Introduction . 1 This application note describes rework considerations 2 What is LGA? . 3 for the Land Grid Array (LGA) style package. 3 LGA Rework . 5 4 Package Removal . 6 Freescale has introduced radio frequency (RF) modules 5 LGA Reliability . 14 such as the MC1320x and MC1321x in LGA packages as 6 References . 14 an alternative package to ball grid array (BGA). The LGA packages reduce the amounts of lead in finished products and are Reduction of Hazardous Substances (RoHS) compliant, optimized for improved radio-frequency (RF) performance for wireless applications, and/or reduce the overall height of the package by eliminating the stand-off height associated with BGA balls. For assistance with any questions about the information contained in this note or for more details about the MC1320x and MC1321x devices, visit www.freescale.com/802154. or contact the appropriate product applications team. © Freescale Semiconductor, Inc., 2009. All rights reserved. Introduction 1.1 Acronyms and Abbreviations BGA Ball Grid Array BT Bismaleimide Triazine CBGA Ceramic Ball Grid Array CTE Coefficient of Thermal Expansion EU European Union ESD Electrostatic Discharge HCTE High Coefficient of Thermal Expansion HDI High Density Interconnect LGA Land Grid Array LTCC Low Temperature Co-fired Ceramic MSLn Moisture Sensitivity Level n NSMD Non-Solder Mask Defined OSP Organic Solderability Protectant PCB Printed Circuit Board RF Radio Frequency RoHS Reduction of Hazardous Substances SMD Solder Mask Defined SMT Surface Mount Technology Land Grid Array (LGA) Package Rework Application Note, Rev. -
Ceramic Leadless Chip Carrier (LCC)
Ceramic,Leadless,Chip,Carrier,(L Ceramic Leadless Chip Carrier (LCC) Literature Number: SNOA023 Ceramic Leadless Chip Carrier (LCC) August 1999 Ceramic Leadless Chip Carrier (LCC) 20 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E20A © 2000 National Semiconductor Corporation MS101105 www.national.com 20 Lead Ceramic Leadless Chip Carrier NS Package Number EA20B Ceramic Leadless Chip Carrier (LCC) www.national.com 2 Ceramic Leadless Chip Carrier (LCC) 24 Lead Ceramic Leadless Chip Carrier NS Package Number E24B 28 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E28A 3 www.national.com 28 Lead Ceramic Leadless Chip Carrier, Dual Cavity NS Package Number EA028C Ceramic Leadless Chip Carrier (LCC) www.national.com 4 Ceramic Leadless Chip Carrier (LCC) 32 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E32A 32 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E32B 5 www.national.com 32 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E32C Ceramic Leadless Chip Carrier (LCC) 32 Lead Ceramic Leadless Chip Carrier, Type E NS Package Number EA32B www.national.com 6 Ceramic Leadless Chip Carrier (LCC) 32 Lead Ceramic Leadless Chip Carrier, DIP NS Package Number EA32C 40 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E40A 7 www.national.com 44 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E44A Ceramic Leadless Chip Carrier (LCC) 48 Lead Ceramic Leadless Chip Carrier NS Package Number EA48B www.national.com 8 Ceramic Leadless Chip Carrier (LCC) 68 Lead Ceramic -
PDF Package Information
This version: Apr. 2001 Previous version: Jun. 1997 PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS This document is Chapter 1 of the package information document consisting of 8 chapters in total. PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS 1. PACKAGE CLASSIFICATIONS 1.1 Packaging Trends In recent years, marked advances have been made in the electronics field. One such advance has been the progression from vacuum tubes to transistors and finally, to ICs. ICs themselves have been more highly integrated into LSIs, VLSIs, and now, ULSIs. With increased functions and pin counts, IC packages have had to change significantly in the last few years in order to keep-up with the advancement in semiconductor development. Functions required for conventional IC packages are as follows: 1) To protect IC chips from the external environment 2) To facilitate the packaging and handling of IC chips 3) To dissipate heat generated by IC chips 4) To protect the electrical characteristics of the IC Standard dual-in-line packages (DIP), which fulfill these basic requirements, have enjoyed wide usage in the electronics industry for a number of years. With increasing integration and higher speed ICs, and with the miniaturization of electronic equipment, newer packages have been requested by the industry which incorporate the functions listed below: 1) Multi-pin I/O 2) Ultra-miniature packages 3) Packages suited to high density ICs 4) Improved heat resistance for use with reflow soldering techniques 5) High throughput speed 6) Improved heat dissipation 7) Lower cost per pin In response to these requests, OKI has developed a diversified family of packages to meet the myriad requirements of today’s burgeoning electronics industry. -
Quad Flat No-Lead (QFN) Evauation Test
National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California 6/17 National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Success Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.35 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov 6/17 This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. Copyright 2017. California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity including the Rochester Institute of Technology (RIT). The author extends his appreciation to program managers of the National Aeronautics and Space -
Classification of Semiconductor Package
www.connect.co.jp www.jccherry.com Technical Data Classification of semiconductor package SIP ZIP Single In-line Package Zigzag In-line Package A package having leads on a single side of the body. A package having Zig-zag formed leads on a single side of the body. DIP PGA Dual In-line Package Pin Grid Array A package having leads in parallel rows A package having pins on top or bottom on two opposite sides of the body for face in a matrix layout of at least three through-hole insertion. rows and three columns. SDIP Shrink DIP A package which reduced the lead pitch of DIP. SOP SON Small Outline Package Small Outline Non-leaded Package A package having gull-wing-shaped leads A package having single-inline terminal on two opposite sides of the body. pads along two opposite edges of the bottom face. The terminal pads may or may not be exposed on the package sides. TSOP Thin SOP SOJ A package height of SOP exceeds 1.0 mm, Small Outline J-leaded Package and 1.2 mm or less. A package having J-shaped leads on two opposite sides of the body. SSOP Shrink SOP A package which reduced the lead pitch of SOP. 50-01 www.connect.co.jp www.jccherry.com Classification of semiconductor package QFP LGA Quad Flat Package Land Grid Array A package having gull-wing-shaped leads A package having lands on top or bottom on four sides of the body. face in a matrix of at least three rows and three columns. -
Building Your Prototype
Building Your Prototype Prototype Construction Techniques Part Numbers Package Types Specification Sheets Schematic Diagrams Practical Advice T. Grotjohn, [email protected] Prototype Construction Techniques 1) Protoboard Use DIP components Keep your wires neat and color coded Prone to bad connections Maximum operating speed: ~ few MHz 2) Wire Wrap Often done using wire wrap sockets on a vector board Use DIP components Wire used is good for digital signals Be careful with high current lines because the wire is small. Typical wire: 30 gauge 0.34 Ω/m 28 gauge 0.21 Ω/m 3) Soldered Board Single solder points board Tied solder points board (Your mini project #1) PCB: printed circuit board PCB can be made for ECE 480 projects in the ECE Shop: See the shop’s web page. (Also see the next page) . Printed Circuit Board System General Information T-Tech Protyping Machine ECE 482 Student Project Design Department of Electrical and Computer Engineering, 1999 Michigan State University, East Lansing, Michigan, USA Part Numbers Typical Part Number: DM8095N Prefix: Indicates the manufacture of the part. See two pages in Attachment 1. Suffixes: Indicates temperature range: “military”, “industrial”, “commercial” Also the suffixes are used to indicate package types. The ECE shop deals most often with the following electronic part suppliers. Allied Electronics (www.alliedelec.com) Digi Key (www.digikey.com) Newark Electronics (www.newark.com) For other (non-electronic) supplies, suppliers often used are Grainger (www.grainger.com) McMaster Carr (www.mcmaster.com) Package Types DIP: Dual Inline Package Easiest to use. Works in protoboards, solder boards, wire wrapping, easiest to solder components to PCB This is your choice for ECE 480. -
Packaging Product Specification
Packaging Product Specification PS007225-0607 Copyright ©2007 by ZiLOG, Inc. All rights reserved. www.zilog.com DO NOT USE IN LIFE SUPPORT Warning: LIFE SUPPORT POLICY ZiLOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZiLOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2007 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of ZiLOG, Inc. -
Package Reliability As Affected by Material and Processes
I,, '• Package Reliability as Affected By Materials and Processes The semiconductor industry is faced with the problem of how to increase the level of reliability of semiconductor parts being used in electronic systems which have had their lifetimes extended through new and.better system designs. By David Nixen, cussed, are all commercially availc1ble and presently The Aerospace Corporation, being used in high volume in industry. It is not the El Segundo, California intention of this article to present any new, revolu tionary packaging approach, but rather to compare the advantages and disadvantages of the major types The word "reliability" has been used in the semicon as they relate to reliability. uuctor industry over the years in every imaginable The actual choice of which package to use will not way. It may refer to why the cost is so high, the be presented here since that choice is too highly delivery so late, the documentation so voluminous, dependent upon the unique conditions of each indi or, it may be why the system is successful. When vidual case. discussed in the true sense of the word, perhaps reliability has no greater importance than in aero PACKAGE FAMILIES ,, , space systems. The basic package families are divided into three Until this year, a spacecraft system had a projected groups; these three groups, in turn, can be subdivid life of three to five years. Since an orbiting system ed and they, in turn, can also be subdivided. Only cannot be considered in a "repair/replace" categoryr the major families will be discussed, although some a component was required to have an extremely high of the subdivisions will be acknowledged. -
LM117/LM317A/LM317 3-Terminal Adjustable Regulator
LM117/LM317A/LM317 3-Terminal Adjustable Regulator July 2004 LM117/LM317A/LM317 3-Terminal Adjustable Regulator General Description age, supplies of several hundred volts can be regulated as long as the maximum input to output differential is not ex- The LM117 series of adjustable 3-terminal positive voltage ceeded, i.e., avoid short-circuiting the output. regulators is capable of supplying in excess of 1.5A over a Also, it makes an especially simple adjustable switching 1.2V to 37V output range. They are exceptionally easy to regulator, a programmable output regulator, or by connecting use and require only two external resistors to set the output a fixed resistor between the adjustment pin and output, the voltage. Further, both line and load regulation are better than LM117 can be used as a precision current regulator. Sup- standard fixed regulators. Also, the LM117 is packaged in plies with electronic shutdown can be achieved by clamping standard transistor packages which are easily mounted and the adjustment terminal to ground which programs the out- handled. put to 1.2V where most loads draw little current. In addition to higher performance than fixed regulators, the For applications requiring greater output current, see LM150 LM117 series offers full overload protection available only in series (3A) and LM138 series (5A) data sheets. For the IC’s. Included on the chip are current limit, thermal overload negative complement, see LM137 series data sheet. protection and safe area protection. All overload protection circuitry remains fully functional even if the adjustment ter- minal is disconnected. Features Normally, no capacitors are needed unless the device is n Guaranteed 1% output voltage tolerance (LM317A) situated more than 6 inches from the input filter capacitors in n Guaranteed max. -
501-5736 Lever Actuated Land Grid Array 1207 Position Socket ( Socket
Lever Actuated Land Grid Array 1207 Qualification test report Position Socket 501-5736 ( Socket F 1207 ) th 25 SEP 2006 Rev.B 1. Introduction 1.1 Testing was performed on the LGA1207 socket to determine if it meets the requirements of product specification 108-78375 1.2 Scope This report covers the electrical, mechanical and environmental performance requirements of the LGA1207 socket. 1.3 Product description LGA1207 socket has arrayed contacts and solder to printed circuit board (PCB). The socket is used by compressing its contacts to the arrayed CPU land in the normal direction of the PCB. The CPU lands are arrayed with same grid pitch to the socket and has gold plating finish on the surface. LGA1207 socket is actuated by the lever and generates required compression force by the back plate attach to the bottom side of the PCB and the socket actuation mechanism. 1.4 Conclusion 1.2 This test report confirmed that Tyco socket F 1207 satisfied the requirements of the product specification of 108-78375 Rev.A 1.5 Test samples Samples were taken randomly from current production. The following samples were used : Part Number Description LF-LGA1207 socket ( Lead free ) 0-1871554-1 Right / U-lever shape Leaded-LGA1207 socket ( Leaded ) 0-1871554-2 Right / U-lever shape Fig. 1 TYCO Electronics AMP K.K. : Tel 044-844-8079 Fax 044-812-3203 1 of 17 Copyright 2000 by Tyco Electronics AMP K.K. All Right Reserved. RESTRICTED TO AMD Lever Actuated Land Grid Array 1207 Qualification test report Position Socket ( Socket F 1207 ) 501-5736 2. -
Ball Grid Array (BGA) Packaging 14
Ball Grid Array (BGA) Packaging 14 14.1 Introduction The plastic ball grid array (PBGA) has become one of the most popular packaging alternatives for high I/O devices in the industry. Its advantages over other high leadcount (greater than ~208 leads) packages are many. Having no leads to bend, the PBGA has greatly reduced coplanarity problems and minimized handling issues. During reflow the solder balls are self-centering (up to 50% off the pad), thus reducing placement problems during surface mount. Normally, because of the larger ball pitch (typically 1.27 mm) of a BGA over a QFP or PQFP, the overall package and board assembly yields can be better. From a performance perspective, the thermal and electrical characteristics can be better than that of conventional QFPs or PQFPs. The PBGA has an improved design-to-produc- tion cycle time and can also be used in few-chip-package (FCPs) and multi-chip modules (MCMs) configurations. BGAs are available in a variety of types, ranging from plastic overmolded BGAs called PBGAs, to flex tape BGAs (TBGAs), high thermal metal top BGAs with low profiles (HL- PBGAs), and high thermal BGAs (H-PBGAs). The H-PBGA family includes Intel's latest packaging technology - the Flip Chip (FC)-style, H-PB- GA. The FC-style, H-PBGA component uses a Controlled Collapse Chip Connect die packaged in an Organic Land Grid Array (OLGA) substrate. In addition to the typical advantages of PBGA pack- ages, the FC-style H-PBGA provides multiple, low-inductance connections from chip to package, as well as, die size and cost benefits. -
2 LGA1366 Socket
Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor Series and LGA1366 Socket Thermal and Mechanical Design Guide March 2011 Document Number: 320837-005 2 Thermal and Mechanical Design Guide INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.