A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-Μm Sige Bicmos

Article A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-µm SiGe BiCMOS

Lei Luo 1,2 , Zhiqun Li 1,2,*, Yan Yao 1,2 and Guoxiao Cheng 1,2

1 Institute of RF-& OE-ICs, Southeast University, Nanjing 210096, China; [email protected] (L.L.); [email protected] (Y.Y.); [email protected] (G.C.) 2 Engineering Research Center of RF-ICs and RF-Systems, Ministry of Education, Southeast University, Nanjing 210096, China * Correspondence: [email protected]; Tel.: +86-25-8379-3303

Received: 19 September 2019; Accepted: 9 October 2019; Published: 11 October 2019

Abstract: A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-µm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate ﬂoating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99–9.33 dB; the maximum relative attenuation is 31.87–30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58–0.36 dB and the phase error RMS is 2.06–3.46 in the 12–17 GHz frequency range. The total chip area is 1 0.9 mm2. ◦ × Keywords: digital step attenuator; low phase variation; triple well isolation NMOS; wideband; CMOS integrated circuits

1. Introduction The attenuator is one of the key components of modern communications. It is widely used in the transmitter/receiver (T/R) module of phased array radar system [1,2], and its main function is to achieve amplitude control. Compared with the X-type attenuator [3] and variable gain ampliﬁer (VGA) [4,5], the passive digital step attenuator has the advantages of low power consumption, high linearity, wide frequency band and low temperature drift. Therefore, the design of attenuator with high resolution, large attenuation, low IL and low phase variation has great value, and very broad application prospects. A variety of passive attenuator circuits have been designed in [6–24]. There are three most-used topologies in the passive attenuators: Switched path attenuators [6–9], distributed attenuators [10,11] and switched T/Pi attenuators [12–24]. Switched path attenuators topology use single-pole-double-throw (SPDT) switches to control the signal between reference thru line path and the resistive attenuation network path. This topology exhibits low phase variation, but has high insertion loss and large chip area, so it is not suitable for multi-bit CMOS digital step attenuator. Transistors as varistors and the half/quarter-wavelength of the transmission lines (TLs) together constitute the distributed attenuators topology. Due to the relative attenuation signal paths across the transmission lines have no series switches, this topology has the advantage of low IL. Meanwhile, the use of the TLs greatly increases the chip area. Switched T/Pi attenuators topology is composed by the resistor attenuation network and series shunt single-pole-single-throw (SPST) switches. Its chip area is very compact and suitable for multi-bit integration.

Electronics 2019, 8, 1149; doi:10.3390/electronics8101149 www.mdpi.com/journal/electronics Electronics 2019, 8, x FOR PEER REVIEW 2 of 16

Electronicscomposed2019 by, 8 , 1149the resistor attenuation network and series shunt single-pole-single-throw (SPST)2 of 15 switches. Its chip area is very compact and suitable for multi-bit integration. In order to meet the designdesign requirements of phased array system for attenuators with high resolution, largelarge attenuation,attenuation, low low IL IL and and low low phase phase change, change this， paperthis paper proposed proposed a 6-bit a CMOS 6-bit CMOS digital digitalstep attenuator step attenuator using switched using switched T/Pi topology. T/Pi topo Thelogy. switches The areswitches designed are anddesigned optimized and optimized by TWNMOS by TWNMOSand through-silicon-via and through-silicon-via (TSV), in order (TSV), to improvein order theto improve performance the performance and reduce the and IL reduce of the switches.the IL of theMoreover, switches. the attenuatorMoreover, adopted the attenuator substrate ﬂoatingadopted and substrate new capacitance floating compensation and new capacitance technology, whichcompensation improved technology, linearity and which reduced improved the phase linearity variation. and reduced the phase variation.

2. Proposed Proposed Circuit Design and Analysis The switch is one of the key building blocks in th thee digital step attenuator [25,26]. [25,26]. In In this this paper, paper, the triple triple well well isolation isolation NMOS NMOS is is adopted adopted in in the the swit switchch shown shown in inFigure Figure 1a.1 a.Figure Figure 1b,c1b,c illustrate illustrate the simplifiedthe simplified equivalent equivalent circuits circuits for foron-state on-state and and off-state off-state of ofthe the switch. switch. As As shown shown in in Figure Figure 11,, thethe on-resistance RRchchand and parasitic parasitic resistance resistance at source at source and drainand terminalsdrain terminals of NMOS of switch NMOS will switch contribute will contributeto the insertion to the loss insertion in the signal loss in path. the signal The parasitic path. The capacitors parasitic C GScapacitors,CGD,C SBCGSand, CGD CDB, CSBwill and contribute CDB will contributeto the off-capacitance to the off-capacitance Coff of NMOS Coff switch of NMOS and switch act as a and leak act path as froma leak input path tofrom output input at to the output off-state. at Athe large off-state. resistor A large RG (10 resistor kΩ) is usedRG (10 to k prevent) is used the to RF prevent signal fromthe RF leaking signal through from leaking the bias through line. Body the biasfloating line. technique Body floating is used technique to improve is used power to handling improve of power the switch handling by reducing of the switch the signal by reducing loss through the signalsource /lossdrain-to-body through source/drain-to-body junctions. To implement junctions. thistechnique, To implement a large this resistor technique, RB (10 a large kΩ) isresistor added R toB (10the bodyk) is terminal added ofto thethe switchbody terminal to enhance of thethe linearity switch to and enhance insertion the loss linearity performance. and insertion Meanwhile, loss TSVperformance. is utilized Meanwhile, to provide approximatelyTSV is utilized ideal to provide global current approximately ground plane ideal withglobal low current impedance ground for planethe attenuator. with low impedance for the attenuator.

Figure 1. ((a)) The NMOS switch in the proposed attenuator; (b) The on-stateon-state simplifiedsimplified equivalent circuits of the switch; (c) The ooff-stateff-state simplifiedsimplified equivalentequivalent circuitscircuits ofof thethe switch.switch.

Inductive andand capacitivecapacitive correction correction structure structure digital digi steptal step attenuator attenuator is adopted is adopted in [18] in to achieve[18] to achievelow phase low variations. phase variations. Although Although the inductance the induct correctionance correction structure structure can achieve can lowachieve IL, it low occupies IL, it occupiesa large chip a large area. chip Capacitance area. Capacitance correction structurecorrection has structure the advantages has the ofadvantages lower phase of variationlower phase and variationbetter agreement and better with agreement simulation with results simulation in the broadbandresults in the frequency broadband range, frequency but it has range, larger but IL it than has largerinductance IL than correction inductance structure. correction In order structure. to solve In theorder contradiction to solve the between contradiction large ILbetween and low large phase IL variationand low phase of capacitance variation correction of capacitance structure, correction especially structure, large attenuation especially large units, attenuation such as 8 dB units, and 16such dB asattenuation 8 dB and cells.16 dB A attenuation new capacitance cells. A compensation new capacitance technique compensation is proposed technique in this paper. is proposed The topology in this of the proposed capacitance compensation correction network attenuation cell circuits in the digital step attenuator is shown in Figure2.

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paper. The topology of the proposed capacitance compensation correction network attenuation cell circuits in the digital step attenuator is shown in Figure 2. Electronics 2019, 8, 1149 3 of 15

Figure 2. (a) The proposed T-type attenuator topology with capacitance compensation correction network; (b) The reference state equivalent circuit; (c) The attenuation state equivalent circuit; (d) The equivalentFigure 2. ( circuita) Theof proposed the capacitance T-type compensationattenuator topology correction with network capacitance at the compensation attenuation state. correction network; (b) The reference state equivalent circuit; (c) The attenuation state equivalent circuit; (d) InThe the equivalent proposed circuit circuit of the structure, capacitance a parallelcompensati capacitoron correction CP is network added at to the the attenuation shunt branch state. of the traditional T-type attenuator in Figure2a. R on is the on-resistance, and Coff is the off-capacitance of the transistor.In the proposed When the circuit switch structure, M1 is on, a parallel and M2 capacitoris off, the C attenuatorP is added works to the in shunt the reference branch of state. the Thetraditional signalpasses T-type through attenuator the in series Figure path, 2a. as R shownon is the in on-resistance, Figure2b. When and the Coff switch is the Moff-capacitance1 is off, and M of2 isthe on, transistor. it works When in the the attenuation switch M state.1 is on, The and signal M2 is flows off, the from attenuator the shunt works attenuation in the reference branch to state. the ground,The signal as shownpasses inthrough Figure the2c. Parallelseries path, capacitor as shown C P isin introduced Figure 2b. asWhen a phase the switch correction M1 is device off, and in the M2 attenuationis on, it works branch. in the Therefore, attenuation the state. correction The sign networkal flows will from affect the the shunt performance attenuation of the branch attenuation to the state.ground, In orderas shown to facilitate in Figure the 2c. theoretical Parallel capacitor analysis, C theP is TSVintroduced and body as a series phase parasitic correction inductance device in arethe neglected.attenuation The branch. simplified Therefore, equivalent the correction circuit of netw the phaseork will correction affect the branch performance is as shown of the in attenuation Figure2d, andstate. the In transmission order to facilitate phase the of the theoretical network analys can beis, derived the TSV from and the body transmission series parasitic (ABCD) inductance matrix of theare attenuationneglected. The state; simplified the equation equivalent of transmission circuit of phase the phaseθ can correction be deduced branch as follows is as (seeshown Appendix in FigureA for 2d, detailedand the derivation):transmission phase of the network can be derived from the transmission (ABCD) matrix of the attenuation state; the equation of transmission phase  can be deduced as follows (see Appendix 2 CpRp(Z0 + Rs) A for detailedθ = derivation):tan 1 − , (1) − 4 2 2 (Rp + Ron)(2Rp + 2Ron + Z0 + R2s)/ω + 2RpCpω + RpCp(Z0 + Rs) 1 CRpp() Z0 R s   tan 42 2 , (1) where ω is the operating angular()(22Rp  Ron frequency. R p R on Z0 is Z00 the R s characteristic )/2 RC p p impedance. RC p p () Z R For s simplicity, all parameters in the equation are treated as the constant except the operating angular frequency ω. where  is the operating angular frequency. Z0 is the characteristic impedance. For simplicity, all The theoretical mathematical analysis image of function θ can be drawn using MATLAB in parameters in the equation are treated as the constant except the operating angular frequency . Figure3a. The slope of θ changes from negative to positive value at the broadband angular frequency The theoretical mathematical analysis image of function  can be drawn using MATLAB in range. When the slope is zero, there exists a critical frequency f (f = ω/2π), which can be used to correct Figure 3a. The slope of  changes from negative to positive value at the broadband angular the transmission phase error. frequency range. When the slope is zero, there exists a critical frequency f (f = /2), which can be Figure3b shows the practical simulation results in 0.13 µm SiGe BiCMOS process of the used to correct the transmission phase error. transmission phase of the phase correction branch in Figure2d. The transmission phase varies with parallel Cp value (swept from 60 fF to 180 fF) at the broadband frequency range. Figure3a,b possess a similar variation tendency, which verifies the theoretical analysis results in Equation (1). Figure4a shows the proposed T-type attenuator topology transmission phases of reference and attenuation states are simulated with various parallel capacitor Cp value. The phases of attenuation states have the same variation trend as those of the phase correction branch in Figure3b.

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Figure 3. (a) The theoretical mathematical analysis image of equation (1); (b) The practical simulation results of the transmission phase of the phase correction branch in 0.13 m SiGe BiCMOS.

Figure 3b shows the practical simulation results in 0.13 m SiGe BiCMOS process of the transmission phase of the phase correction branch in Figure 2d. The transmission phase varies with parallel Cp value (swept from 60 fF to 180 fF) at the broadband frequency range. Figure 3a,b possess a similar variation tendency, which verifies the theoretical analysis results in Equation (1). Figure 4a shows the proposed T-type attenuator topology transmission phases of reference and attenuation states are simulated with various parallel capacitor Cp value. The phases of attenuation

states have the same variation trend as those of the phase correction branch in Figure 3b. FigureFigure 3. 3.( a(a)) The The theoretical theoretical mathematical mathematical analysis analysis image image of of Equation equation (1); (1); ( b(b)) The The practical practical simulation simulation µ resultsresults of of the the transmission transmission phase phase of of the the phase phase correction correction branch branch in in 0.13 0.13 mm SiGe SiGe BiCMOS. BiCMOS.

FigureFigure 4. 4.( a(a)) The The simulatedsimulated transmissiontransmission phase results of of the the proposed proposed T-type T-type attenuator attenuator topology topology of of reference and attenuation states with various C value; (b) the phase difference of reference and reference and attenuation states with various Cp value; (b) the phase difference of reference and attenuation states with various C value. attenuation states with various Cp p value. It is obvious that the capacitance variation influences the attenuation state significantly, whereas, It is obvious that the capacitance variation influences the attenuation state significantly, it has less effect on the reference state. By adjusting the capacitance Cp value, we can control the whereas, it has less effect on the reference state. By adjusting the capacitance Cp value, we can transmission phase of reference and attenuation states to intersect at different frequencies to produce control the transmission phase of reference and attenuation states to intersect at different frequencies zero phase difference. The low phase difference in a specific frequency band can be achieved by to produce zero phase difference. The low phase difference in a specific frequency band can be choosing the appropriate capacitance Cp value, as shown in Figure4b. achieved by choosing the appropriate capacitance Cp value, as shown in Figure 4b. Figure5a shows the simulation attenuation results with traditional T-type and proposed C p T-type Figure 5a shows the simulation attenuation results with traditional T-type and proposed Cp topology in 4 dB attenuation cell. The simulation phase difference results with traditional T-type and T-typeFigure topology 4. (a) The in simulated4 dB attenuation transmission cell. phase The resultssimulation of the phaseproposed difference T-type attenuator results with topology traditional of proposedreference Cp T-type and attenuation topology in states 4 dB with attenuation various cellCp value; is illustrated (b) the inphase Figure difference5b. With of C referencep compensation and circuit attenuation structure, states Flatness with of various the phase Cp value. difference is better in a wide bandwidth range.

It is obvious that the capacitance variation influences the attenuation state significantly, whereas, it has less effect on the reference state. By adjusting the capacitance Cp value, we can control the transmission phase of reference and attenuation states to intersect at different frequencies to produce zero phase difference. The low phase difference in a specific frequency band can be achieved by choosing the appropriate capacitance Cp value, as shown in Figure 4b. Figure 5a shows the simulation attenuation results with traditional T-type and proposed Cp T-type topology in 4 dB attenuation cell. The simulation phase difference results with traditional

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T-type and proposed Cp T-type topology in 4 dB attenuation cell is illustrated in Figure 5b. With Cp compensationElectronics 2019, 8 circuit, 1149 structure, Flatness of the phase difference is better in a wide bandwidth range.5 of 15

Figure 5. (a) The simulation attenuation results with traditional T-type and proposed Cp T-type Figure 5. (a) The simulation attenuation results with traditional T-type and proposed Cp T-type topology in 4 dB attenuation cell; (b) the simulation phase difference results with traditional T-type and topology in 4 dB attenuation cell; (b) the simulation phase difference results with traditional T-type proposed Cp T-type topology in 4 dB attenuation cell. and proposed Cp T-type topology in 4 dB attenuation cell. Meanwhile, in order to study the influence of TSV on phase difference, parasitic parameters of Meanwhile, in order to study the influence of TSV on phase difference, parasitic parameters of TSV with different sizes can be obtained by the electromagnetic field (EM) simulation. Table1 shows TSV with different sizes can be obtained by the electromagnetic field (EM) simulation. Table 1 shows parasitic inductance and resistance of TSV with different sizes. parasitic inductance and resistance of TSV with different sizes. Table 1. Parasitic inductance and resistance of TSV with different sizes. Table 1. Parasitic inductance and resistance of TSV with different sizes. Number of Row Vias. Number of Column Vias Parasitic Inductance (pH) Parasitic Resistance (mΩ) Number of column Parasitic Parasitic resistance Number1 of row vias. 3 33 37 2 2vias inductance 28 (pH) (m 26) 11 73 2333 37 17 12 122 1728 26 9 2 7 15 10 21 57 1123 17 5 21 1212 817 9 5 22 227 615 10 3 2 5 11 5 TSV is utilized2 to provide approximately12 ideal global current8 ground plane with low5 impedance for the attenuator.2 Take the proposed C22p T-type topology in 4 dB6 attenuation cell as an3 example, the TSV connected to the switch body terminal mainly provides on-chip grounding of the substrate, and TSV is utilized to provide approximately ideal global current ground plane with low its effect on the phase variation of the attenuator can be neglected. The TSV connected to capacitance impedance for the attenuator. Take the proposed Cp T-type topology in 4 dB attenuation cell as an compensation correction branch of the attenuation cell also provides on-chip grounding. The parallel example, the TSV connected to the switch body terminal mainly provides on-chip grounding of the capacitor Cp grounding terminal of the capacitance compensation correction branch in attenuation substrate, and its effect on the phase variation of the attenuator can be neglected. The TSV connected cell is not ideal, which results in an additional phase variation of the attenuator circuit. Although the to capacitance compensation correction branch of the attenuation cell also provides on-chip effect of TSV on attenuator performance is small, it cannot be ignored. The simulation phase difference grounding. The parallel capacitor Cp grounding terminal of the capacitance compensation correction results with TSV size variation in proposed Cp T-type topology in 4 dB attenuation cell is illustrated in branch in attenuation cell is not ideal, which results in an additional phase variation of the Figure6. In microwave and millimeter wave bands, TSV will inevitably introduce parasitic inductance attenuator circuit. Although the effect of TSV on attenuator performance is small, it cannot be and resistance. The parasitic parameters are related to their size (i.e., the number of rows and columns ignored. The simulation phase difference results with TSV size variation in proposed Cp T-type vias). The larger the size, the smaller the parasitic inductance and resistance, but the bigger size will topology in 4 dB attenuation cell is illustrated in Figure 6. In microwave and millimeter wave bands, occupy a large area of the layout, so a compromise should be considered. After careful consideration, TSV will inevitably introduce parasitic inductance and resistance. The parasitic parameters are the TSV size of 2 5 was selected in this design. related to their size× (i.e., the number of rows and columns vias). The larger the size, the smaller the parasitic inductance and resistance, but the bigger size will occupy a large area of the layout, so a compromise should be considered. After careful consideration, the TSV size of 2  5 was selected in this design.

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Figure 6. The simulation phase difference results with TSV size variation in proposed Cp T-type topologyFigure in 6. 4 dBThe attenuation simulation cell. phase difference results with TSV size variation in proposed Cp T-type topology in 4 dB attenuation cell. The proposed capacitance compensation correction network and switch are also applicable to the Pi and bridge-TThe proposed type attenuation capacitance cells. compensation They have correction the same operationnetwork and principle switch to are realize also lowapplicable phase to differencethe Pi and as the bridge-T proposed type T-type attenuation attenuator cells. topology. They have the same operation principle to realize low phase difference as the proposed T-type attenuator topology. Traditional capacitance Cc and Cp compensation correction networks are widely used in the digital controlTraditional step attenuator capacitance circuit Cc and [18, 20C,p21 compensation], but there are correction large insertion networks losses, are especially widely inused large in 8 the digital control step attenuator circuit [18,20,21], but there are large insertion losses, especially in and 16 dB attenuation units. In order to solve this problem, a parallel capacitor Cp is added to the attenuationlarge 8 and shunt 16 dB branch attenuation in 8 and units. 16 dB In attenuation order to solve cells. this Take problem, 16 dB attenuation a parallel capacitor unit as an Cp example: is added to the attenuation shunt branch in 8 and 16 dB attenuation cells. Take 16 dB attenuation unit as an Figure7a shows the simulation IL results with traditional C c and proposed Cc + Cp compensation in example: Figure 7a shows the simulation IL results with traditional Cc and proposed Cc + Cp 16 dB attenuation cell. The IL decreases obviously with the increase of frequency in the proposed Cc + compensation in 16 dB attenuation cell. The IL decreases obviously with the increase of frequency in Cp compensation structure. The simulated attenuation, phase difference results with traditional Cc the proposed Cc + Cp compensation structure. The simulated attenuation, phase difference results and proposed Cc + Cp compensation in 16 dB attenuation cell is illustrated in Figure7b. With C c + Cp compensationwith traditional circuit C structure,c and proposed the attenuation Cc + Cp andcompensation phase difference in 16 dB change attenuation more smoothly cell is illustrated in a wide in frequencyFigure band.7b. With Cc + Cp compensation circuit structure, the attenuation and phase difference change more smoothly in a wide frequency band.

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Figure 7. (a) The simulation insertion loss results with traditional Cc and proposed Cc + Cp compensation in 16 dB attenuation cell; (b) the simulation attenuation, phase difference results with Figure 7. (a) The simulation insertion loss results with traditional Cc and proposed Cc + Cp compensation traditional Cc and proposed Cc + Cp compensation in 16 dB attenuation cell. Figurein 16 dB 7. attenuation (a) The simulation cell; (b) the insertion simulation loss attenuation, results with phase traditional difference Cc results and proposed with traditional Cc + C Cpc compensationand proposed in Cc 16+ CdBp compensationattenuation cell; in ( 16b) dBthe attenuation simulation cell.attenuation, phase difference results with traditionalThrough theCc and above proposed theoretical Cc + C pand compensation simulation in analys 16 dB is,attenuation in the proposed cell. 6-bit digital control step attenuatorThrough circuit, the above0.5 db, theoretical 1 db, 2 dB andand simulation4 dB attenuation analysis, units in theadopt proposed the proposed 6-bit digital parallel control capacitor step attenuatorCp compensationThrough circuit, the above 0.5method, db, theoretical 1 db, which 2 dB andandreduces 4simulation dB attenuationthe additional analys unitsis, phasein adopt the proposedshift the proposed of attenuation. 6-bit parallel digital Incontrol capacitor the largestep Cp attenuatorcompensationattenuation circuit, unit method, (8 0.5 db, db, which 16 1 db,db), reduces 2 wedB combineand the 4 additionaldB theattenuation traditional phase units shift capacitance adopt of attenuation. the compensationproposed In the parallel large method attenuation capacitor with Cunitthep compensation proposed (8 db, 16 db), parallel method, we combine capacitance which the reduces traditional Cp compensation the capacitance additional method, compensationphase shiftwhic hof method reducesattenuation. withthe theInproblems proposedthe large of attenuationparallelexcessive capacitance insertion unit (8 db, Clossp compensation16 anddb), largewe combine phase method, theshift which traditional fluctuation reduces capacitance therange problems in compensationthe of traditional excessive method insertion capacitance with loss theandcompensation proposed large phase method.parallel shift fluctuation capacitance range Cp in compensation the traditional method, capacitance whic compensationh reduces the method. problems of excessiveThe utilized insertion attenuation attenuation loss and cell celllarge topology topology phase inshift in 6-bit 6-bit fluctuation CMOS CMOS digital digital range control control in the step step traditional attenuator attenuator capacitanceis shown is shown in compensationinFigure Figure 8. 80.5dB,. 0.5 method. dB,1dB 1 and dB and2dB 2attenuation dB attenuation cells are cells configured are configured with switched with switched bridge-T bridge-T type in type Figure in Figure8a. 4dBThe8a. utilizedattenuation 4dB attenuation attenuation cell is cell configured cell is configuredtopology with in with 6-bitswitched switched CMOS T-type digital T-type in control in Figure Figure step 8b.8b. attenuator The switchedswitched is shown Pi-typePi-type in Figuretopology 8. 0.5dB, inin Figure Figure 1dB8c 8cand is suitableis 2dB suitable attenuation for largefor large attenuation cells attenuation are configured cells, suchcells, withassuch 8 and switched as 168 dBand cells.bridge-T 16 dB The cells. blocktype Thein diagram Figure block 8a.ofdiagram the4dB proposed attenuation of the proposed 6-bit cell digital is6-bit configured control digital step control with attenuator stepswitched attenuator is shown T-type inis shownin Figure Figure 9in. Figure8b. The 9. switched Pi-type topology in Figure 8c is suitable for large attenuation cells, such as 8 and 16 dB cells. The block diagram of the proposed 6-bit digital control step attenuator is shown in Figure 9.

Figure 8. The utilized attenuation cell topology in 6-bit CMOS digital control step attenuator, (a) Figure 8. The utilized attenuation cell topology in 6-bit CMOS digital control step attenuator. Proposed Bridged-T type topology, (b) Proposed T-type topology and (c) Proposed Pi-type topology.

Figure 8. The utilized attenuation cell topology in 6-bit CMOS digital control step attenuator.

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FigureFigure 9. 9.The The block block diagramdiagram of the proposed 6-bit 6-bit digital digital control control step step attenuator. attenuator.

TheThe component component values values of eachof each attenuator attenuator unit unit are are summarized summarized in Tablein Table2. The 2. 6-bitThe 6-bit CMOS CMOS digital controldigital step control attenuator step attenuator circuit is circuit optimized is optimize in termsd ofin linearity,terms of linearity, loading eloadingffect and effect power and processing power ability.processing Finally, ability. the bitFinally, ordering the bit 0.5-4-8-2-1-16 ordering 0.5-4-8-2-1-16 dB sequence dB issequence adopted is inadopted this paper. in this The paper. proposed The proposed attenuator is controlled by the 6-bit digital signal control circuit array, Vc1, Vc2, Vc3, Vc4, Vc5, attenuator is controlled by the 6-bit digital signal control circuit array, Vc1,Vc2,Vc3,Vc4,Vc5,Vc6, which areV usedc6, which to control are used 0.5 to dB, control 1 dB, 0.5 2 dB,dB, 41 dB,dB, 82 dB, 4 16 dB, dB 8 attenuationdB, 16 dB attenuation modules, modules, respectively. respectively. The layout The layout of series/parallel resistors are the key components in the attenuator design; and the of series/parallel resistors are the key components in the attenuator design; and the resistance values resistance values need to be carefully selected. In particular, small resistance values are realized by need to be carefully selected. In particular, small resistance values are realized by parallel connection parallel connection of large resistance to reduce the influence of process variation effects. The power of large resistance to reduce the influence of process variation effects. The power consumption of the consumption of the attenuator is extremely low, which is contributed by the dynamic power attenuator is extremely low, which is contributed by the dynamic power consumption of inverters in consumption of inverters in each attenuation module. each attenuation module. Table 2. Component values of each proposed attenuator unit. Table 2. Component values of each proposed attenuator unit. Atten. W1,3,5 W2,4,6,7 Cc Cp Atten. (dB) TopologyTopology R (ΩR)Rs () (ΩR)Ro () (ΩR)Rp () (ΩR)Wc () (µm) W (µm) C (fF) C (fF) (dB) s o p c 1,3,5(m) (2,4,6,7m) (fF) c (fF) p 0.5 Bridge-T 5.92 40.9 368 0 40 15 0 17 10.5 Bridge-TBridge-T 15.75.92 74.140.9 1293368 00 90 40 15 20 0 0 17 17 21 Bridge-TBridge-T 20.715.7 164.674.1 8731293 00 8090 20 20 0 017 83 42 T-typeBridge-T 15.320.7 0164.6 90.5873 00 8080 20 15 0 083 50.7 8 Pi-type 0 0 91.1 53.7 60 15 84.2 58.1 164 Pi-type T-type 015.3 00 50.190.5 70.60 20 80 15 15 0 102.550.7 152.2 8 Pi-type 0 0 91.1 53.7 60 15 84.2 58.1 16 Pi-type 0 0 50.1 70.6 20 15 102.5 152.2 The full chip electromagnetic (EM) simulation of the proposed 6-bit digital control step attenuator except resistors,The full chip capacitors electromagnetic and NMOS (EM) switch simulation transistors of componentsthe proposed is realized6-bit digital in ADS control Momentum step inattenuator order to further except ensureresistors, the capacitors performance. and NMOS The transmission switch transistors RF lines componen betweents is the realized circuits in ofADS each attenuationMomentum cell in areorder used to tofurther connect ensure each the module, performance. which improvesThe transmission the matching RF lines performance between the and adjustscircuits the of transmission each attenuation phase cell characteristics. are used to co Bothnnect inputeach andmodule, output which impedances improves ofthe the matching proposed performance and adjusts the transmission phase characteristics. Both input and output impedances attenuator are matched to 50 Ω. of the proposed attenuator are matched to 50 . 3. Measurement Results 3. Measurement Results The proposed 6-bit digital control step attenuator has been designed and fabricated in 0.13-µm The proposed 6-bit digital control step attenuator has been designed and fabricated in 0.13-m SiGe BiCMOS technology. The die photograph of the proposed 6-bit digital control step attenuator is SiGe BiCMOS technology. The die photograph of the proposed 6-bit digital control step attenuator is depicted in Figure 10. The total chip size is 1 0.9 mm2. All the DC Pads are bond wired to a PCB depicted in Figure 10. The total chip size is 1  ×0.9 mm2. All the DC Pads are bond wired to a PCB for for chip testing, and the chip is probed with Cascade’s 100 µm ground-signal-ground (GSG) probes chip testing, and the chip is probed with Cascade’s 100 m ground-signal-ground (GSG) probes at atthe input and output ports. ports. The The power power consumptio consumptionn of of the the proposed proposed attenuator attenuator is isextremely extremely low low andand negligible. negligible.

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Figure 10. The die photograph of the proposed 6-bit6-bit digital control step attenuator.

The input return lossloss (RL)(RL) isis >>1313 dB in Figure 1111aa andand thethe outputoutput returnreturn lossloss isis >>14.114.1 dB in Figure 1111bb at at 10–18 10–18 GHz GHz for for the the 64 states. 64 states. Figure Figure 12 shows 12 shows the measured the measured insertion insertion loss (of theloss reference (of the state)reference is 6.99–9.33 state) is dB6.99–9.33 and IP dB1dB and(of theIP−1dB reference (of the state)reference is 13.6–16.2 state) is dBm 13.6–16.2 at 12–17 dBm GHz. at 12–17 The maximumGHz. The − attenuationmaximum attenuation relative to that relative of the to reference that of the state reference is 31.87–30.31 state is dB 31.8 with7–30.31 0.5-dB dB step with (64 0.5-dB states) atstep 12–17 (64 GHzstates) in at Figure 12–17 13 GHz. The in measured Figure 13. results The measured show that theresults root show mean that square the (RMS) root mean for the square amplitude (RMS) error for isthe 0.58–0.36 amplitude dB anderror the is RMS0.58–0.36 phase dB error and is the 2.06–3.46 RMS ◦phasein the error 12–17 is GHz 2.06–3.46 frequency in rangethe 12–17 for the GHz 64 statesfrequency in Figure range 14 for. The the RMS64 states for thein Figure amplitude 14. The error RMS can for be deﬁnedthe amplitude as: error can be defined as:

N v 1 2 tu N ARMSAA m__ i theo i  dB, (2) 1 X2 A = N i1(A A ) (dB), (2) RMS N m_i − theo_i i=1 where ARMS is the attenuation RMS amplitude error, I is the attenuation state index, N is 64, Am_i is the wheremeasuredARMS attenuationis the attenuation relative RMS to amplitudethe reference error, inI is a the given attenuation state, stateand index,Atheo_i Nis isthe 64, theoreticalAm_i is the measuredattenuation attenuation in a given relativestate. The to theRMS reference phase error in a givenfor the state, attenuation and Atheo_i is calculatedis the theoretical using the attenuation equation indefined a given as state.follows: The RMS phase error for the attenuation is calculated using the equation deﬁned as follows: M uv 1 2 t M deg RMS1 X m__ i ref m 2, (3) θ = M i1 θ θ (deg), (3) RMS M m_i − re f _m i=1 where RMS is the attenuation RMS phase error, i is the attenuation state index, M is 64, m_i is the wheremeasuredθRMS attenuationis the attenuation relative phase RMS phase in a given error, state,i is the and attenuation ref_m is the state measured index, attenuationM is 64, θm_i relativeis the measuredphase in the attenuation reference state. relative phase in a given state, and θref_m is the measured attenuation relative phase in the reference state.

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Electronics 2019, 8, x FOR PEER REVIEW 10 of 16 Electronics 2019, 8, 1149 10 of 15

Figure 11. (a) The measured input return loss of the proposed attenuator; (b) the measured output return loss of the proposed attenuator. Figure 11. (a) The measured input return loss of the proposed attenuator; (b) the measured output return loss of the proposed attenuator. FigureFigure 11. 11.( a(a)) The The measured measured input input return return loss loss of of the the proposed proposed attenuator; attenuator; ( b(b)) the the measured measured output output returnreturn loss loss of of the the proposed proposed attenuator. attenuator.

Figure 12. The measured insertion loss and IP-1dB of the proposed attenuator.

Figure 12. The measured insertion loss and IP of the proposed attenuator. Figure 12. The measured insertion loss and IP-1dB-1dB of the proposed attenuator.

Figure 12. The measured insertion loss and IP-1dB of the proposed attenuator.

Figure 13. (a) The measured 64-state relative attenuation of the proposed attenuator; (b) the measured 64-stateFigure relative 13. The insertion measured phase 64-state of the proposedrelative attenuatio attenuator.n and phase of the proposed attenuator.

Figure 13. The measured 64-state relative attenuation and phase of the proposed attenuator.

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FigureFigure 14. 14. TheThe measured measured RMS RMS amplitude amplitude error error and and ph phasease error error of of the the proposed proposed attenuator. attenuator. 4. Comparison with Relevant Digital Control Step Attenuators 4. Comparison with Relevant Digital Control Step Attenuators This work is compared with other recently published similar digital control step attenuators This work is compared with other recently published similar digital control step attenuators in in Table3. The proposed 6-bit digital control step attenuator has better insertion loss compared Table 3. The proposed 6-bit digital control step attenuator has better insertion loss compared with with [16–18] and the higher IP–1dB than [13,16,21]. Compared with [12,13,17], this design has wide [16–18] and the higher IP–1dB than [13,16,21]. Compared with [12,13,17], this design has wide frequency coverage. Even compared with all references in Table3, the RMS phase error of this design frequency coverage. Even compared with all references in Table 3, the RMS phase error of this has considerable competitive advantage. In this paper, the design of a 6-bit digital attenuator with design has considerable competitive advantage. In this paper, the design of a 6-bit digital attenuator low insertion loss and small RMS phase error in Ku-band (12–17 GHz) is realized by using substrate with low insertion loss and small RMS phase error in Ku-band (12–17 GHz) is realized by using ﬂoating technology and the proposed capacitance compensation technology. substrate floating technology and the proposed capacitance compensation technology.

Table 3. Performance comparison of relevant digital control step attenuators. Table 3. Performance comparison of relevant digital control step attenuators. [12] [13] [16] [17] [18] [21] Reference [12] [13] [16] [17] [18] [21] This Work Reference 2017 2017 2016 2018 2010 2018 This Work Frequency (GHz)2017 19–212017 14–182016 6–12.52018 20–24 2010 DC–14 2018 DC–20 12–17 0.18 µm 0.35 µm 0.25 µm 0.13 µm 0.18 µm 0.13 µm 0.13 µm Frequency(GHz)Technology 19–21 14–18 6–12.5 20–24 DC–14 DC–20 12–17 CMOS BiCMOS BiCMOS BiCMOS CMOS BiCMOS BiCMOS 0.18 0.18 Number of Bits 60.35 m 60.25 m 70.13 m 6 60.13 m 6 0.13 6m TechnologyAttenuation Rang (dB)m 32 31.5 16.51 31.5m 31.5 31.5 31.87–30.31 Attenuation Step (dB) 0.5BiCMOS 0.5BiCMOS 0.26 BiCMOS 0.5 0.5BiCMOS 0.5 BiCMOS 0.5 RL (dB) CMOS >12 >10 >13 >9 CMOS>10 >12 >13 IL (dB) <8 8 0.6 <12.7 20.9–21.95 <10 1.7–7.2 6.99–9.33 Number of Bits 6 6 ± 7 6 6 6 6 RMS Amplitude Error (dB) N/A <0.29 <0.26 <0.43 <0.5 <0.37 0.58–0.36 Attenuation RMS Phase Error (◦) 32 <3.831.5 <3.916.51 2.2–3.531.5 1.6–4.2 31.5< 4.2 31.5 <431.87–30.31 2.06–3.46 RangIP (dB)1dB (dBm) N/A 10 12.5 14 15 10 13.6–16.2 − 2 1 1 1 2 1 2 2 AttenuationDie area Step (mm ) 0.45 0.27 0.29 0.77 0.5 0.98 0.9 0.5 0.5 1. 0.26 2. 0.5 0.5 0.5 0.5 (dB) excluding pads including pads. RL(dB) >12 >10 >13 >9 >10 >12 >13 5. ConclusionsIL (dB) <8 80.6 <12.7 20.9–21.95 <10 1.7–7.2 6.99–9.33 RMS Amplitude This paper hasN/A presented <0.29 a 12–17 GHz <0.26 6-bit digital <0.43 control <0.5 step attenuator<0.37 with0.58–0.36 low phase Error(dB) imbalance in 0.13-µm SiGe BiCMOS technology. In this design, a parallel capacitor C is added to the RMS Phase p attenuation shunt branch<3.8 of the<3.9 traditional 2.2–3.5 Pi, T and bridge-T1.6–4.2 type<4.2 attenuation <4 cells to 2.06–3.46form a phase Error() correction network with the parallel resister. Furthermore, in order to study the influence of TSV on IP–1dB (dBm) N/A 10 12.5 14 15 10 13.6–16.2 phase difference, parasitic parameters of TSV with different sizes can be obtained by an electromagnetic Die area(mm2) 0.451 0.271 0.291 0.772 0.51 0.982 0.92 field (EM) simulation. After careful consideration, the TSV size of 2 5 was selected in this design. 1. excluding pads 2. including pads. × As far as the author knows, this is the first 6-bit digital attenuator designed with TSV. The influence of TSV on attenuator performance is also analyzed and verified. With the help of these techniques, the transmission phase error of the attenuation state can be corrected, thus, leading to a low phase imbalance. Meanwhile, substrate floating technology is adopted to reduce switches insertion loss and

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5. Conclusions This paper has presented a 12–17 GHz 6-bit digital control step attenuator with low phase imbalance in 0.13-m SiGe BiCMOS technology. In this design, a parallel capacitor Cp is added to the attenuation shunt branch of the traditional Pi, T and bridge-T type attenuation cells to form a phase correction network with the parallel resister. Furthermore, in order to study the influence of TSV on phase difference, parasitic parameters of TSV with different sizes can be obtained by an electromagnetic field (EM) simulation. After careful consideration, the TSV size of 2  5 was selected in this design. As far as the author knows, this is the first 6-bit digital attenuator designed with TSV. The influence of TSV on attenuator performance is also analyzed and verified. With the help of these techniques, the transmission phase error of the attenuation state can be corrected, thus, leading to a low phase imbalance. Meanwhile, substrate floating technology is adopted to reduce switches Electronicsinsertion2019 loss, 8 ,and 1149 improve linearity. The proposed attenuator achieves the RMS phase error12 ofless 15 than 3.46 and amplitude error less than 0.58 dB over 12–17 GHz. It has a maximum attenuation range of 31.87 dB with the approximate 0.5-dB step. In addition, good input/output return loss, high improve linearity. The proposed attenuator achieves the RMS phase error less than 3.46◦ and amplitude IP–1dB, moderate chip area and wide bandwidth are obtained, which makes it suitable to use in error less than 0.58 dB over 12–17 GHz. It has a maximum attenuation range of 31.87 dB with the Ku-band phased array systems. approximate 0.5-dB step. In addition, good input/output return loss, high IP–1dB, moderate chip area and wide bandwidth are obtained, which makes it suitable to use in Ku-band phased array systems. Author Contributions: Formal analysis, L.L., Y.Y. and G.C.; Funding acquisition, Z.L.; Investigation, L.L., Y.Y. Authorand G.C.; Contributions: Methodology,Formal L.L., Y.Y. analysis, and G.C.; L.L., Supervision, Y.Y. and G.C.; Z.L.; Funding Writing acquisition, – original draft, Z.L.; Investigation,L.L.; Writing – L.L., review Y.Y. and editing, G.C.; Methodology, Y.Y. and G.C. L.L., Y.Y. and G.C.; Supervision, Z.L.; Writing—original draft, L.L.; Writing—review and editing, Y.Y. and G.C. Funding: This research was funded by National Natural Science Foundation of China, grant number 61474021. Funding: This research was funded by National Natural Science Foundation of China, grant number 61474021. Acknowledgments: The authors would like to thank the Global Foundries for the fabrication and Keysight for Acknowledgments:ADS EM Design support.The authors would like to thank the Global Foundries for the fabrication and Keysight for ADS EM Design support. Conflicts of Interest: The authors declare no conflict of interest. Conﬂicts of Interest: The authors declare no conﬂict of interest.

Appendix A For T-network conﬁguration,configuration, ABCD-parameters rela relatete the voltages to current in the following form for a two-port network:

I1 I2 ZA ZB Port1+ + Port2

ZC V1 V2

VAVBI V 112=AV BI (A1)(1.1) 1 1 − 2 I1 = CV1 DI2 (A2) I112CV− DI (1.2) Which can be put in matrix form as Which can be put in matrix form as " # " #" # V1 AB V1 VV11= AB  . (A3) I  CD I2 . (1.3) 1 −  I12CD I  The ABCD parameters in Equation (A3) are deﬁned as The ABCD parameters in Equation (1.3) are defined as

= V1 = V1 A V I2=0 A I V2=0 2 − 2 . (A4) = I1 = I1 C V I2=0 D I V2=0 2 − 2 The ABCD network is useful in ﬁnding the voltage or current gain of a component or the overall gain of a network. One of the great advantages of ABCD parameters is their use in cascaded network or components. When this condition exists, the overall ABCD parameter of the network becomes the matrix product of an individual network and a component. For T-network conﬁguration, Parameters A and C are determined when Port2 is open circuited as ! V1 ZC ZC + ZA A = I2=0 V2 = V1 A = , (A5) V2 → ZC + ZA → ZC and ! ! I1 1 1 C = I2=0 I1 = V2 C = . (A6) V2 → ZC → ZC Electronics 2019, 8, 1149 13 of 15

Parameters B and D are determined when Port2 is short circuited as ! V1 V1 ZC ZAZB + ZAZC + ZBZC B = V =0 I2 = − B = , (A7) I 2 → Z + (Z //Z ) (Z + Z ) → Z − 2 A B C B C C and ! ! I1 ZC ZB + ZC D = − V2=0 I2 = I1 D = . (A8) I2 → − ZB + ZC → ZC Therefore, the T-network ABCD matrix is

" #  ZC+ZA ZAZB+ZAZC+ZBZC  AB  Z Z  =  C C . (A9) CD  1 ZB+ZC  ZC ZC

Simpliﬁed the equivalent circuit of phase correction branch, as shown in Figure2d, the transmission phase of the network is derived from the transmission (ABCD) matrix for the attenuation state. According to Equation (A9), we can get the Figure2d ABCD parameters of the network as follows: 1 + jRpωCp (Ron + Rs) + Rp A = , (A10) Ron 1 + jRpωCc + Rp

2 2RsRon + Rs 1 + jRpωCp + 2RsRp B = , (A11) Ron 1 + jRpωCp + Rp

1 + jRpωCp C = , (A12) Ron 1 + jRpωCp + Rp (Rs + Ron) 1 + jRpωCp + Rp D = . (A13) Ron 1 + jRpωCp + Rp

Assume that the matching impedance of Port 1 and Port 2 is Z0, according to the theory of microwave network, the insertion phase θ of the T-network can be calculated by the following equation:

2 Im AZ0 + B + CZ + DZ0 1 0 θ = tan− . (A14) + + 2 + Re AZ0 B CZ0 DZ0

Im and Re represent the imaginary part and the real part of the formula, respectively.

2 Im AZ0 + B + CZ + DZ0 =  0  + 2 2 2 2 + 2 + 2 2 2 2  2Rs 1 Rpω Cp RpωCpZ0 Rs 1 Rpω Cp RpωCp  (A15)   − + 2 + 2 2 2 2  Z0 1 Rpω Cp RpωCp

Due to R2ω2C2 1, the formula can be simpliﬁed to (A16) p p

2 2 2 2 2 2 Im AZ + B + CZ + DZ = 2RsR ωCpZ + R R ωCp + Z R ωCp , (A16) 0 0 0 − p 0 s p 0 p + + 2 + = 2 + + + Re AZ0 B CZ0 DZ0 Z0 Rp Ron 2Z0Rs Rp Ron 2 2 2 2 2 +Rs Rp + Ron + 2Z0 Rp + Ron + 2Rs Rp + Ron + 2 RpωCp (Zo + Rs), (A17) 2 2 +RpωCp(Zo + Rs) Electronics 2019, 8, 1149 14 of 15

2 RpωCp(Z0 + Rs) θ = tan 1 − , (A18) − 2 2 2 2 Rp + Ron (Z0 + Rs) + 2 Rp + Ron + 2 RpωCp + RpωCp(Z0 + Rs)

2 CpRp(Z0 + Rs) θ = tan 1 − . (A19) − 4 2 2 (Rp + Ron)(2Rp + 2Ron + Z0 + Rs)/ω + 2RpCpω + RpCp(Z0 + Rs) The appendix gives a detailed derivation of Formula (1) in this paper.

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