electronics Article A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-µm SiGe BiCMOS Lei Luo 1,2 , Zhiqun Li 1,2,*, Yan Yao 1,2 and Guoxiao Cheng 1,2 1 Institute of RF-& OE-ICs, Southeast University, Nanjing 210096, China; [email protected] (L.L.); [email protected] (Y.Y.); [email protected] (G.C.) 2 Engineering Research Center of RF-ICs and RF-Systems, Ministry of Education, Southeast University, Nanjing 210096, China * Correspondence: [email protected]; Tel.: +86-25-8379-3303 Received: 19 September 2019; Accepted: 9 October 2019; Published: 11 October 2019 Abstract: A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-µm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate floating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99–9.33 dB; the maximum relative attenuation is 31.87–30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58–0.36 dB and the phase error RMS is 2.06–3.46 in the 12–17 GHz frequency range. The total chip area is 1 0.9 mm2. ◦ × Keywords: digital step attenuator; low phase variation; triple well isolation NMOS; wideband; CMOS integrated circuits 1. Introduction The attenuator is one of the key components of modern communications. It is widely used in the transmitter/receiver (T/R) module of phased array radar system [1,2], and its main function is to achieve amplitude control. Compared with the X-type attenuator [3] and variable gain amplifier (VGA) [4,5], the passive digital step attenuator has the advantages of low power consumption, high linearity, wide frequency band and low temperature drift. Therefore, the design of attenuator with high resolution, large attenuation, low IL and low phase variation has great value, and very broad application prospects. A variety of passive attenuator circuits have been designed in [6–24]. There are three most-used topologies in the passive attenuators: Switched path attenuators [6–9], distributed attenuators [10,11] and switched T/Pi attenuators [12–24]. Switched path attenuators topology use single-pole-double-throw (SPDT) switches to control the signal between reference thru line path and the resistive attenuation network path. This topology exhibits low phase variation, but has high insertion loss and large chip area, so it is not suitable for multi-bit CMOS digital step attenuator. Transistors as varistors and the half/quarter-wavelength of the transmission lines (TLs) together constitute the distributed attenuators topology. Due to the relative attenuation signal paths across the transmission lines have no series switches, this topology has the advantage of low IL. Meanwhile, the use of the TLs greatly increases the chip area. Switched T/Pi attenuators topology is composed by the resistor attenuation network and series shunt single-pole-single-throw (SPST) switches. Its chip area is very compact and suitable for multi-bit integration. Electronics 2019, 8, 1149; doi:10.3390/electronics8101149 www.mdpi.com/journal/electronics Electronics 2019, 8, x FOR PEER REVIEW 2 of 16 Electronicscomposed2019 by, 8 , 1149the resistor attenuation network and series shunt single-pole-single-throw (SPST)2 of 15 switches. Its chip area is very compact and suitable for multi-bit integration. In order to meet the designdesign requirements of phased array system for attenuators with high resolution, largelarge attenuation,attenuation, low low IL IL and and low low phase phase change, change this， paperthis paper proposed proposed a 6-bit a CMOS 6-bit CMOS digital digitalstep attenuator step attenuator using switched using switched T/Pi topology. T/Pi topo Thelogy. switches The areswitches designed are anddesigned optimized and optimized by TWNMOS by TWNMOSand through-silicon-via and through-silicon-via (TSV), in order (TSV), to improvein order theto improve performance the performance and reduce the and IL reduce of the switches.the IL of theMoreover, switches. the attenuatorMoreover, adopted the attenuator substrate floatingadopted and substrate new capacitance floating compensation and new capacitance technology, whichcompensation improved technology, linearity and which reduced improved the phase linearity variation. and reduced the phase variation. 2. Proposed Proposed Circuit Design and Analysis The switch is one of the key building blocks in th thee digital step attenuator [25,26]. [25,26]. In In this this paper, paper, the triple triple well well isolation isolation NMOS NMOS is is adopted adopted in in the the swit switchch shown shown in inFigure Figure 1a.1 a.Figure Figure 1b,c1b,c illustrate illustrate the simplifiedthe simplified equivalent equivalent circuits circuits for foron-state on-state and and off-state off-state of ofthe the switch. switch. As As shown shown in in Figure Figure 11,, thethe on-resistance RRchchand and parasitic parasitic resistance resistance at source at source and drainand terminalsdrain terminals of NMOS of switch NMOS will switch contribute will contributeto the insertion to the loss insertion in the signal loss in path. the signal The parasitic path. The capacitors parasitic C GScapacitors,CGD,C SBCGSand, CGD CDB, CSBwill and contribute CDB will contributeto the off-capacitance to the off-capacitance Coff of NMOS Coff switch of NMOS and switch act as a and leak act path as froma leak input path tofrom output input at to the output off-state. at Athe large off-state. resistor A large RG (10 resistor kW) is usedRG (10 to k prevent) is used the to RF prevent signal fromthe RF leaking signal through from leaking the bias through line. Body the biasfloating line. technique Body floating is used technique to improve is used power to handling improve of power the switch handling by reducing of the switch the signal by reducing loss through the signalsource /lossdrain-to-body through source/drain-to-body junctions. To implement junctions. thistechnique, To implement a large this resistor technique, RB (10 a large kW) isresistor added R toB (10the bodyk) is terminal added ofto thethe switchbody terminal to enhance of thethe linearity switch to and enhance insertion the loss linearity performance. and insertion Meanwhile, loss TSVperformance. is utilized Meanwhile, to provide approximatelyTSV is utilized ideal to provide global current approximately ground plane ideal withglobal low current impedance ground for planethe attenuator. with low impedance for the attenuator. Figure 1. ((a)) The NMOS switch in the proposed attenuator; (b) The on-stateon-state simplifiedsimplified equivalent circuits of the switch; (c) The ooff-stateff-state simplifiedsimplified equivalentequivalent circuitscircuits ofof thethe switch.switch. Inductive andand capacitivecapacitive correction correction structure structure digital digi steptal step attenuator attenuator is adopted is adopted in [18] in to achieve[18] to achievelow phase low variations. phase variations. Although Although the inductance the induct correctionance correction structure structure can achieve can lowachieve IL, it low occupies IL, it occupiesa large chip a large area. chip Capacitance area. Capacitance correction structurecorrection has structure the advantages has the ofadvantages lower phase of variationlower phase and variationbetter agreement and better with agreement simulation with results simulation in the broadbandresults in the frequency broadband range, frequency but it has range, larger but IL it than has largerinductance IL than correction inductance structure. correction In order structure. to solve In theorder contradiction to solve the between contradiction large ILbetween and low large phase IL variationand low phase of capacitance variation correction of capacitance structure, correction especially structure, large attenuation especially large units, attenuation such as 8 dB units, and 16such dB asattenuation 8 dB and cells.16 dB A attenuation new capacitance cells. A compensation new capacitance technique compensation is proposed technique in this paper. is proposed The topology in this of the proposed capacitance compensation correction network attenuation cell circuits in the digital step attenuator is shown in Figure2. Electronics 2019, 8, x FOR PEER REVIEW 3 of 16 paper. The topology of the proposed capacitance compensation correction network attenuation cell circuits in the digital step attenuator is shown in Figure 2. Electronics 2019, 8, 1149 3 of 15 Figure 2. (a) The proposed T-type attenuator topology with capacitance compensation correction network; (b) The reference state equivalent circuit; (c) The attenuation state equivalent circuit; (d) The equivalentFigure 2. ( circuita) Theof proposed the capacitance T-type compensationattenuator topology correction with network capacitance at the compensation attenuation state. correction network; (b) The reference state equivalent circuit; (c) The attenuation state equivalent circuit; (d) InThe the equivalent proposed circuit circuit of the structure, capacitance a parallelcompensati capacitoron correction CP is network added at to the