Philips Semiconductors Preliminary Speciﬁcation

INTEGRATED CIRCUITS

DATA SHEET

SAA4997H VErtical Reconstruction IC (VERIC) for PALplus

Preliminary speciﬁcation 1996 Oct 24 File under Integrated Circuits, IC02 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

FEATURES GENERAL DESCRIPTION • PALplus decoding The VErtical Reconstruction IC (VERIC) for PALplus • Vertical reconstruction (VERIC) is especially designed for use in conjunction with the Motion Adaptive Colour Plus And Control IC • Quadrature mirror filter (MACPACIC) to decode the transmitted PALplus video • Luminance and chrominance processing signal in PALplus colour TV receivers. It provides the full • Controlling. vertical resolution of a PALplus picture from the letter box part and the decoded helper information.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. MAX. UNIT

VDD supply voltage − 5.25 V

Tamb operating ambient temperature 0 70 °C

ORDERING INFORMATION

TYPE PACKAGE NUMBER NAME DESCRIPTION VERSION SAA4997H QFP64 plastic quad ﬂat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm SOT319-2

1996 Oct 24 2 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

BLOCK DIAGRAMS TRSTN Y_VE_0 to 7 OE_FM2 TDO_VE RE_FM3 RSTR_FM23 OE_FM3 U/V_VE_0/1 RE_FM2 56 39 55 40 30 29 54

MGE443 4 8 36 CLK_32B3 UV FORMATTER 23 C / CLK_16B2 SAA4997H F 28 26 27 BOUNDARY SCAN TEST bypass multi-PIP mode select (LP-FILTER) PROCESSING 5 CHROMINANCE 8 8 4

handbook, full pagewidth FM-control UV-control C / multi-PIP F bypass UV Fig.1 Block diagram. EVEN_FIELD TDI TCK TMS REFORMATTER INTPOL DELAY Y - UV FM CONTROL LOGIC 21 20 22 Y-control COMPENSATOR FILM PIXEL SELECT LUMINANCE (QM-FILTER) PROCESSING 8 8 DECODER DECODER LINE COUNTER PIXEL COUNTER PIXEL SELECT 8 4 19 17 VA_AI HREF_MA Y_FM23_0 to 7 U/V_FM23_0/1

1996 Oct 24 3 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus V_VE_[0,1] TDO_VE OE_FM3 U_VE_[0,1] OE_FM2 RE_FM2 RE_FM3 RSTR_FM23 8 4

MGE444 V_VE_0,1 U_VE_0,1 Vertical Y_VE_0 to 7 Y_VE_[0 to 7] VERIC Reconstruction IC - Inverse QMF reconstruction filter - Vertical chrominance SRC - FM2/FM3 read control U_FM23_0,1 V_FM23_0,1 Y_FM23_0 to 7 8 4 4 11 4 3 NC TDI 8 8 4 4 TCK TMS FILM VA_AI SS1-4 DD1-4 TRSTN V V INTPOL TEST1-3 HREF_MA CLK_16B2 CLK_32B3 EVEN_FIELD FM2 FM3 TMS4C2970 TMS4C2970 CLK_32B3 CLK_32B1 4 4 8 8 (1) (1) (1)

ook, full pagewidth CLK_16B1, 2, 3 CLK_32B1, 2, 3 WE_FM3 V_TO_FM1_1 VA_AI HREF_MA WE_FM1, RE_FM1 RST_FM14 WE_FM4, RE_FM4 WE_MA FILM EVEN_FIELD INTPOL TDO_MA Y_TO_FM1_0 to 7 U_TO_FM1_0 WE_FM2 U_TO_FM1_1 RSTW_FM23 V_TO_FM1_0 CLK_16B1 2 2 8 4 8 3 3 4 U_MA_0,1 V_MA_0,1 V_FM4_0,1 U_FM4_0,1 Y_MA_0 to 7 FM4 Fig.2 Block diagram of the PALplus decoder module. 4 TMS4C2970 . MACPACIC and Control IC SS - BB-decompanding - Motion adaptive luminance/chrominance separation - Memory control - PALplus control - Clock generation - Sync generation - SNERT interface Motion Adaptive Colour Plus V_TO_FM4_0,1 U_TO_FM4_0,1 Y_ADC_0 to 7 U_ADC_0,1 V_ADC_0,1 Y_FM1_0 to 7 U_FM1_0,1 V_FM1_0,1 8 3 5 5 4 (2) TDI TCK TMS SS1-5 DD1-5 SRCK TRSTN CLAMP V V CLK_16 CLK_32 TEST1-3 8 4 FM1 SNERT_CL SNERT_DA VA_FRONT WE_FRONT SNERT_RST TMS4C2970 VERIC_AV_N SWCK CLK_16 CLK_16B1 Y_FRONT[0 to 7] V_FRONT[0,1] U_FRONT[0,1] (1) In case of stand alone MACPACIC the output signals are U_TO_FM1_1, V_TO_FM1_0 or V_TO_FM1_1; otherwise WE_FM2, RSTW_FM23 WE_FM3. (2) VERIC available: VERIC_AV_N is connected to V

1996 Oct 24 4 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

PINNING

SYMBOL PIN TYPE DESCRIPTION Y_VE_1 1 output luminance output data bit 1 Y_VE_0 2 output luminance output data bit 0 U_VE_1 3 output chrominance output data bit 1 U-component U_VE_0 4 output chrominance output data bit 0 U-component V_VE_1 5 output chrominance output data bit 1 V-component V_VE_0 6 output chrominance output data bit 0 V-component

VSS1 7 input ground 1

VDD1 8 input positive supply voltage 1 (+5 V) n.c. 9 − not connected n.c. 10 − not connected n.c. 11 − not connected n.c. 12 − not connected n.c. 13 − not connected n.c. 14 − not connected n.c. 15 − not connected n.c. 16 − not connected HREF_MA 17 input horizontal reference n.c. 18 − not connected VA_AI 19 input vertical reference pulse related to output data INTPOL 20 input INTPOL = 1: PALplus interpolation active INTPOL = 0: VERIC switched to bypass mode (standard signal) FILM 21 input FILM = 0: CAMERA mode FILM = 1: FILM mode EVEN_FIELD 22 input EVEN_FIELD = 0: odd ﬁeld related to MACPACIC input data EVEN_FIELD = 1: even ﬁeld related to MACPACIC input data CLK_16B2 23 input buffered clock input (16 MHz)

VSS2 24 input ground 2

VDD2 25 input positive supply voltage 2 (+5 V) TCK 26 input boundary scan test clock input TMS 27 input boundary scan test mode select input TDI 28 input boundary scan test data input TDO_VE 29 output boundary scan test data output TRSTN 30 input boundary scan test reset input n.c. 31 − not connected n.c. 32 − not connected TEST1 33 tbf test pins TEST2 34 tbf TEST3 35 tbf CLK_32B3 36 input buffered clock input (32 MHz)

VSS3 37 input ground 3

1996 Oct 24 5 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

SYMBOL PIN TYPE DESCRIPTION

VDD3 38 input positive supply voltage 3 (+5 V) OE_FM3 39 output output enable field memory 3 RE_FM3 40 output read enable field memory 3 V_FM23_1 41 input chrominance input data bit 1 V-component V_FM23_0 42 input chrominance input data bit 0 V-component U_FM23_1 43 input chrominance input data bit 1 U-component U_FM23_0 44 input chrominance input data bit 0 U-component Y_FM23_7 45 input Y input data bit 7 Y_FM23_6 46 input Y input data bit 6 Y_FM23_5 47 input Y input data bit 5 Y_FM23_4 48 input Y input data bit 4 Y_FM23_3 49 input Y input data bit 3 n.c. 50 − not connected Y_FM23_2 51 input Y input data bit 2 Y_FM23_1 52 input Y input data bit 1 Y_FM23_0 53 input Y input data bit 0 RSTR_FM23 54 output reset read field memory 2 and 3 RE_FM2 55 output read enable field memory 2 OE_FM2 56 output output enable field memory 2

VDD4 57 input positive supply voltage 4 (+5 V)

VSS4 58 input ground 4 Y_VE_7 59 output luminance output data bit 7 Y_VE_6 60 output luminance output data bit 6 Y_VE_5 61 output luminance output data bit 5 Y_VE_4 62 output luminance output data bit 4 Y_VE_3 63 output luminance output data bit 3 Y_VE_2 64 output luminance output data bit 2

1996 Oct 24 6 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

handbook, full pagewidth DD4 SS4 V Y_FM23_1 OE_FM2 RE_FM2 Y_VE_3 RSTR_FM23 V Y_VE_4 Y_FM23_0 Y_VE_5 Y_VE_6 Y_VE_2 Y_VE_7 64 63 62 61 60 59 58 57 56 55 54 53 52

Y_VE_1 1 51 Y_FM23_2

Y_VE_0 2 50 n.c.

U_VE_1 3 49 Y_FM23_3

U_VE_0 4 48 Y_FM23_4

V_VE_1 5 47 Y_FM23_5

V_VE_0 6 46 Y_FM23_6

VSS1 7 45 Y_FM23_7

VDD1 8 44 U_FM23_0

n.c. 9 43 U_FM23_1

n.c. 10 SAA4997H 42 V_FM23_0

n.c. 11 41 V_FM23_1

n.c. 12 40 RE_FM3

n.c. 13 39 OE_FM3

n.c. 14 38 VDD3

n.c. 15 37 VSS3

n.c 16 36 CLK_32B3

HREF_MA 17 35 TEST3

n.c. 18 34 TEST2

VA_AI 19 33 TEST1

20 21 22 23 24 25 26 27 28 29 30 31 32 MGE442 TDI n.c. n.c. SS2 TCK DD2 TMS FILM V V TRSTN INTPOL TDO_VE CLK_16B2 EVEN_FIELD

Fig.3 Pin configuration.

1996 Oct 24 7 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

FUNCTIONAL DESCRIPTION The luminance vertical conversion process in the decoder is complementary to that of the encoder. Introduction In the decoder the inverse QMF function is implemented to As shown in Fig.2 the PALplus module consists of two recombine the two separated sub-bands and to generate special integrated circuits: the original video signal with 576 active lines per frame. • Motion Adaptive Colour Plus And Control IC (MACPACIC) Each output line is calculated from up to seven input lines stored in line memories containing main or helper • VErtical Reconstruction IC (VERIC) information. The various lines are multiplied by switched and four field memories TMS4C2970. coefficients, changing every line within a sequence of four lines, depending on the specific mode (CAMERA or FILM). The MACPACIC and the VERIC are intended to generate digitally decoded 50 Hz YUV signals. The MACPACIC In case of standard PAL reception, the VERIC is switched performs the decompanding function for the helper lines to bypass mode controlled by the signal INTPOL. and the motion adaptive luminance/chrominance For multi-PIP processing the VERIC is also switched to separation. Furthermore, PALplus system controlling, bypass mode, but controlling of FM2/3 is different (see memory controlling and clock generation are carried out in Fig.6). The total signal delay between the MACPACIC this circuit. input and the VERIC output is one line for this mode. The function of the VERIC is to reconstruct the separated FM2/3 are driven with 32 MHz clock frequency. 2 × 72 helper lines and the 430 main lines into a standard The non-multiplexed input data are clocked out with 576 lines frame according the PALplus system description 16 MHz. “REV 2.0”. Chrominance is converted from 430 lines to 576 lines using a vertical sample rate converter. Chrominance processing The data of the VERIC are clocked out with 16 MHz. The chrominance processing is carried out by the vertical The Y :U:V bandwidth ratio is 4:1:1. interpolation filter (poly phase filter). The functional block diagram of the VERIC is shown in In CAMERA and FILM mode, intra-field vertical sample Fig.1. The device consists of 3 main parts: rate conversion is carried out. • Luminance processing One output line is calculated out of three or four lines in • Chrominance processing CAMERA or FILM mode using different coefficients or passed through in bypass mode. • Controlling. The input data are delivered by the field memories FM2 Control functions and FM3, which include multiplexed first and second field The VERIC controller generates the necessary internal data processed by the MACPACIC. The luminance and control signals for the line memories, formatters, chrominance input data of the VERIC are clocked with reformatters, the selector signals for the multiplexers and 32 MHz (CLK_32B3). Internally the device operates at the read signals for the field memories FM2/3. 32 or 16 MHz clock frequency. The system control input signals EVEN_FIELD, INTPOL Luminance processing and FILM are derived from the control part of the MACPACIC. The field selection information EVEN_FIELD In the PALplus encoder the luminance signal is separated is related to the input data of the MACPACIC and is vertically into two sub-bands by a special Quadrature adapted in the VERIC to its input data. Mirror Filter (QMF). The control functions are described in Tables 1 and 2. A vertical low-pass sub-band consists of the 430 main letter box lines per frame, and a vertical high-pass Table 1 EVEN_FIELD sub-band includes the 144 helper lines per frame. The used QMF technique has two advantages: VALUE STATUS • Essentially loss-free data processing EVEN_FIELD = 1 even ﬁeld selected • Cancellation of alias components in the main and helper EVEN_FIELD = 0 odd ﬁeld selected signal in the decoder.

1996 Oct 24 8 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

Table 2 INTPOL and FILM Table 3 Delays

VALUE STATUS MODE FIELD VERIC I/O DELAY INTPOL = 0 FILM = 0 bypass mode; FILM mode ﬁrst 2 lines standard signals second 3 lines INTPOL = 1 FILM = 0 interpolation active; CAMERA mode ﬁrst 3 lines PALplus CAMERA mode second 4 lines INTPOL = 0 FILM = 1 bypass mode; multi-PIP INTPOL = 1 FILM = 1 interpolation active; Input/Output formats PALplus FILM mode INPUT FORMATS Modes and delays The luminance input range of the main and helper signal has the following values: The PALplus module can operate in two different hardware configurations: Main signal: black = 16, white = 191 (straight binary) • Full PALplus configuration (MACPACIC and VERIC) Helper signal: ±70, mid = 128 (straight binary) • Stand alone MACPACIC. Chrominance format: ±90, mid = 0 (two’s complement). The vertical interpolation of the VERIC can be activated by OUTPUT FORMATS the signal INTPOL depending on the PALplus signalling bits, transmitted in line 23 indicating the type of signal Luminance format: black = 16, white = 191 (straight being received. binary) However, the delay between input data of the MACPACIC Blanking: code 16 and output data of the VERIC always has to be 1.5 fields. Chrominance format: ±90, mid = 0 (two’s complement) This is achieved with a suitable read timing of the field Blanking: code 0. memories FM2 and FM3 controlled by VA_AI which is derived from the field length measurement in the Test activities MACPACIC. The pins TEST1, TEST2 and TEST3 are provided to In case of INTPOL = LOW and additionally FILM = HIGH perform the IC test activities, such as scan test. (FILM mode), the VERIC is switched to multi-PIP mode. In case the delay between input of the MACPACIC and The pins TRSTN, TDI, TMS, TCK and TDO_VE are output of the VERIC is one line (1024 CLK_16 periods). intended for a boundary scan test. The line and pixel timings of the VERIC are shown in Figures 5 to 14.

1996 Oct 24 9 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

DC CHARACTERISTICS

Tj = 0 to 125 °C SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply

VDD supply voltage 4.75 5.0 5.25 V IDD supply current VDD =5V −− 80 mA IDD(q) quiescent supply current all inputs to VDD or VSS −− 100 µA Inputs

VIL LOW level input voltage −0.5 − +0.8 V VIH HIGH level input voltage 2.0 − VDD V ILI input leakage current −− 1.0 µA Outputs

VOL LOW level output voltage IO =20µA −− 0.1 V VOH HIGH level output voltage IO =20µAVDD − 0.1 −−V IOL LOW level output current VO = 0.5 V 4.0 −−mA IOH HIGH level output current VO =VDD − 0.5 V 4.0 −−mA

AC CHARACTERISTICS

Tj = 0 to 125 °C SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Clock timing CLK_32B3 (see Fig.4)

TCY(32) cycle time 28.1 31.25 − ns

tH HIGH time 9.2 −−ns

tL LOW time 9.2 −−ns tr rise time 2.0 − 4.0 ns tf fall time 2.0 − 4.0 ns

∆fclk deviation of clock frequency −10 − +10 % Clock timing CLK_16B2 (see Fig.4)

TCY(16) cycle time 56.2 −−ns

tH HIGH time 20.5 −−ns

tL LOW time 20.5 −−ns tr rise time 2.0 − 4.0 ns tf fall time 4.0 − 4.0 ns δ duty cyclet 40 − 50 % δ = ----H- tL

1996 Oct 24 10 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Input data timing (CLK_32)

tsu input data set-up time CLK_16B2 −4.7 −−ns Y and UV_FM23 −0.8 −−ns

th(i) input data hold time CLK_16B2 5.1 −−ns Y and UV_FM23 5.2 −−ns Input control timing (CLK_16B2)

HREF_MA, VA_AI, FILM, EVEN_FIELD AND INTPOL

tsu input data set-up time 4.5 −−ns th(i) input data hold time 0.1 −−ns Output data timing (CLK_16B2)

Y AND UV_FM23

th(o) output data hold time CL =15pF 8 −−ns td(o) output data delay time CL =15pF −− 27 ns Output control timing (CLK_32B3)

OE_FM2, OE_FM3, RE_FM2, RE_FM3 AND RSTR_FM23

th(o) output data hold time CL =15pF 5 −−ns td(o) output data delay time CL =15pF −− 20 ns Delays

tw(HREF) HREF_MA pulse width − 60 × TCY(16) − ns td(RE) delay − 127 × TCY(32) − ns RE_FM2/3 to HREF_MA

tw(RE) RE_FM2/3 pulse width − 1680 × TCY(32) − ns td(VE)(MA) delay HREF_MA to YUV_VE − 80 × TCY(16) − ns td(VE) delay data input to output − 16 × TCY(16) − ns td(VE) delay data input to output multi-PIP − 2 × TCY(16) − ns td(RSTR) delay RSTR multi-PIP − 2016 × TCY(32) − ns td(FM2) delay FM2 input to output multi-PIP − 2040 × TCY(32) − ns

1996 Oct 24 11 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

TIMING

handbook, full pagewidth tr tf 90% CLK 50% 10%

tH tL

DATA/CONTROL Dn XX D(n+1)

th(o) th(i) td(o) tsu MGE445

Data input: CLK = CLK_32B3 Data output: CLK = CLK_16B2 Control input: CLK = CLK_16B2 Control output: CLK = CLK_32B3

Fig.4 Data/control input/output set-up and hold timing.

1996 Oct 24 12 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE446

handbook, full pagewidth w(RE) t CY(32) T d(VE) t × Fig.5 Pixel timing (except multi-PIP mode). 1 d(VE)(MA) t d(RE) t w(HREF) t HREF_MA RE_FM2/3 CLK_32B3 CLK_16B2 Y(U/V)_VE Y(U/V)_FM23

1996 Oct 24 13 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE447 23 3 1 3 d(VE) t 1122

handbook, full pagewidth 1024 pixels d(FM2) t 33 22 d(RSTR) t 3 11 2 d(MA) t 1 d(RSTW) t Fig.6 Pixel timing multi-PIP mode (MACPACIC input to VERIC output). VA_AI YUV_VE YUV_MA YUV_FM2 YUV_ADC CLK_16B2 CLK_32B3 RSTR_FM2 RSTW_FM2 WE_FM2 and RE_FM2 are constant HIGH; YUV_MA = MACPACIC input.

1996 Oct 24 14 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE448 B V1 V0 U1 U0 Y839 836B 836B 836B 836B

handbook, full pagewidth Fig.7 Input data timing (except multi-PIP mode). field word Y0A Y0B Y1A Y1B Y2A Y2B Y3A Y3B Y4A Y4B Y5A Y5B Y6A Y6B Y7A Y7B Y8A Y8B V70A V50A V30A V10A V70B V50B V30B V10B V74AV60A V54A V40A V34A V20A V14A V00A V74B V60B V54B V40B V34B V20B V14B V00B V78A V64A V58A V44A V24A V04A V64B V44B V24B V04B V68A V48A U70A U50A U30A U10A U70B U50B U30B U10B U74A U54AU60A U34A U40A U14A U20A U74B U00A U54B U60B U34B U40B U14B U20B U78A U00B U58A U64A U44A U24A U04A U64B U44B U24B U04B U68A U48A V 6 0 A bit input signal RE_FM2/3 CLK_32B3 V_FM23_1 V_FM23_0 U_FM23_1 U_FM23_0 Y_FM23(0-7)

1996 Oct 24 15 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE449 0 0 0 0 16 Y V1 V0 U1 U0 836 836 836 836 839

handbook, full pagewidth Fig.8 Output data timing. Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 V70 V50 V30 V10 V74V60 V54 V40 V34 V20 V14 V00 V78 V64 V44 V24 V04 V68 U70 U50 U30 U10 U74U60 U54 U40 U34 U20 U14 U00 U78 U64 U44 U24 U04 U68 0 0 0 0 16 word bit V 6 0 input signal V_VE_1 V_VE_0 U_VE_1 U_VE_0 Y_VE(0-7) CLK_16B2

1996 Oct 24 16 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE450 311 311/623 145 lines 166 167 handbook, full pagewidth 166/478 167/479 146 lines 24 23 Fig.9 Line read timing FM2/3 bypass mode standard signal, first field. 22 21 25 26 27 multiplexed active lines from FM23 21/333 20 lines RE_FM2 RE_FM3 OE_FM2 OE_FM3 VA_AI YUV_FM23(0-7) Y/UV_VE

1996 Oct 24 17 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE451 623 311/623 145 lines 478 479 handbook, full pagewidth 166/478 167/479 146 lines 336 335 Fig.10 Line read timing FM2/3 bypass mode standard signal, second field. 334 333 337 338 339 multiplexed active lines from FM23 21/333 19 lines field B RE_FM2 RE_FM3 OE_FM2 OE_FM3 VA_AI YUV_FM23(0-7) Y/UV_VE

1996 Oct 24 18 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE452

full pagewidth 161 162 163 164 165 166 167 302 303 304 305 306 307 308 309 310 M11,10 UV11,10 H3,4 Fig.11 Line read timing FM2/3 CAMERA mode, first field. 24 23 25 26 27 H1,2 M7,6 M9,8 21 22 23 24 25 26 27 161 162 163 164 165 166 167 302 303 304 305 306 307 308 309 310 M3,2 M5,4 UV3,2 UV5,4 UV7,6 UV9,8 (1) VERIC line counter RE_FM3 RE_FM2 OE_FM3 OE_FM2 Y/UV_VE U/V_FM23 Y_FM23 (1) M = main line and H = helper line.

1996 Oct 24 19 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE453

handbook, full pagewidth 476 477 478 479 480 481 482 614 615 616 617 618 619 620 621 622 623 H3,4 M11,10 Fig.12 Line read timing FM2/3 CAMERA mode, second field. 336 337 338 339 20 21 22 23 24 25 26 160 161 162 163 164 165 166 301 302 303 304 305 306 307 308 309 310 3,2 5,4 7,6 9,8 11,12 M3,2 M5,4 H1,2 M7,6 M9,8 (1) VERIC line counter RE_FM3 RE_FM2 OE_FM3 OE_FM2 Y/UV_VE U/V_FM23(0-1) Y_FM23(0-7) (1) M = main line and H = helper line.

1996 Oct 24 20 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE454

handbook, full pagewidth 162 163 164 165 166 167 168 303 304 305 306 307 308 309 310 M11,10 UV11,10 H3,4 Fig.13 Line read timing FM2/3 FILM mode, first field. 25 24 M5,4 23 26 27 28 H1,2 M7,6 M9,8 M3,2 UV3,2 UV5,4 UV7,6 UV9,8 (1) RE_FM3 RE_FM2 OE_FM3 OE_FM2 Y/UV_VE U/V_FM23 Y_FM23 (1) M = main line and H = helper line.

1996 Oct 24 21 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

MGE455

handbook, full pagewidth 474 475 476 477 478 479 480 615 616 617 618 619 620 621 622 623 M11,10 H3,4 Fig.14 Line read timing FM2/3 FILM mode, second field. M7,6 M9,8 336 337 338 339 340 H1,2 M3,2 M5,4 (1) RE_FM3 RE_FM2 OE_FM3 OE_FM2 Y/UV_VE Y_FM23(0-7) (1) M = main line and H = helper line.

1996 Oct 24 22 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2

c y X

51 33 A 52 32 Z E

e Q A2 E H A (A ) E A1 3

θ w M pin 1 index Lp bp L

64 20 detail X 1 19

w M ZD v M A e bp

D B

HD v M B

0 5 10 mm scale

DIMENSIONS (mm are the original dimensions)

A (1) (1) (1) (1) θ UNITmax. A1 A2 A3 bp cED eHHD ELLp QZvwyZD E 0.25 2.90 0.50 0.25 20.1 14.1 24.2 18.2 1.0 1.4 1.2 1.2 7o mm 3.20 0.25 1 1.95 0.2 0.2 0.1 0.05 2.65 0.35 0.14 19.9 13.9 23.6 17.6 0.6 1.2 0.8 0.8 0o

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION 92-11-17 SOT319-2 95-02-04

1996 Oct 24 23 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

SOLDERING If wave soldering cannot be avoided, the following conditions must be observed: Introduction • A double-wave (a turbulent wave with high upward There is no soldering method that is ideal for all IC pressure followed by a smooth laminar wave) packages. Wave soldering is often preferred when soldering technique should be used. through-hole and surface mounted components are mixed • The footprint must be at an angle of 45° to the board on one printed-circuit board. However, wave soldering is direction and must incorporate solder thieves not always suitable for surface mounted ICs, or for downstream and at the side corners. printed-circuits with high population densities. In these situations reflow soldering is often used. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), This text gives a very brief insight to a complex technology. QFP100 (SOT317-1), QFP100 (SOT317-2), A more in-depth account of soldering ICs can be found in QFP100 (SOT382-1) or QFP160 (SOT322-1). our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must Reﬂow soldering be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe Reflow soldering techniques are suitable for all QFP dispensing. The package can be soldered after the packages. adhesive is cured. The choice of heating method may be influenced by larger Maximum permissible solder temperature is 260 °C, and plastic QFP packages (44 leads, or more). If infrared or maximum duration of package immersion in solder is vapour phase heating is used and the large packages are 10 seconds, if cooled to less than 150 °C within not absolutely dry (less than 0.1% moisture content by 6 seconds. Typical dwell time is 4 seconds at 250 °C. weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more A mildly-activated flux will eliminate the need for removal information, refer to the Drypack chapter in our “Quality of corrosive residues in most applications. Reference Handbook” (order code 9398 510 63011). Repairing soldered joints Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied Fix the component by first soldering two diagonally- to the printed-circuit board by screen printing, stencilling or opposite end leads. Use only a low voltage soldering iron pressure-syringe dispensing before package placement. (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When Several techniques exist for reflowing; for example, using a dedicated tool, all other leads can be soldered in thermal conduction by heated belt. Dwell times vary one operation within 2 to 5 seconds between between 50 and 300 seconds depending on heating 270 and 320 °C. method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.

Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.

1996 Oct 24 24 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

DEFINITIONS

Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1996 Oct 24 25 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

NOTES

1996 Oct 24 26 Philips Semiconductors Preliminary speciﬁcation

VErtical Reconstruction IC (VERIC) for SAA4997H PALplus

NOTES

1996 Oct 24 27 Philips Semiconductors – a worldwide company

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© Philips Electronics N.V. 1996 SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 537021/1200/01/pp28 Date of release: 1996 Oct 24 Document order number: 9397 750 01423