MICRONAS VPC 3205C, VPC 3215C Video Processor Family

PRELIMINARY DATA SHEET

Edition Oct. 19, 1998 6251-457-2PD MICRONAS VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

Contents

Page Section Title

4 1. Introduction 4 1.1. System Architecture 4 1.2. Video Processor Family 5 1.3. VPC Applications

6 2. Functional Description 6 2.1. Analog Front-End 6 2.1.1. Input Selector 6 2.1.2. Clamping 6 2.1.3. Automatic Gain Control 6 2.1.4. Analog-to-Digital Converters 6 2.1.5. Digitally Controlled Clock Oscillator 6 2.1.6. Analog Video Output 7 2.2. Adaptive Comb Filter 7 2.3. Color Decoder 8 2.3.1. IF-Compensation 8 2.3.2. Demodulator 8 2.3.3. Chrominance Filter 9 2.3.4. Frequency Demodulator 9 2.3.5. Burst Detection 9 2.3.6. Color Killer Operation 9 2.3.7. PAL Compensation/1-H Comb Filter 10 2.3.8. Luminance Notch Filter 10 2.3.9. Skew Filtering 11 2.4. Horizontal Scaler 11 2.5. Blackline Detector 11 2.6. Control and Data Output Signals 11 2.6.1. Line-Locked Clock Generation 12 2.6.2. Sync Signals 12 2.6.3. DIGIT3000 Output Format 12 2.6.4. Line-Locked 4:2:2 Output Format 12 2.6.5. Line-Locked 4:1:1 Output Format 12 2.6.6. Output Code Levels 12 2.6.7. Output Signal Levels 12 2.6.8. Test Pattern Generator 13 2.6.9. Priority Bus Codec 13 2.7. PAL+ Support 13 2.7.1. Output Signals for PAL+/Color+ Support 15 2.8. Video Sync Processing

17 3. Serial Interface 17 3.1. I2C-Bus Interface 17 3.2. Control and Status Registers 29 3.2.1. Calculation of Vertical and East-West Deflection Coefficients 29 3.2.2. Scaler Adjustment

2 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Contents, continued

Page Section Title

31 4. Specifications 31 4.1. Outline Dimensions 31 4.2. Pin Connections and Short Descriptions 33 4.3. Pin Descriptions (pin numbers for PLCC68 package) 35 4.4. Pin Configuration 36 4.5. Pin Circuits 37 4.6. Electrical Characteristics 37 4.6.1. Absolute Maximum Ratings 37 4.6.2. Recommended Operating Conditions 38 4.6.3. Recommended Crystal Characteristics 39 4.6.4. Characteristics 39 4.6.4.1. Characteristics, 5 MHz Clock Output 39 4.6.4.2. Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1) 39 4.6.4.3. Characteristics, Reset Input, Test Input 40 4.6.4.4. Characteristics, Priority, FPDAT Input/Output 40 4.6.4.5. Characteristics, VGAV Input 41 4.6.4.6. Characteristics, I2C Bus Interface 41 4.6.4.7. Characteristics, Analog Video Inputs 41 4.6.4.8. Characteristics, Analog Front-End and ADCs 43 4.6.4.9. Characteristics, Output Pin Specification 44 4.6.4.10. Characteristics, Input Pin Specification 45 4.6.4.11. Characteristics, Clock Output Specification

46 5. Application Circuit 47 5.1. VGA mode with VPC3215C

48 6. Data Sheet History

Micronas 3 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

Video Processor Family –I2C-Bus Interface – one 20.25 MHz crystal, few external components Release Note: Revision bars indicate significant changes to the previous edition. – 68-pin PLCC package

1. Introduction 1.1. System Architecture

The VPC 32x5 is a high-quality, single-chip video Fig. 1–1 shows the block diagram of the video proces- front-end, which is targeted for 4:3 and 16:9, 50/60 and sor. 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as CIP 3250A, DDP 3300A, TPU 3040) and/or it can be used 1.2. Video Processor Family with 3rd-party products. The VPC video processor family supports 15/32 kHz The main features of the VPC 32x5 are systems and is available with different comb filter options. The 50 Hz/single scan versions provide con- – all-digital video processing trolling for the display and the vertical/east west deflec- – high-performance adaptive 4H comb filter Y/C sepa- tion of DDP 3300A. The 100 Hz/double scan versions rator with adjustable vertical peaking have a line-locked clock output interface and the PAL+ preprocessing option. Table 1–1 gives an over- – multi-standard color decoder PAL/NTSC/SECAM view of the VPC video processor family. including all substandards – 4 composite, 1 S-VHS input, 1 composite output

– integrated high-quality A/D converters and associ- Table 1–1: VPC Processor Family ated clamp and AGC circuits

– multi-standard sync processing Features 50 Hz/ 100 Hz/ – linear horizontal scaling (0.25 ... 4), as well as single scan double scan non-linear horizontal scaling ‘panorama vision’ 4H comb filter VPC 3205C VPC 3215C – PAL+ preprocessing (VPC 3215) 2H comb filter VPC 3200A VPC 3210A – line-locked clock, data and sync output (VPC 3215) – display/deflection control (VPC 3205) no comb filter VPC 3201A VPC 3211A – submicron CMOS technology

V1 V2/Y Front-End Adaptive Color Horizontal Output Combfilter Decoder Scaler Formatter C V3 2*ADC, NTSC Panorama 8 bit PAL mode V4 SECAM YUV CVBS Out clock

Sync Processing Clock Gen. 2 H/V DCO I C line-locked clock synthesis

20.25 MHz I2C

Fig. 1–1: VPC 32x5C block diagram

4 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

1.3. VPC Applications The IP indicates memory based image processing, such as scan rate conversion, vertical processing Fig. 1–2 depicts several VPC applications. Since the (Zoom), or PAL+ reconstruction. VPC functions as a video front-end, it must be comple- Examples: mented with additional functionality to form a complete – Europe: 15 kHz/50 Hz → 32 kHz/100 Hz interlaced TV set. – US: 15 kHz/60 Hz → 32 kHz/60 Hz non-interlaced The DDP 33x0 contains the video back-end with video postprocessing (contrast, peaking, DTI,...), H/V-deflec- Note that the VPC supports memory based application, RGB insertion (SCART, Text, PIP,...) and tube tions through line-locked clocks, syncs, and data. CIP control (cutoff, white drive, beam current limiter). It may run either with the native DIGIT3000 clock but generates a beam scan velocity modulation output also with a line-locked clock system. from the digital YCrCb and RGB signals. Note that this signal is not generated from the external analog RGB inputs.

The CIP 3250A provides a high quality analog RGB interface with character insertion capability. This allows appropriate processing of external sources, such as MPEG2 set-top boxes in transparent (4:2:2) quality. Furthermore, it translates RGB/Fastblank signals to the common digital video bus and makes those signals available for 100 Hz upconversion or double scan processing. In some European countries (Italy), this feature is mandatory.

VPC DDP RGB CVBS 3300A a) 320x H/V RGB Defl.

VPC DDP RGB b) CVBS IP 3310B 321x H/V Defl.

VPC CIP DDP RGB CVBS 321x 3250A IP 3310B c) H/V RGB Defl.

Fig. 1–2: VPC 32xx applications a) 15 kHz application Europe b) double scan application (US, Japan) c) 100 Hz application (Europe) with RGB inputs

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2. Functional Description 2.1.3. Automatic Gain Control

2.1. Analog Front-End A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/–4.5 dB in This block provides the analog interfaces to all video 64 logarithmic steps to the optimal range of the ADC. inputs and mainly carries out analog-to digital conver- The gain of the video input stage including the ADC is sion for the following digital video processing. A block 213 steps/V with the AGC set to 0 dB. diagram is given in Fig. 2–1.

Most of the functional blocks in the front-end are digi- 2.1.4. Analog-to-Digital Converters tally controlled (clamping, AGC, and clock-DCO). The control loops are closed by the Fast Processor (‘FP’) Two ADCs are provided to digitize the input signals. embedded in the decoder. Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the required reference voltages for the converters. The 2.1.1. Input Selector two ADCs are of a 2-stage subranging type.

Up to five analog inputs can be connected. Four inputs are for input of composite video or S-VHS luma signal. 2.1.5. Digitally Controlled Clock Oscillator These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. One input is for The clock generation is also a part of the analog front connection of S-VHS carrier-chrominance signal. This end. The crystal oscillator is controlled digitally by the input is internally biased and has a fixed gain amplifier. control processor; the clock frequency can be adjusted within ±150 ppm.

2.1.2. Clamping 2.1.6. Analog Video Output The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling The input signal of the Luma ADC is available at the capacitors and is generated by digitally controlled cur- analog video output pin. The signal at this pin must be rent sources. The clamping level is the back porch of buffered by a source follower. The output voltage is the video signal. S-VHS chroma is also AC coupled. 2 V, thus the signal can be used to drive a 75 Ω line. The input pin is internally biased to the center of the The magnitude is adjusted with an AGC in 8 steps ADC input range. together with the main AGC.

Analog Video Output AGC +6/–4.5 dB VIN4 CVBS/Y digital CVBS or Luma VIN3 clamp ADC CVBS/Y VIN2 CVBS/Y gain VIN1 input mux CVBS/Y CIN bias ADC digital Chroma Chroma system clocks

DVCO ±150 reference frequency generation ppm

20.25 MHz

Fig. 2–1: Analog front-end

6 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

2.2. Adaptive Comb Filter HDG typically defines the comb strength on horizontal edges. It determines the amount of the remaining The 4H adaptive comb filter is used for high-quality cross-luminance and the sharpness on edges respec- luminance/chrominance separation for PAL or NTSC tively. As HDG increases, the comb strength, e. g. composite video signals. The comb filter improves the cross luminance reduction and sharpness, increases. luminance resolution (bandwidth) and reduces interfer- ences like cross-luminance and cross-color. The adap- VDG typically determines the comb filter behaviour on tive algorithm eliminates most of the mentioned errors vertical edges. As VDG increases, the comb strength, without introducing new artifacts or noise. e. g. the amount of hanging dots, decreases.

A block diagram of the comb filter is shown in Fig. 2–2. After selecting the combfilter performance in horizontal The filter uses four line delays to process the informa- and vertical direction, the diagonal picture perfor- tion of three video lines. To have a fixed phase rela- mance may further be optimized by adjusting DDR. As tionship of the color subcarrier in the three channels, DDR increases, the dot crawl on diagonal colored the system clock (20.25 MHz) is fractionally locked to edges is reduced. the color subcarrier. This allows the processing of all color standards and substandards using a single crys- To enhance the vertical resolution of the the picture, tal frequency. the VPC 32x5 provides a vertical peaking circuitry. The filter gain is adjustable between 0 – +6 dB and a coring The CVBS signal in the three channels is filtered at the filter suppresses small amplitudes to reduce noise arti- subcarrier frequency by a set of bandpass/notch fil- facts. In relation to the comb filter, this vertical peaking ters. The output of the three channels is used by the widely contributes to an optimal two-dimensional reso- adaption logic to select the weighting that is used to lution homogeneity. reconstruct the luminance/chrominance signal from the 4 bandpass/notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption 2.3. Color Decoder algorithm are completely suppressed. In this block, the standard luma/chroma separation The comb filter uses the middle line as reference, and multi-standard color demodulation is carried out. therefore, the comb filter delay is two lines. If the comb The color demodulation uses an asynchronous clock, filter is switched off, the delay lines are used to pass thus allowing a unified architecture for all color stan- the luma/chroma signals from the A/D converters to dards. the luma/chroma outputs. Thus, the processing delay is always two lines. A block diagram of the color decoder is shown in Fig. 2–4. The luma as well as the chroma processing, is In order to obtain the best-suited picture quality , the shown here. The color decoder also provides several user has the possibility to influence the behaviour of special modes, e.g. wide band chroma format which is the adaption algorithm going from moderate combing intended for S-VHS wide bandwidth chroma. Also, fil- to strong combing. Therfore, the following three para- ter settings are available for processing a PAL+ helper meters may be adjusted: signal. – HDG ( horizontal difference gain ) If the adaptive comb filter is used for luma chroma – VDG ( vertical difference gain ) separation, the color decoder uses the S-VHS mode processing. The output of the color decoder is YC C – DDR ( diagonal dot reducer ) r b in a 4:2:2 format.

Bandpass Filter CVBS Input Luma Output Bandpass/ 2H Delay Line Notch Filter Chroma Output Bandpass 2H Delay Line Filter Luma / Chroma Mixers Adaption Logic Chroma Input

Fig. 2–2: Block diagram of the adaptive comb filter (PAL mode)

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2.3.1. IF-Compensation 2.3.2. Demodulator

With off-air or mistuned reception, any attenuation at The entire signal (which might still contain luma) is higher frequencies or asymmetry around the color sub- quadrature-mixed to the baseband. The mixing fre- carrier is compensated. Four different settings of the quency is equal to the subcarrier for PAL and NTSC, IF-compensation are possible (see Fig. 2–3): thus achieving the chroma demodulation. For SECAM, the mixing frequency is 4.286 MHz giving the quadra- – flat (no compensation) ture baseband components of the FM modulated – 6 dB/octave chroma. After the mixer, a lowpass filter selects the chroma components; a downsampling stage converts – 12 dB/octave the color difference signals to a multiplexed half rate – 10 dB/MHz data stream.

The last setting gives a very large boost to high fre- The subcarrier frequency in the demodulator is gener- quencies. It is provided for SECAM signals that are ated by direct digital synthesis; therefore, substan- decoded using a SAW filter specified originally for the dards such as PAL 3.58 or NTSC 4.43 can also be PAL standard. demodulated.

2.3.3. Chrominance Filter

The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell-filter characteristic. At the output of the lowpass filter, all luma information is eliminated.

The lowpass filters are calculated in time multiplex for the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard (see Fig. 2–5). For PAL/NTSC, a wide band chroma filter can be selected. This filter is intended for high bandwidth chroma signals, e.g. a nonstandard wide Fig. 2–3: Frequency response of chroma IF-com- bandwidth S-VHS signal. pensation

Notch Luma / CVBS Luma Filter

Chroma 1 H Delay CrossSwitch MUX

ACC IF Compensation Lowpass Filter MIXER Phase/Freq MUX DC-Reject Demodulator Chroma

ColorPLL/ColorACC

Fig. 2–4: Color decoder

8 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

The ACC has a control range of +30 ... –6 dB.

For SECAM decoding, the frequency of the burst is measured. Thus, the current chroma carrier frequency can be identified and is used to control the SECAM processing. The burst measurements also control the color killer operation; they can be used for automatic standard detection as well.

2.3.6. Color Killer Operation PAL/NTSC The color killer uses the burst-phase/burst-frequency measurement to identify a PAL/NTSC or SECAM color signal. For PAL/NTSC, the color is switched off (killed) as long as the color subcarrier PLL is not locked. For SECAM, the killer is controlled by the toggle of the burst frequency. The burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. Thus, color will be killed for very noisy signals. The color amplitude killer has a programmable hysteresis. SECAM

Fig. 2–5: Frequency response of chroma filters 2.3.7. PAL Compensation/1-H Comb Filter

The color decoder uses one fully integrated delay line. 2.3.4. Frequency Demodulator Only active video is stored.

The frequency demodulator for demodulating the SE- The delay line application depends on the color stan- CAM signal is implemented as a CORDIC-structure. It dard: calculates the phase and magnitude of the quadrature – NTSC: 1-H comb filter or color compensation components by coordinate rotation. – PAL: color compensation The phase output of the CORDIC processor is differ- – SECAM: crossover-switch entiated to obtain the demodulated frequency. After the deemphasis filter, the Dr and Db signals are scaled In the NTSC compensated mode, Fig. 2–6 c), the color to standard CrCb amplitudes and fed to the cross- signal is averaged for two adjacent lines. Thus, over-switch. cross-color distortion and chroma noise is reduced. In the NTSC 1-H comb filter mode, Fig. 2–6 d), the delay line is in the composite signal path, thus allowing 2.3.5. Burst Detection reduction of cross-color components, as well as cross-luminance. The loss of vertical resolution in the In the PAL/NTSC-system the burst is the reference for luminance channel is compensated by adding the ver- the color signal. The phase and magnitude outputs of tical detail signal with removed color information. If the the CORDIC are gated with the color key and used for 4H adaptive comb filter is used, the 1-H NTSC comb controlling the phase-lock-loop (APC) of the demodula- filter has to be deselected. tor and the automatic color control (ACC) in PAL/NTSC.

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2.3.8. Luminance Notch Filter

CVBS Luma Notch Y Y If a composite video signal is applied, the color infor- 8 filter 8 mation is suppressed by a programmable notch filter. Chroma C C chroma Chroma C C Process. r b Process. r b 8 The position of the filter center frequency depends on the subcarrier frequency for PAL/NTSC. For SECAM, a) conventional b) S-VHS the notch is directly controlled by the chroma carrier frequency. This considerably reduces the cross-lumi- CVBS nance. The frequency responses for all three systems Notch Y 8 filter are shown in Fig. 2–9.

dB Chroma 1 H C C 10 Process. Delay r b

0 c) compensated

–10 Notch Y CVBS filter 1 H –20 Delay 8 –30

–40 C C MHz Chroma r b 02 4 68 10 Process. PAL/NTSC notch filter d) comb filter

dB Fig. 2–6: NTSC color decoding options 10

–10

–20

–30 CVBS Notch Y 8 filter –40 MHz 02 4 68 10

Chroma 1 H C C SECAM notch filter Process. Delay r b Fig. 2–9: Frequency responses of the luma a) conventional notch filter for PAL, NTSC, SECAM

Luma Y 8 2.3.9. Skew Filtering

Chroma Chroma 1 H C C Process. Delay r b The system clock is free-running and not locked to the 8 TV line frequency. Therefore, the ADC sampling pat- b) S-VHS tern is not orthogonal. The decoded YCrCb signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. Fig. 2–7: PAL color decoding options The skew filters are controlled by a skew parameter and allow the application of a group delay to the input signals without introducing waveform or frequency CVBS Notch Y response distortion. 8 filter The amount of phase shift of this filter is controlled by MUX Chroma 1 H C C the horizontal PLL1. The accuracy of the filters is 1/32 Process. Delay r b clocks for luminance and 1/4 clocks for chroma. Thus the 4:2:2 YCrCb data is in an orthogonal pixel format Fig. 2–8: SECAM color decoding even in the case of nonstandard input signals such as VCR.

10 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

2.4. Horizontal Scaler to the previous measurement and the minima are stored in the I2C-register BLKLIN. To adjust the picture The 4:2:2 YCrCb signal from the color decoder is pro- amplitude, the external controller reads this register, cessed by the horizontal scaler. The scaler block calculates the vertical scaling coefficient and transfers allows a linear or nonlinear horizontal scaling of the the new settings, e.g. vertical sawtooth parameters, input video signal in the range of 0.25 to 4. Nonlinear horizontal scaling coefficient etc., to the VPC. scaling, also called “panorama vision”, provides a geometrical distortion of the input picture. It is used to Letterbox signals containing logos on the left or right fit a picture with 4:3 format on a 16:9 screen by stretch- side of the black areas are processed as black lines, ing the picture geometry at the borders. Also, the while subtitles, inserted in the black areas, are pro- inverse effect can be produced by the scaler. A sum- cessed as non-black lines. Therefore the subtitles are mary of scaler modes is given in Table 2–1. visible on the screen. To suppress the subtitles, the vertical zoom coefficient is calculated by selecting the The scaler contains a programmable decimation filter, larger number of black lines only. Dark video scenes a 1-line FIFO memory, and a programmable interpola- with a low contrast level compared to the letterbox tion filter. The scaler input filter is also used for pixel area are indicated by the BLKPIC bit. skew correction, see 2.3.9. The decimator/interpolator structure allows optimal use of the FIFO memory. The controlling of the scaler is done by the internal Fast 2.6. Control and Data Output Signals Processor. The VPC 32xx supports two output modes: In Table 2–1: Scaler modes DIGIT3000 mode, the output interfaces run at the main system clock, in line-locked mode, the VPC generates Mode Scale Description an asynchronous line-locked clock that is used for the Factor output interfaces.

Compression 0.75 4:3 source displayed on 4:3 → 16:9 linear a 16:9 tube, 2.6.1. Line-Locked Clock Generation with side panels An on-chip rate multiplier will be used to synthesize Panorama non- 4:3 source displayed on any desired output clock frequency of 13.5/16/18 MHz. 4:3 →16:9 linear a 16:9 tube, A double clock frequency output is available to support compr Borders distorted 100 Hz systems. The synthesizer is controlled by the embedded RISC controller, which also controls all Zoom 1.33 Letterbox source (PAL+) front-end loops (clamp, AGC, PLL1, etc.). This allows → 4:3 4:3 linear displayed on a 4:3 tube, the generation of a line-locked output clock regardless vertical overscan with of the system clock (20.25 MHz) which is used for cropping of side panels comb filter operation and color decoding. The control of scaling and output clock frequency is kept indepen- Panorama non- Letterbox source (PAL+) dent to allow aspect ratio conversion combined with 4:3 → 4:3 linear displayed on a 4:3 tube, sample rate conversion. The line-locked clock circuity zoom vertical overscan, bor- generates control signals, e.g. horizontal/vertical sync, ders distorted, no crop- active video output, it is also the interface from the ping internal (20.25 MHz) clock to the external line-locked 20.25 → 0.66 sample rate conversion clock system. 13.5 MHz to line-locked clock If no line-locked clock is required, i.e. in the DIGIT3000 mode, the system runs at the 20.25 MHz main clock. The horizontal timing reference in this mode is pro- 2.5. Blackline Detector vided by the front-sync signal. In this case, the line-locked clock block and all interfaces run from the In case of a letterbox format input video, e.g. Cinema- 20.25 MHz main clock. The synchronization signals scope, PAL+ etc., black areas at the upper and lower from the line-locked clock block are still available, but part of the picture are visible. It is suitable to remove or for every line the internal counters are reset with the reduce these areas by a vertical zoom and/or shift main-sync signal. A double clock signal is not available operation. in DIGIT3000 mode. The VPC 32xx supports this feature by a letterbox detector. The circuitry detects black video lines by measuring the signal amplitude during active video. For every field the number of black lines at the upper and lower part of the picture are measured, compared

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2.6.2. Sync Signals 2.6.5. Line-Locked 4:1:1 Output Format

The front end will provide a number of sync/control sig- The orthogonal 4:1:1 output format is compatible to the nals which are output with the output clock. The sync industry standard. The YCrCb samples are skew-cor- signals are generated in the line-locked clock block. rected and interpolated to an orthogonal sampling raster (see Table 2–3). – Href : horizontal sync – AVO: active video out (programmable) Table 2–3: 4:1:1 Orthogonal output format – HC: horizontal clamp (programmable) Luma Y1 Y2 Y3 Y4 – Vref : vertical sync Chroma

– INTLC: interlace 7 5 3 1 C3, C7 Cb1 Cb1 Cb1 Cb1 – HELPER: PAL+ helper lines 6 4 2 0 C2, C6 Cb1 Cb1 Cb1 Cb1 7 5 3 1 All horizontal signals are not qualified with field infor- C1, C5 Cr1 Cr1 Cr1 Cr1 mation, i.e. the signals are present on all lines. The 6 4 2 0 horizontal timing is shown in Fig. 2–10. Details of the C0, C4 Cr1 Cr1 Cr1 Cr1 horizontal/vertical timing are given in Fig. 2–14. Y note: C*x (x = pixel number and y = bit number)

2.6.3. DIGIT3000 Output Format 2.6.6. Output Code Levels The picture bus format between all DIGIT3000 ICs is 4:2:2 YCrCb with 20.25 MHz samples/s. Only active Output Code Levels correspond to ITU-R code levels: video is transferred, synchronized by the system main Y = 16...240 sync signal (MSY) which indicates the start of valid Black Level = 16 ± data for each scan line and which initializes the color CrCb = 128 112 multiplex. The video data is orthogonally sampled An overview over the output code levels is given in YCrCb, the output format is given in Table 2–2. The Table 2–4. number of active samples per line is 1080 for all standards (525 and 625). 2.6.7. Output Signal Levels The output can be switched to 4:1:1 mode with the output format according to Table 2–3. All data and sync lines operate at TTL compliant levels. With an optional external 3.3 V supply for the out- Via the MSY line, serial data is transferred which con- put pins, reduced voltage swings can be obtained. tains information about the main picture such as current line number, odd/even field etc.). It is generated by the deflection circuitry and represents the orthogo- 2.6.8. Test Pattern Generator nal timebase for the entire system. The YCrCb outputs can be switched to a test mode where YCrCb data are generated digitally in the Table 2–2: Orthogonal 4:2:2 output format VPC32xx. Test patterns include luma/chroma ramps, flat field, and a pseudo color bar.

Luma Y1 Y2 Y3 Y4

Chroma Cb1 Cr1 Cb3 Cr3

2.6.4. Line-Locked 4:2:2 Output Format

In line-locked mode, the VPC 32xx will produce the industry standard pixel stream for YCrCb data. The difference to DIGIT3000 native mode is only the number of active samples, which of course, depends on the chosen scaling factor. Thus, Table 2–2 is valid for both 4:2:2 modes.

12 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

2.6.9. Priority Bus Codec – delay compensation to composite video path – helper window (line# identification) The VPC data outputs are controlled by the priority bus interface. This interface allows a maximum of 8 signal – output at the luma output port sources to be connected on a common video YCrCb bus. The 3-bit priority bus signal controls the arbitra- Helper signals are processed like the main video luma tion and source switching of the video sources on a signals, i.e. they are subject to scaling, sample rate pixel-by-pixel basis. The priority bus makes features conversion and orthogonalization if activated. The possible, such as adaptive comb filter processing is switched off for the helper lines. – real time digital PIP insertion – Teletext/Mixed-mode picture insertion. It is expected that further helper processing (e.g. nonlinear expansion, matched filter) is performed outside In general, each source has its own YCrCb bus the VPC. request. This bus request may either be software or hardware controlled, i.e. a fast blank signal. Data colli- sion on the bus is avoided by a bus arbiter that pro- 2.7.1. Output Signals for PAL+/Color+ Support vides the individual bus grant in accordance to the user defined source priority. For a PAL+/Color+ signal, the 625 line PAL image contains a 16/9 core picture of 431 lines which is in stan- Each master sends a bus request using his individual dard PAL format. The upper and lower 72 lines contain priority ID onto the bus and immediately reads back the PAL+ helper signal, and line 23 contains signalling the bus state. Only in case of a positive arbitration, e.g. information for the PAL+ transmission. the master reads back his own priority ID, the bus is granted to the master. For PAL+ mode, the Y signal of the core picture, which is during lines 60–274 and 372–586, is replaced by the orthogonal composite video input signal. In order to fit 2.7. PAL+ Support the signal to the 8-bit port width, the ADC signal amplitudes are used. During the helper window, which is in For PAL+, the VPC 321x provides basic helper prepro- lines 24–59, 275–310, 336–371, 587–622, the demodu- cessing: lated helper is signal processed by the horizontal scaler and the output circuitry. It is available at the luma output – A/D conversion (shared with the existing ADCs) port. The processing in the helper reference lines 23 – mixing with subcarrier frequency and 623 is different for the wide screen signaling part and the black reference and helper burst signals. The – lowpass filter 2.5 MHz code levels are given in detail in Table 2–4, the output – gain control by chroma ACC signal for the helper reference line is shown in Fig. 2–11.

Table 2–4: Output signal code levels for PAL/PAL+ signal

Output Signal Luma Outputs Y[7:0] Chroma Outputs C[7:0]

Output Format Black/Zero Amplitude Output Format Amplitude Level

Standard YCrCb binary 16 224 offset binary 128±112 (100% Chroma signed ±112

CVBS, CrCb binary 64 149 (luma) offset binary 128±112

signed ±112

Demodulated signed 0 ±109 –– Helper

Helper WSS binary 68 149 (WSS:106) ––

Helper black level, offset binary 128 19 (128–109) –– Ref. Burst

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horizontal pixel counter 0 line length (programmable)

horizontal sync (HS) 131

horizontal clamp (HC) start / stop programmable

newline (internal signal) start of video output (programmable)

active video out (AVO) start / stop programmable

vertical sync (VS), field 1 field 1 16

vertical sync (VS), field 2 field 2 line length/2

Fig. 2–10: Horizontal timing for line-locked mode

255 255 black level WSS Signal Helper Burst 174 (demodulated)

128

19 0 binary format signed format

Fig. 2–11: PAL+ helper reference line output signal

14 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

2.8. Video Sync Processing For vertical sync separation, the sliced video signal is integrated. The FP uses the integrator value to derive vertical sync and field information. Fig. 2–12 shows a block diagram of the front-end sync processing. To extract the sync information from the The information extracted by the video sync process- video signal, a linear phase lowpass filter eliminates all ing is multiplexed onto the hardware front sync signal noise and video contents above 1 MHz. The sync is (FSY) and is distributed to the rest of the video pro- separated by a slicer; the sync phase is measured. A cessing system. The format of the front sync signal is variable window can be selected to improve the noise given in Fig. 2–13. immunity of the slicer. The phase comparator measures the falling edge of sync, as well as the integrated The data for the vertical deflection, the sawtooth, and sync pulse. the East-West correction signal is calculated by the VPC 32xx. The data is buffered in a FIFO and trans- The sync phase error is filtered by a phase-locked loop ferred to the back-end IC DDP 3300A by a single wire that is computed by the FP. All timing in the front-end is interface. derived from a counter that is part of this PLL, and it thus counts synchronously to the video signal. Frequency and phase characteristics of the analog video signal are derived from PLL1. The results are fed A separate hardware block measures the signal back to the scaler unit for data interpolation and orthogonal- porch and also allows gathering the maximum/mini- ization and to the clock synthesizer for line-locked mum of the video signal. This information is processed clock generation. Horizontal and vertical syncs are by the FP and used for gain control and clamping. latched with the line-locked clock.

PLL1

lowpass phase 1 MHz horizontal front front sync comparator skew & sync & counter sync syncslicer separation lowpass generator vblank field

video input clock frontend clock timing synthesizer syncs H/V syncs clamp & signal meas. clamping, colorkey, FIFO_write

vertical Sawtooth vertical vertical sync Parabola FIFO serial Calculation E/W separation data sawtooth

Fig. 2–12: Sync separation block diagram

skew skew not V: vertical sync F1 used FV LSB MSB 0 = off input Parity 1 = on analog F0 reserved video (not in scale) F: field # 0 = field 1 1 = field 2 FSY F0 F1

Fig. 2–13: Front sync format

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field 1

CCIR 623624 625 1234 5 678 23 24

Front-Sync (FSY)

Vertical Sync (VS) Interlace (INTLC)

> 1clk field 2

CCIR 310 311312 313 314 315 316 317 318319 320 335 336

Vertical Sync (VS)

Interlace (INTLC) >1 clk

Active Video Output (AVO)

helper ref line 23, 623 (internal signal) signal matches output video

The following signals are identical for field1 / field2

helper lines 23–59, 275–310, 336–371, 587–623, signal matches output video

Fig. 2–14: Vertical timing of VPC 32x5 shown in reference to input video. Video output signals are delayed by 3-h for comb filter version (VPC 32x5).

16 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

3. Serial Interface 3.2. Control and Status Registers

3.1. I2C-Bus Interface Table 3–1 gives definitions of the VPC control and status registers. The number of bits indicated for each Communication between the VPC and the external register in the table is the number of bits implemented controller is done via I2C-bus. The VPC has an in hardware, i.e. a 9-bit register must always be I2C-bus slave interface and uses I2C clock synchroni- accessed using two data bytes but the 7 MSB will be zation to slow down the interface if required. The ‘don’t care’ on write operations and ‘0’ on read opera- I2C-bus interface uses one level of subaddress: one tions. Write registers that can be read back are indi- I2C-bus address is used to address the IC and a sub- cated in Table 3–1. address selects one of the internal registers. The I2C-bus chip address is given below: Functions implemented by software in the on-chip control microprocessor (FP) are explained in Table 3–2. A6 A5 A4 A3 A2 A1 A0 R/W A hardware reset initializes all control registers to 0. 10001111/0 The automatic chip initialization loads a selected set of registers with the default values given in Table 3–1.

The registers of the VPC have 8 or 16-bit data size; The register modes given in Table 3–1 are 16-bit registers are accessed by reading/writing two 8-bit data words. – w: write only register – w/r: write/read data register Figure 3–1 shows I2C-bus protocols for read and write operations of the interface; the read operation requires – r: read data from VPC an extra start condition and repetition of the chip – v: register is latched with vertical sync address with read command set. The mnemonics used in the Intermetall VPC demo software are given in the last column.

2 S 1000 111 WAck 0111 1100 Ack 1 or 2 byte Data P I C write access subaddress 7c

I2C read access S 1000 111 WAck 0111 1100 Ack S 1000 111 RAck high byte Data Ack subaddress 7c low byte Data Nak P

W = 0 SDA 1 R = 1 0 Ack = 0 S P Nak = 1 SCL S = Start P = Stop

Fig. 3–1: I2C-bus protocols

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Table 3–1: Control and status registers

I2C Sub- Number Mode Function Default Name address of bits

FP Interface

h’35 8 r FP status – FPSTA bit [0] write request bit [1] read request bit [2] busy

h’36 16 w bit[8:0] 9-bit FP read address – FPRD bit[11:9] reserved, set to zero

h’37 16 w bit[8:0] 9-bit FP write address – FPWR bit[11:9] reserved, set to zero

h’38 16 w/r bit[11:0] FP data register, reading/writing to this – FPDAT register will autoincrement the FP read/ write address. Only 16 bit of data are transferred per I2C telegram.

Black Line Detector

h’12 16 w/r read only register, do not write to this register! After reading, – BLKLIN LOWLIN and UPLIN are reset to 127 to start a new measurement. bit[6:0] number of lower black lines LOWLIN bit[7] always 0 bit[14:8] number of upper black lines UPLIN bit[15] 0/1 normal/black picture BLKPIC

Pin Circuits

h’1F 16 w/r SYNC pins (HS, HC, AVO, HELP, INTLC, VS): TRPAD bit[2:0] 0..7 output strength for SYNC Pins 0 SNCSTR (7 = tristate, 6 = weak ... 0 = strong) bit[3] 0/1 pushpull/tristate for AVO Pin 0 AVODIS bit[4] 0/1 pushpull/tristate for other SYNC Pins 0 SNCDIS bit[5] 0/1 synchronization/no synchronization with 0 VASYSEL horizontal HS for signals VS and INTLC CLOCK pins (LLC1, LLC2): bit[6] 0/1 pushpull/tristate for LLC1 0 LLC1DIS bit[7] 0/1 pushpull/tristate for LLC2 0 LLC2DIS DATA pins (LB[7:0], CB[7:0]): bit[10:8] 0..7 output strength for DATA pins 0 DATSTR (7 = tristate, 6 = weak ... 0 = strong) bit[11] 0/1 tristate/pushpull for DATA pins 0 DATEN bit[12] 0/1 half-cycle pull-up(DIGIT3000)/pushpull for 0 LCPUDIS LB, CB (LCC) bit[13] reserved (set to 0) bit[14:15] output strength for LLC1: (–2,–1,0,1) 0 LLC1STR

18 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

I2C Sub- Number Mode Function Default Name address of bits

h’20 8 w/r SYNC GENERATOR CONTROL: SYNCMODE bit[1:0] 00 AVO and active Y/C data at same time 0 AVOPRE 01 AVO precedes Y/C data one clock cycle 10 AVO precedes Y/C data two clock cycles 11 AVO precedes Y/C data three clock cycles bit[2] 0/1 positive/negative polarity for HS signal 0 HSINV bit[3] 0/1 positive/negative polarity for HC signal 0 HCINV bit[4] 0/1 positive/negative polarity for AVO signal 0 AVOINV bit[5] 0/1 positive/negative polarity for VS signal 0 VSINV bit[6] 0/1 positive/negative polarity for HELP signal 0 HELPINV bit[7] 0/1 positive/negative polarity for INTLC signal 0 INTLCINV

h’30 8 w/r V-SYNC DELAY CONTROL: VSDEL bit[7:0] VS delay (8 LLC clock cycles per LSB) 0 VSDEL

Priority Bus

h’23 8 w/r priority bus overwrite register bit [7:0] 8 bit mask, bit[x] = 1 : overwrite priority x 0 PRIOVR

h’24 8 w/r priority bus ID register and control PRIOMODE bit [2:0] 0..7 priority ID, 0 highest 0 PID bit [4:3] 0..3 pad driver strength, 0 (strong) to 3 (weak) 0 PRIOSTR bit [5] 0/1 output mode: DIGIT3000/LLC 0 OMODE bit [6] 0/1 source for prio request: AVO/active always 0 PIDSRC bit [7] 0/1 disable/enable priority interface, if disabled 0 PIDE data pins are tristate !

Sync Generator

h’21 16 w/r LINE LENGTH: bit[10:0] LINE LENGTH register 1295 LINLEN In LLC mode, this register defines the cycle of the sync counter which generates the SYNC pulses. In LLC mode, the synccounter counts from 0 to LINE LENGTH, so this register has to be set to “number of pixels per line –1”. In DIGIT3000 mode, LINE LENGTH has to be set to 1295 for correct adjustment of vertical signals. bit[15:11] reserved (set to 0)

h’26 16 w/r HC START: bit[10:0] HC START defines the beginning of the 50 HCSTRT HC signal in respect to the value of the sync counter. bit[15:11] reserved (set to 0)

h’27 16 w/r HC STOP: bit[10:0] HC STOP defines the end of the HC signal 800 HCSTOP in respect to the value of the sync counter. bit[15:11] reserved (set to 0)

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I2C Sub- Number Mode Function Default Name address of bits

h’28 16 w/r AVO START: bit[10:0] AVO START defines the beginning of the 60 AVSTRT AVO signal in respect to the value of the sync counter. bit[11] reserved (set to 0) bit[12] 0/1 vertical window disable/enable VERWIN bit[13] 0/1 vertical window 312/262 lines bit[15:14] –2..1 vertical window interlace offset

h’29 16 w/r AVO STOP: bit[10:0] AVO STOP defines the end of the AVO 0 AVSTOP signal in respect to the value of the sync counter. bit[15:11] reserved for test picture generation (set to 0 in normal operation) bit[11] 0/1 disable/enable test pattern generator 0 COLBAREN bit[13:12] luma output mode: 0 LMODE 00 Y = ramp (240 ... 17) 01 Y = 16 10 Y = 90 11 Y = 240 bit[14] 0/1 chroma output: 422/411 mode 0 M411 bit[15] 0/1 chroma output: pseudo color bar/zero 0 CMODE if LMODE = 0

h’22 16 w/r NEWLINE: bit[10:0] NEWLINE defines the readout start of the 50 NEWLIN next line inrespect to the value of the sync counter. The value of this register must be greater than 31 for correct operation and should be identical to AVOSTART (recommended). In case of 1H-bypass mode for scaler block, NEWLINE has no function. bit[12:11] reserved (set to 0) 0 FLW bit[13] vertical free run mode enabled, the vertical frequency is selected via VERWIN (h’28) bit[15:14] reserved (set to 0)

20 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Table 3–2: Control Registers of the Fast Processor

– default values are initialized at reset – * indicates: register is initialized according to the current standard when SDT register is changed.

FP Sub- Function Default Name address

Standard Selection

h’20 Standard select: SDT bit[2:0] standard 0 0 PAL B,G,H,I (50 Hz) 4.433618 PAL 1 NTSC M (60 Hz) 3.579545 NTSC 2 SECAM (50 Hz) 4.286 SECAM 3 NTSC44 (60 Hz) 4.433618 NTSC44 4 PAL M (60 Hz) 3.575611 PALM 5 PAL N (50 Hz) 3.582056 PALN 6 PAL 60 (60 Hz) 4.433618 PAL60 7 NTSC COMB (60 Hz) 3.579545 NTSCC bit[3] 0/1 MOD standard modifier 0 SDTMOD PAL modified to simple PAL NTSC modified to compensated NTSC SECAM modified to monochrome 625 NTSCC modified to monochrome 525 bit[4] 0/1 PAL+ mode off/on 0 PALPLUS bit[5] 0/1 4-H COMB mode 0 COMB bit[6] 0/1 S-VHS mode: 0 SVHS The S-VHS/COMB bits allow the following modes: 00 composite input signal 01 comb filter active 10 S-VHS input signal 11 CVBS mode (composite input signal, no luma notch) Option bits allow to suppress parts of the initialization; this can be used for color standard search: bit[7] no hpll setup 0 SDTOPT bit[8] no vertical setup bit[9] no acc setup bit[10] 4-H comb filter setup only bit[11] status bit, normally write 0. After the FP has switched to a new standard, this bit is set to 1 to indicate operation complete. Standard is automatically initialized when the insel register is written.

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FP Sub- Function Default Name address

h’21 Input select: writing to this register will also initialize the standard INSEL bit[1:0] luma selector 0 VIS 00 VIN3 01 VIN2 10 VIN1 11 VIN4 bit[2] chroma selector 1 CIS 0/1 VIN1/CIN bit[4:3] IF compensation 0 IFC 00 off 01 6 dB/Okt 10 12 dB/Okt 11 10 dB/MHz only for SECAM bit[6:5] chroma bandwidth selector 2 CBW 00 narrow 01 normal 10 broad 11 wide bit[7] 0/1 adaptive/fixed SECAM notch filter 0 FNTCH bit[8] 0/1 enable luma lowpass filter 0 LOWP bit[10:9] hpll speed 3 HPLLMD 00 no change 01 terrestrial 10 vcr 11 mixed bit[11] status bit, write 0, this bit is set to 1 to indicate operation complete.

h’22 picture start position: This register sets the start point of active video 0SFIF and can be used e.g. for panning. The setting is updated when ‘sdt’ register is updated or when the scaler mode register ‘scmode’ is written.

h’23 luma/chroma delay adjust. The setting is updated when ‘sdt’ register 0LDLY is updated. bit[5:0] reserved, set to zero bit[11:6] luma delay in clocks, allowed range is +1 ... –7

h’29 helper delay register (PAL+ mode only) 0 HLP_DLY bit[11:0] delay adjust for helper lines adjustable from –96...96, 1 step corresponds to 1/32 clock

h’2f VGA mode select, pull-in range is limited to 2% VGA_C bit[1:0] 0 31.5 kHz 1 35.2 kHz 0 VGAMODE 2/3 37.9 kHz is set to 0 by FP if VGA = 0 bit[10] 0/1 disable/enable VGA mode bit[11] status bit, write 0, this bit is set to 1 to indicate 0 VGA operation complete.

22 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

FP Sub- Function Default Name address

Comb Filter

h’28 comb filter control register h’e7 COMB_UC bit[1:0] notch filter select 3 NOSEL 00 flat frequency characteristic 01 min. peaked 10 med. peaked 11 max. peaked bit[3:2] diagonal dot reduction 1 DDR 00 min. reduction ... 11 max. reduction bit[4:5] horizontal difference gain 2 HDG 00 min. gain ... 11 max. gain bit[7:6] vertical difference gain 3 VDG 00 max. gain ... 11 min. gain bit[11:8] vertical peaking gain 0 VPK 0 no vertical peaking... 15 max. vertical peaking

h’55 comb filter test register CMB_TST bit[1:0] reserved, set ot 0 bit[2] 0/1 disable/enable vertical peaking DC rejection filter 0 DCR bit[3] 0/1 disable/enable vertical peaking coring 0 COR bit[11:4] reserved, set to 0

Color Processing

h’34 ACC multiplier value for PAL+ Helper Signal 1280 ACCH b[10:0] eeemmmmmmmm m * 2–e

h’36 ACC PAL+ Helper gain adjust, gain is referenced to PAL burst, 787 HLPGAIN allowed values from 256..1023 a value of zero allows manual adjust of Helper amplitude via ACCh

h’39 amplitude killer level (0:killer disabled) 25 KILVL

h’3a amplitude killer hysteresis 5 KILHY

h’16c automatic helper disable for nonstandard signals 0HLPDIS bit[11:0] 0 automatic function disabled bit[1:0] 01 enable bit[11:2] 1..50 number of fields to switch on helper signal

h’dc NTSC tint angle, ±512 = ±π/4 0 TINT

Horizontal PLL

h’aa h-pll gain setting, these registers are used to set the h-pll speed, pll h’ab speed selection is done via the input selection register h’ac

DVCO

h’f8 crystal oscillator center frequency adjust, –2048 ... 2047 –720 DVCO

h’f9 crystal oscillator center frequency adjustment value for line-lock read only ADJUST mode, true adjust value is DVCO – ADJUST. For factory crystal alignment, using standard video signal: disable autolock mode, set DVCO = 0, set lock mode, read crystal offset from ADJUST register and use negative value for initial center frequency adjustment via DVCO.

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FP Sub- Function Default Name address

h’f7 crystal oscillator line-locked mode, lock command/status 0XLCK write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked

h’b5 crystal oscillator line-locked mode, autolock feature. If autolock is 400 AUTOLCK enabled, crystal oscillator locking is started automatically. bit[11:0] threshold, 0:autolock off

FP Status Register

h’12 general purpose control bits bit[2:0] reserved, do not change bit[3] vertical standard force 0 VFRC bit[8:4] reserved, do not change bit[9] disable flywheel interlace 1 DFLW bit[11:10] reserved, do not change to enable vertical free run mode set vfrc to 1 and dflw to 0

h’13 standard recognition status – ASR bit[0] 1 vertical lock bit[1] 1 horizontally locked bit[2] 1 no signal detected bit[3] 1 color amplitude killer active bit[4] 1 disable amplitude killer bit[5] 1 color ident killer active bit[6] 1 disable ident killer bit[7] 1 interlace detected bit[8] 1 no vertical sync detection bit[9] 1 spurious vertical sync detection bit[12:10] reserved

h’14 input noise level, available only for VPC 3215C read only NOISE

h’cb number of lines per field, P/S: 312, N: 262 read only NLPF

h’15 vertical field counter, incremented per field read only VCNT

h’74 measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC) read only SAMPL

h’31 measured burst amplitude read only BAMPL

h’f0 firmware version number read only – bit[7:0] internal revision number bit[11:8] firmware release

h’f1 hardware version number read only – bit[5:0] internal hardware revision number bit[11:6] hardware id, VPC 32x5C = 01

24 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

FP Sub- Function Default Name address

Scaler Control Register

h’40 scaler mode register 0SCMODE bit[1:0] scaler mode PANO 0 linear scaling mode 1 nonlinear scaling mode, ’panorama’ 2 nonlinear scaling mode, ’waterglass’ 3 reserved bit[2] reserved, set to 0 bit[3] color mode select S411 0/1 4:2:2 mode / 4:1:1 mode bit[4] scaler bypass BYE bit[5] reserved, set to 0 bit[6] luma output format YOF 0 ITU-R luma output format (16–240) 1 CVBS output format bit[7] chroma output format COF 0/1 ITU-R (offset binary) / signed bit[10:8] reserved, set to 0 bit[11] 0 scaler update command, when the registers are updated the bit is set to 1

h’41 luma offset register 57 YOFFS bit[6:0] luma offset 0..127 ITU-R output format: 57 CVBS output format: 4 this register is updated when the scaler mode register is written

h’42 active video length for 1H-FIFO 1080 FFLIM bit[11:0] length in pixels D3000 mode (1296/h)1080 LLC mode (864/h)720 this register is updated when the scaler mode register is written

h’43 scaler1 coefficient: This scaler compresses the signal. 1024 SCINC1 For compression by a factor c, the value c*1024 is required. bit[11:0] allowed values from 1024... 4095 This register is updated when the scaler mode register is written.

h’44 scaler2 coefficient: This scaler expands the signal. 1024 SCINC2 For expansion by a factor c, the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 This register is updated when the scaler mode register is written.

h’45 scaler1/2 nonlinear scaling coefficient 0SCINC This register is updated when the scaler mode register is written.

h’47 – scaler1 window controls, see table 0 SCW1_0 – 4 h’4b 5 12-bit registers for control of the nonlinear scaling This register is updated when the scaler mode register is written.

h’4c – scaler2 window controls, see table 0 SCW2_0 – 4 h’50 5 12-bit registers for control of the nonlinear scaling This register is updated when the scaler mode register is written.

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FP Sub- Function Default Name address

LLC Control Register

h’60 horizontal offset 0 LLC_OFFSET bit[11:0] offset between FSY and HS

h’65 vertical freeze start –10 LLC_START freeze llc pll for llc_start < line number < llc_stop bit[11:0] allowed values from –156...+156

h’66 vertical freeze stop 4 LLC_STOP freeze llc pll for llc_start < line number < llc_stop bit[11:0] allowed values from –156...+156

h’69 20 bit llc clock center frequency 42 = h’02A LLC_CLOCKH h’6a 13.5 MHz 174763 = h’02AAAB 2731 = h’AAB LLC_CLOCKL 16 MHz –135927 = h’FDED08 18 MHz 174763 = h’02AAAB

h’61 pll frequency limiter, 8% 54 LLC_DFLIMIT 13.5 MHz 54 16 MHz 48 18 MHz 54

h’6d llc clock generator control word 2053 LLC_CLKC bit[4:0] hardware register shadow llc_clkc = 5→13.5 MHz llc_clkc = 3→16 MHz llc_clkc = 3→18 MHz bit[10:5] reserved bit[11] 0/1 enable/disable llc pll

26 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Table 3–3: Control Registers of the Fast Processor that are used for the control of DDP 3300A

– this function is only available in the 50 Hz version (VPC 320x) – default values are initialized at reset – * indicates: register is initialized according to the current standard when SDT register is changed

FP Sub- Function Default Name address

FP Display Control Register

h’130 White Drive Red (0...1023) 700 WDR 1)

h’131 White Drive Green (0...1023) 700 WDG 1)

h’132 White Drive Blue (0...1023) 700 WDB 1)

h’139 Internal Brightness, Picture (0 ..511), the center value is 256, the range 256 IBR allows for both increase and reduction of brightness.

h’13c Internal Brightness, measurement (0...511), the center value is 256, 256 IBRM the brightness for measurement can be set to measure at higher cutoff current. The measurement brightness is independent of the drive values.

h’13a Analog Brightness for external RGB (0...511), the center value is 256, 256 ABR the range allows for both increase and reduction of brightness.

h’13b Analog Contrast for external RGB (0...511) 350 ACT

1) The white drive values will become active only after writing the blue value WDB, latching of new values is indicated by setting the MSB of WDB.

FP Display Control Register, BCL

h’144 BCL threshold current, 0...2047 (max ADC output ~1152) 1000 BCLTHR

h’142 BCL time constant 0...15 →13 ... 1700 msec 15 BCLTM

h’143 BCL loop gain. 0..15 0 BCLG

h’145 BCL minimum contrast 0 ...1023 307 BCLMIN

h’105 Test register for BCL/EHT comp. function, register value: 0BCLTST 0 normal operation 1 stop ADC offset compensation x>1 use x in place of input from Measurement ADC

FP Display Control Register, Deflection

h’103 interlace offset, –2048 ...2047 0INTLC This value is added to the SAWTOOTH output during one field.

h’102 discharge sample count for deflection retrace, 7DSCC SAWTOOTH DAC output impedance is reduced for DSCC lines after vertical retrace.

h’11f vertical discharge value, –1365 DSCV SAWTOOTH output value during discharge operation, typically same as A0 init value for sawtooth.

h’10b EHT (electronic high tension) compensation coefficient, 0...511 0 EHT

h’10a EHT time constant. 0 ..15 → 3.2 ...410 msec 15 EHTTM

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Control registers, continued

FP Sub- Function Default Name address

FP Display Control Register

FP Display Control Register, Vertical Sawtooth

h’110 DC offset of SAWTOOTH output 0OFS This offset is independent of EHT compensation.

h’11b accu0 init value –1365 A0

h’11c accu1 init value 900 A1

h’11d accu2 init value 0 A2

h’11e accu3 init value 0 A3

FP Display Control Register, East-West Parabola

h’12b accu0 init value –1121 A0

h’12c accu1 init value 219 A1

h’12d accu2 init value 479 A2

h’12e accu3 init value –1416 A3

h’12f accu4 init value 1052 A4

28 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

3.2.1. Calculation of Vertical and East-West 3.2.2. Scaler Adjustment Deflection Coefficients In case of linear scaling, most of the scaler registers In Table 3–4 the formula for the calculation of the need not be set. Only the scaler mode, active video deflection initialization parameters from the polynomi- length, and the fixed scaler increments (scinc1/scinc2) nal coefficients a,b,c,d,e is given for the vertical and must be written. East-West deflection. Let the polynomial be

2 3 4 The adjustment of the scaler for nonlinear scaling P = a + b(x – 0.5) + c(x – 0.5) + d(x – 0.5) + e(x – 0.5) modes should use the parameters given in table 3–5. An example for ‘panorama vision’ mode with 13.5 MHz The initialization values for the accumulators a0..a3 for line-locked clock is depicted in Fig. 3–2. The figure vertical deflection and a0..a4 for East-West deflection shows the scaling of the input signal and the variation are 12-bit values. The coefficients that should be used of the scaling factor during the active video line. The to calculate the initialization values for different field scaling factor starts below 1, i.e. for the borders the frequencies are given below, the values must be video data is expanded by scaler 2. The scaling factor scaled by 128, i.e. the value for a0 of the 50 Hz vertical becomes one and compression scaling is done by deflection is scaler 1. When the picture center is reached, the scaling factor is held constant. At the second border the a0 = (a · 128 – b · 1365.3 + c · 682.7 – d · 682.7) ÷ 128 scaler increment is inverted and the scaling factor changes back symmetrically. The picture indicates the function of the scaler increments and the scaler window parameters. The correct adjustment requires that pixel counts for the respective windows are always in number of output samples of scaler 1 or 2.

Table 3–4: Tables for the Calculation of Initialization values for Vertical Sawtooth and East-West Parabola

Vertical Deflection 50 Hz East-West Deflection 50 Hz

abcd ab c d e

a0 128 –1365.3 +682.7 –682.7 a0 128 –341.3 1365.3 –85.3 341.3

a1 899.6 –904.3 +1363.4 a1 111.9 –899.6 84.8 –454.5

a2 296.4 –898.4 a2 586.8 –111.1 898.3

a3 585.9 a3 72.1 –1171.7 a4 756.5 Vertical Deflection 60 Hz East-West Deflection 60 Hz abcd ab c d e a0 128 –1365.3 +682.7 –682.7 a0 128 –341.3 1365.3 –85.3 341.3 a1 1083.5 –1090.2 +1645.5 a1 134.6 –1083.5 102.2 –548.4 a2 429.9 –1305.8 a2 849.3 –161.2 1305.5 a3 1023.5 a3 125.6 –2046.6

a4 1584.8

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border center border input signal video signal

output signal

scinc compression ratio scinc1 1

scinc2 expansion compression compression expansion (scaler2) (scaler1) (scaler1) (scaler2)

scaler window 01 234 cutpoints

Fig. 3–2: Scaler operation for ‘panorama’ mode at 13.5 MHz

Table 3–5: Set-up values for nonlinear scaler modes

Mode DIGIT3000 (20.25 MHz) LLC (13.5 MHz)

‘waterglass’ ‘panorama’ ‘waterglass’ ‘panorama’ border 35% border 30% border 35% border 30%

scinc1 1643 1427 1024 1024 2464 2125 1024 1024

scinc2 1024 1024 376 611 1024 1024 573 914

scinc 90 56 85 56 202 124 190 126

fflim 945 985 921 983 719 719 681 715

scw1 – 0 110 115 83 94 104 111 29 13

scw1 – 1 156 166 147 153 104 111 115 117

scw1 – 2 317 327 314 339 256 249 226 241

scw1 – 3 363 378 378 398 256 249 312 345

scw1 – 4 473 493 461 492 360 360 341 358

scw2 – 0 110 115 122 118 104 111 38 14

scw2 – 1 156 166 186 177 104 111 124 118

scw2 – 2 384 374 354 363 256 249 236 242

scw2 – 3 430 425 418 422 256 249 322 346

scw2 – 4 540 540 540 540 360 360 360 360

30 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

4. Specifications

4.1. Outline Dimensions 16 x 1.27±0.1 = 20.32 ±0.1 ° 1.1 x 45 0.9 1.27 ±0.1 1.2 x 45° 9 1 61

10 60 0.48

2 1.6 0.1 ±

2 0.1

9 ± 1.27 0.125 0.1 ± ± 0.711 23.4 0.1 ± 24.22

25.125 15 9 16 x 1.27 = 20.32 0.07 ±

26 44 0.22

1.9 27 43 4.05 25.125 ± 0.125 0.1 24.22 ±0.1 4.75±0.15

SPGS7004-3/5E Fig. 4–1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm

4.2. Pin Connections and Short Descriptions

NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram

Pin No. Pin Name Type Connection Short Description PLCC (if not used) 68-pin

1GNDF SUPPLY X Ground, Analog Front-End

2GNDF SUPPLY X Ground, Analog Front-End 3 CLK5 OUT LV CCU 5 MHz Clock Output

4VSTBY SUPPLY X Standby Supply Voltage 5 XTAL2 OUT X Analog Crystal Output

6 XTAL1 IN X Analog Crystal Input

7GNDF SUPPLY X Ground, Analog Front-End

9GNDP SUPPLY X Ground, Output Pad Circuitry 10 INTLC OUT LV Interlace Output

12 VS OUT LV Vertical Sync Pulse

13 FSY OUT LV Front Sync Pulse

14 MSY/HS IN/OUT LV Main Sync/Horizontal Sync Pulse

15 HELPER OUT LV Helper Line Output

Micronas 31 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

Pin No. Pin Name Type Connection Short Description PLCC (if not used) 68-pin

16 HC IN/OUT LV Horizontal Clamp Pulse

17 AVO OUT LV Active Video Output

18 LLC2 OUT LV Double Output Clock

19 LLC1 IN/OUT LV Output Clock

20 Y7 OUT GNDP Picture Bus Luma (MSB)

21 Y6 OUT GNDP Picture Bus Luma

22 Y5 OUT GNDP Picture Bus Luma

23 Y4 OUT GNDP Picture Bus Luma

24 Y3 OUT GNDP Picture Bus Luma

25 Y2 OUT GNDP Picture Bus Luma

26 GNDP X Ground, Output Pad Circuitry

28 Y1 OUT GNDP Picture Bus Luma

29 Y0 OUT GNDP Picture Bus Luma (LSB) 30 CLK20 IN/OUT LV Main Clock Output 20.25 MHz

31 VSUPD SUPPLY X Supply Voltage, Digital Circuitry

34 GNDD SUPPLY X Ground, Digital Circuitry

35 GNDP SUPPLY X Ground, Output Pad Circuitry

36 VSUPP SUPPLY X Supply Voltage, Output Pad Supply

38 C7 OUT GNDP Picture Bus Chroma (MSB)

39 C6 OUT GNDP Picture Bus Chroma

40 C5 OUT GNDP Picture Bus Chroma

41 C4 OUT GNDP Picture Bus Chroma

42 C3 OUT GNDP Picture Bus Chroma

43 C2 OUT GNDP Picture Bus Chroma

46 C1 OUT GNDP Picture Bus Chroma

47 C0 OUT GNDP Picture Bus Chroma (LSB) 48 PR0 IN/OUT LV Picture Bus Priority (LSB)

49 PR1 IN/OUT LV Picture Bus Priority

50 PR2 IN/OUT LV Picture Bus Priority (MSB)

51 GNDP SUPPLY X Ground, Output Pad Circuitry

52 VGAV IN GNDP VGAV Input

32 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

Pin No. Pin Name Type Connection Short Description PLCC (if not used) 68-pin

53 FPDAT IN/OUT LV Front-End/Back-End Data

54 RESQ IN X Reset Input, Active Low

55 SDA IN/OUT X I2C Bus Data

56 SCL IN/OUT X I2C Bus Clock

57 TEST IN GNDD Test Pin, connect to GNDD 58 VIN4 IN VRT Video 4 Analog Input

59 GNDF SUPPLY X Ground, Analog Front-End 60 VIN3 IN VRT Video 3 Analog Input

61 VIN2 IN VRT Video 2 Analog Input

62 VIN1 IN VRT* Video 1 Analog Input

63 CIN IN LV* Chroma/Video 4 Analog Input

64 VOUT OUT LV Analog Video Output

65 ASGF X Analog Shield GNDF

66 VSUPF SUPPLY X Supply Voltage, Analog Front-End 67 ISGND SUPPLY X Signal Ground for Analog Input, connect to GNDF 68 VRT OUTPUT X Reference Voltage Top, Analog

8, 11 NC – LV OR GNDD Not connected 27, 32 33, 37 44, 45

*) chroma selector must be set to 1 (CIN chroma select)

4.3. Pin Descriptions Pins 6 and 5 – XTAL1 Crystal Input and XTAL2 Crystal (pin numbers for PLCC68 package) Output (Fig. 4–8) These pins are connected to an 20.25 MHz crystal Pin 1 – Ground, Analog Front-End GNDF oscillator which is digitally tuned by integrated shunt capacitances. The CLK20 and CLK5 clock signals are Pin 2 – Ground, Analog Front-End GNDF derived from this oscillator. An external clock can be fed into XTAL1. In this case, clock frequency adjust- Pin 3 – CCU 5 MHz Clock Output CLK5 (Fig. 4–11) ment must be switched off. This pin provides a clock frequency for the TV micro- controller, e.g. a CCU 3000 controller. It is also used Pin 7 – Ground, Analog Front-End GNDF by the DDP 3300A display controller as a standby clock. Pin 9 – Ground, Output Pad Circuitry GNDP

Pin 4 – Standby Supply Voltage VSTDBY Pin 10 – Interlace Output, INTLC (Fig. 4–4) In standby mode, only the clock oscillator is active, This pin supplies the interlace information, 0 indicates GNDF should be ground reference. Please activate first field, 1 indicates second field. RESQ before powering-up other supplies

Micronas 33 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

Pin 12 – Vertical Sync Pulse, VS (Fig. 4–4) Pin 51 – Ground, Output Pad Circuitry GNDP This pin supplies the vertical sync signal. Pin 52 – VGAV-Input. (Fig. 4–3) Pin 13 – Front Sync Pulse, FSY (Fig. 4–4) This pin is connected to the vertical sync signal of a VGA This pin supplies the front sync information. signal.

Pin 14 – Main Sync/Horizontal Sync Pulse MSY/HS Pin 53 – Front-End/Back-End Data FPDAT (Fig. 4–6) (Fig. 4–4) This pin interfaces to the DDP 3300A back-end pro- This pin supplies the horizontal sync pulse information cessor. The information for the deflection drives and in line-locked mode. In DIGIT3000 mode, this pin is the for the white drive control, i.e. the beam current limiter, main sync input. is transmitted by this pin.

Pin 15 – Helper Line Output, Helper (Fig. 4–4) Pin 54 – Reset Input RESQ (Fig. 4–3) This signal indicates a helper line in PAL+ mode. A low level on this pin resets the VPC 32xx.

Pin 16 – Horizontal Clamp Pulse, HC (Fig. 4–4) Pin 55 – I2C Bus Data SDA (Fig. 4–13) This signal can be used to clamp an external video sig- This pin connects to the I2C bus data line. nal, that is synchronous to the input signal. The timing is programmable. Pin 56 – I2C Bus Clock SCL (Fig. 4–3) This pin connects to the I2C bus clock line. Pin 17 – Active Video Output, AVO (Fig. 4–4) This pin indicates the active video output data. The Pin 57 – Test Input TEST (Fig. 4–3) signal is clocked with the LLC1 clock. This pin enables factory test modes. For normal operation, it must be connected to ground. Pin 18 – Double Output Clock, LLC2 (Fig. 4–6) Pin 59 – Ground, Analog Front-End GNDF Pin 19 – Output Clock, LLC1 (Fig. 4–6) This is the clock reference for the luma, chroma, and Pins 62,61,60,58 – Video Input 1–4 (Fig. 4–12) status outputs. These are the analog video inputs. A CVBS or S-VHS luma signal is converted using the luma (Video 1) AD Pin 26 – Ground, Output Pad Circuitry GNDP converter. The VIN1 input can also be switched to the chroma (Video 2) ADC. The input signal must be Pins 20 to 25,28,29 – Luma Outputs Y0 – Y7 (Fig. 4–4) AC-coupled. These output pins carry the digital luminance data. The data are clocked with the LLC1 clock. Pin 63 – Chroma Input CIN (Fig. 4–10) This pin is connected to the S-VHS chroma signal. A Pin 30 – Main Clock Output CLK20 (Fig. 4–5) resistive divider is used to bias the input signal to the This is the 20.25 MHz main clock output. middle of the converter input range. CIN can only be connected to the chroma (Video 2) A/D converter. The Pin 31 – Supply Voltage, Digital Circuitry VSUPD signal must be AC-coupled.

Pin 34 – Ground, Digital Circuitry GNDD Pin 64 – Analog Video Output, VOUT (Fig. 4–7) The analog video signal that is selected for the main Pin 35 – Ground, Output Pad Circuitry GNDP (luma, CVBS) ADC is output at this pin. An emitter follower is required at this pin. Pin 36 – Supply Voltage, Output Pad Supply VSUPP Pin 65 – Ground, Analog Shield Front-End GNDF Pins 38 to 43,46,47 – Chroma Outputs C0–C7 (Fig. 4–4) These outputs carry the digital CrCb chrominance data. Pin 66 – Supply Voltage, Analog Front-End VSUPF The data are clocked with the LL1 clock. The data are (Fig. 4–9) sampled at half the clock rate and multiplexed. The CrCb multiplex is reset for each TV line. Pin 67 – Signal GND for Analog Input ISGND (Fig. 4– 11) This is the high quality ground reference for the Pins 48 to 50 – Picture Bus Priority PR0–PR2 (Fig. 4–6) video input signals. The Picture Bus Priority lines carry the digital priority selection signals. The priority interface allows digital Pin 68 – Reference Voltage Top VRT (Fig. 4–9) switching of up to 8 sources to the back-end processor. Via this pin, the reference voltage for the A/D converters Switching for different sources is prioritized and can be is decoupled. The pin is connected with 10 µF/47 nF to on a per pixel basis. the Signal Ground Pin.

34 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

4.4. Pin Configuration

GNDF

GNDF VRT CLK5 ISGND VSTBY VSUPF XTAL2 ASGF XTAL1 VOUT GNDF CIN NC VIN1 GNDP VIN2

9 8 7 6 5 4 3 2 1 6867666564636261 INTLC 10 60 VIN3 NC 11 59 GNDF VS 12 58 VIN4 FSY 13 57 TEST MSY/HS 14 56 SCL HELPER 15 55 SDA HC 16 54 RESQ AVO 17 53 FPDAT LLC2 18 VPC 32x5C 52 VGAV LLC1 19 51 GNDP Y7 20 50 PR2 Y6 21 49 PR1 Y5 22 48 PR0 Y4 23 47 C0 Y3 24 46 C1 Y2 25 45 NC GNDP 26 44 NC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

NC C2 Y1 C3 Y0 C4 CLK20 C5 VSUPD C6 NC C7 NC NC GNDD VSUPP

GNDP

Fig. 4–2: 68-pin PLCC package

Micronas 35 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

4.5. Pin Circuits VSTBY VSUPD P P 0.5M

f ECLK N N GNDF GNDD Fig. 4–8: Input/Output Pins XTAL1, XTAL2 Fig. 4–3: Input pins RESQ, TEST, VGAV

VSUPF – + P V SUPD V SUPP P P VRT ADC Reference Vref N ISGND N Fig. 4–9: Pins VRT, ISGND GNDP

Fig. 4–4: Output pins C0–C7, Y0–Y7, FSY, V HC, AVO, HELPER, VS, INTLC, HS, LLC1, LLC2 SUPF

To ADC VSUPD P P GNDF Fig. 4–10: Chroma input CIN N N

GNDD VSTBY P Fig. 4–5: Output pin CLK20 N

GNDF VSUPD P Fig. 4–11: Output pin CLK5

VSUPF N N

GNDD To ADC Fig. 4–6: Input/Output pins PR0–PR2, FPDAT

GNDF VSUPF Vin’s – Fig. 4–12: Input pins VIN1–VIN4 + P VOUT

VREF N

GNDF GNDD Fig. 4–7: Output pin VOUT Fig. 4–13: Pins SDA, SCL

36 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

4.6. Electrical Characteristics

4.6.1. Absolute Maximum Ratings

Symbol Parameter Pin No. Min. Max. Unit ° TA Ambient Operating Temperature – 065C ° TS Storage Temperature ––40 125 C

VSUP Supply Voltage, all Supply Inputs ––0.3 6 V

VI Input Voltage, all Inputs ––0.3 VSUP+0.3 V

VO Output Voltage, all Outputs ––0.3 VSUP+0.3 V

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

4.6.2. Recommended Operating Conditions

Symbol Parameter Pin Name Min. Typ. Max. Unit ° TA Ambient Operating Temperature – 0 – 65 C

VSUP Supply Voltages, all Supply Pins – 4.75 5.0 5.25 V

VSUPP Supply Volt., Output Pad Supply VSUPP 3.15 – 5.25 V

fXTAL Clock Frequency XTAL1/2 – 20.25 – MHz

Micronas 37 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

4.6.3. Recommended Crystal Characteristics

Symbol Parameter Min. Typ. Max. Unit ° TA Operating Ambient Temperature 0 – 65 C

fP Parallel Resonance Frequency – 20.250000 – MHz with Load Capacitance CL = 13 pF ∆ ± fP/fP Accuracy of Adjustment –– 20 ppm ∆ ± fP/fP Frequency Temperature Drift –– 30 ppm Ω RR Series Resistance ––25

C0 Shunt Capacitance 3 – 7pF

C1 Motional Capacitance 20 – 30 fF Load Capacitance Recommendation

1) CLext External Load Capacitance from – 3.3 – pF pins to Ground (pin names: Xtal1 Xtal2)

DCO Characteristics 2,3)

CICLoadmin Effective Load Capacitance @ min. 34.35.5pF DCO–Position, Code 0, package: 68PLCC

CICLoadrng Effective Load Capacitance Range, 11 12.7 15 pF DCO Codes from 0..255

1) Remarks on defining the External Load Capacitance: External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance of the PCBs to the required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size should be determined in the application. The suggested value is a figure based on experience with various PCB layouts. Tuning condition: Code DVCO Register=–720 2) Remarks on Pulling Range of DCO:

The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard). The resulting frequency fL with an effective load capacitance of CLeff = CICLoad + CLoadBoard is:

1 + 0.5 * [ C1 / (C0 + CL) ] fL = fP * ______1 + 0.5 * [ C1 / (C0 + CLeff) ]

3) Remarks on DCO codes The DCO hardware register has 8 bits, the fp control register uses a range of –2048...2047

38 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

4.6.4. Characteristics

° at TA = 0 to 65 C, VSUPD/F = 4.75 to 5.25 V, VSUPP = 3.15 to 3.5V f = 20.25 MHz for min./max. values ° at TC = 60 C, VSUPD/F = 5 V, Vsupp = 3.15V f = 20.25 MHz for typical values

Symbol Parameter Pin Name Min. Typ. Max. Unit

PTOT Total Power Dissipation ––1.15 1.5 W

IVSUPA Current Consumption VSUPF – 40 – mA

IVSUPD Current Consumption VSUPD – 160 – mA

IVSUPP Current Consumption VSUPP – 40 – mA

IVSTDBY Current Consumption VSTDBY – 1 – mA IL Input / Output Leakage Current All I/O Pins –1 – 1 µA

4.6.4.1. Characteristics, 5 MHz Clock Output

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VOL Output Low Voltage CLK5 ––0.4 V IOL = 0.4 mA

VOH Output High Voltage 4.0 – V– V –IOL = 0.9 mA STDBY

tOT Output Transition Time – 50 – ns CLOAD = 30 pF

4.6.4.2. Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1)

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VDCAV DC Average CLK20 VSUP/2 VSUP/2 VSUP/2 VCLOAD = 30 pF – 0.3 + 0.3

VPP VOUT Peak to Peak 1.3 1.6 – VCLOAD = 30 pF

tOT Output Transition Time ––18 ns CLOAD = 30 pF

VIT Input Trigger Level 2.1 2.5 2.9 V only for test purposes

VI Clock Input Voltage XTAL1 1.3 ––VPP capacitive coupling used, XTAL2 open

4.6.4.3. Characteristics, Reset Input, Test Input

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VIL Input Low Voltage RESQ ––1.5 V TEST VIH Input High Voltage 3.0 ––V

Micronas 39 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

4.6.4.4. Characteristics, Priority, FPDAT Input/Output

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VOL Output Low Voltage PR[2:0] ––0.5 V IOL = 14.4 mA, strength 0 FPDAT IOL = 10.8 mA, strength 1 IOL = 7.2 mA, strength 2 IOL = 3.6 mA, strength 3 note: FPDAT strength = 2

µ VOH Output High Voltage 1.8 2.0 2.5 V –IOL = 10 A CLOAD = 70 pF

tOH Output Hold Time 6 ––ns

tODL Output Delay Time ––35 ns CLOAD = 70 pF IL = 14.4 mA strength = 3

IPL Output Pull-up Current PR[2:0] 1.2 1.5 1.5 mA VOL = 0 V FPDAT VIL Input Low Voltage ––0.8 V

VIH Input High Voltage 1.5 ––V

tIS Input Setup Time 7 ––ns

tIH Input Hold Time 5 ––ns

20.25 MHz Clock

tIS tIH VIH Priority Bus Input VIL

tOH

tOH VOHTRI Priority Bus Output VOL tODL

Fig. 4–14: Priority, FPDAT input/output

4.6.4.5. Characteristics, VGAV Input

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VIL Input Low Voltage VGAV ––0.8 V

VIH Input High Voltage 2.0 ––V

40 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

4.6.4.6. Characteristics, I2C Bus Interface

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VIL Input Low Voltage SDA, SCL ––1.5 V

VIH Input High Voltage 3.0 ––V

VOL Output Low Voltage ––0.4 V Il = 3 mA 0.6 V Il = 6 mA

VIH Input Capacitance ––5pF

tF Signal Fall Time ––300 ns CL = 400 pF

tR Signal Rise Time ––300 ns CL = 400 pF

fSCL Clock Frequency SCL 0 – 400 kHz µ tLOW Low Period of SCL 1.3 –– s µ tHIGH High Period of SCL 0.6 –– s

tSU Data Data Set Up Time to SCL high SDA 100 ––ns µ tHD Data DATA Hold Time to SCL low 0 – 0.9 s

4.6.4.7. Characteristics, Analog Video Inputs

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VVIN Analog Input Voltage VIN1, VIN2 0 – 3.5 V VIN3, VIN4 CIN

CCP Input Coupling Capacitor VIN1, VIN2 – 680 – nF Video Inputs VIN3, VIN4

CCP Input Coupling Capacitor CIN – 1 – nF Chroma Input

4.6.4.8. Characteristics, Analog Front-End and ADCs

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

µ Ω VVRT Reference Voltage Top VRT 2.5 2.6 2.8 V 10 F/10 nF, 1 G Probe

Luma – Path

Ω RVIN Input Resistance VIN1 1 ––M Code Clamp–DAC=0 VIN2 CVIN Input Capacitance VIN3 – 5 – pF VIN4

VVIN Full Scale Input Voltage VIN1 1.8 2.0 2.2 VPP min. AGC Gain VIN2 VVIN Full Scale Input VoltageVIN3 0.5 0.6 0.7 VPP max. AGC Gain VIN4 AGC AGC step width – 0.166 – dB 6-Bit Resolution= 64 Steps fsig=1MHz, ± DNLAGC AGC Differential Non-Linearity –– 0.5 LSB – 2 dBr of max. AGC–Gain

Micronas 41 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VVINCL Input Clamping Level, CVBS VIN1 – 1.0 – V Binary Level = 64 LSB VIN2 min. AGC Gain VIN3 QCL Clamping DAC Resolution VIN4 –16 15 steps 5 Bit – I–DAC, bipolar VVIN=1.5 V µ ICL–LSB Input Clamping Current per step 0.7 1.0 1.3 A ± DNLICL Clamping DAC Differential Non- –– 0.5 LSB Linearity

Chroma – Path

Ω RCIN Input Resistance CIN 1.4 2.0 2.6 k SVHS Chroma VIN1

VCIN Full Scale Input Voltage, 1.08 1.2 1.32 VPP Chroma

VCINDC Input Bias Level, – 1.5 – V SVHS Chroma

Binary Code for Open – 128 –– Chroma Input

Dynamic Characteristics for all Video-Paths (Luma + Chroma)

BW Bandwith VIN1 810– MHz –2 dBr input signal level VIN2 XTALK Crosstalk, any Two Video Inputs VIN3 ––56 – dB 1 MHz, –2 dBr signal level VIN4 THD Total Harmonic Distortion – 50 – dB 1 MHz, 5 harmonics, –2 dBr signal level

SINAD Signal to Noise and Distortion – 45 – dB 1 MHz, all outputs, Ratio –2 dBr signal level

INL Integral Non-Linearity ––±1 LSB Code Density, DC-ramp DNL Differential Non-Linearity ––±0.8 LSB

DG Differential Gain ––±3% –12 dBr, 4.4 MHz signal on DC-ramp DP Differential Phase ––1.5 deg

Analog Video Output

VOUT Output Voltage Out: 1.7 2.0 2.3 VPP VIN = 1 VPP, AGC= 0 dB VOUT AGCVOUT AGC step width, VOUT In: – 1.333 – dB 3 Bit Resolution=7 Steps VIN1 3 MSB’s of main AGC VIN2 ± DNLAGC AGC Differential Non-Linearity –– 0.5 LSB VIN3 VIN4 VOUTDC DC-level – 1 – V clamped to Back porch

BW VOUT Bandwidth 8 10 – MHz Input: –2 dBr of main ADC ≤ range, CL 10 pF

THD VOUT Total Harmonic Distortion –––40 dB Input: –2 dBr of main ADC ≤ range, CL 10 pF 1 MHz, 5 Harmonics

CLVOUT Load Capacitance VOUT ––10 pF ± ILVOUT Output Current –– 0.1 mA

42 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

4.6.4.9. Characteristics, Output Pin Specification

Output Specification for SYNC, CONTROL, and DATA Pins: Y[7:0], C[7:0], AVO, HS, HC, HELPER, INTLC, VS, FSY

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VOL Output Low Voltage –––0.4 V see table below

VOH Output High Voltage – 2.4 ––V see table below

tOH Output Hold Time – 6 ––ns

tOD Output Delay Time –––35 ns NOTE 1

2 NOTE 1: CLOAD depends on the selected driver strength which is I C-programmable.

Table 4–1: Driver strength

Strength VSUPP = 5 V VSUPP = 3.3 V Load Load

000 < 100 pF < 50 pF

001 < 55 pF < 28 pF

010 < 37 pF < 20 pF

011 < 28 pF < 14 pF

100 < 23 pF < 12 pF

101 < 18 pF < 10 pF

110 < 14 pF < 8 pF

111 pins tristate

CLK20 20.25 MHz in case of DIGIT3000 mode

2.0 V LLC1 t t ≤ 5 ns 13.5 MHz R, F in case of LLC Mode 0.8 V

VOH Output Data valid Data valid VOL tOH tOD

Fig. 4–15: Sync, control, and data outputs

Micronas 43 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

4.6.4.10. Characteristics, Input Pin Specification

Input Specification for SYNC, CONTROL, and DATA Pin: MSY (DIGIT3000 mode only)

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

VIL Input Low Voltage –––0.8 V

VIH Input High Voltage – 1.5 ––V

tIS Input Setup Time – 7 ––ns

tIH Input Hold Time – 5 ––ns

CLK20 20.25 MHz in case of DIGIT3000 Mode

VIH Input Data valid VIL tIS tIH

2.0 V LLC1 ≤ 13.5 MHz tR, tF 5ns in case of LLC Mode 0.8 V

VIH Input Data valid VIL tIS tIH

Fig. 4–16: Sync, control, and data inputs

44 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

4.6.4.11. Characteristics, Clock Output Specification

Line-Locked Clock Pins: LLC1, LLC2

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

CL Load capacitance –––50 pF

13.5 MHz Line Locked Clock

1/T13 LLC1 Clock Frequency – 12.5 – 14.5 MHz

tWL13 LLC1 Clock Low Time – 26 ––ns CL = 30 pF

tWH13 LLC1 Clock High Time – 26 ––ns CL = 30 pF

1/T27 LLC2 Clock Frequency – 25 – 29 MHz

tWL27 LLC2 Clock Low Time – 10 ––ns CL = 30 pF

tWH27 LLC2 Clock High Time – 10 ––ns CL = 30 pF

16 MHz Line Locked Clock

1/T13 LLC1 Clock Frequency – 14.8 – 17.2 MHz

18 MHz Line Locked Clock

1/T13 LLC1 Clock Frequency – 16.6 – 19.4 MHz

common timings – all modes

tSK Clock Skew – 0 – 4ns

tR, tF Clock Rise/Fall Time –––5nsCL = 30 pF

VIL Input Low Voltage –––0.8 V

VIH Input High Voltage – 2.0 ––V

VOL Output Low Voltage –––0.4 V IL = 2 mA

VOH Output High Voltage – 2.4 ––VIH = –2 mA

T13

tWH13 tWL13 V LLC1 IH (13.5 MHz ±7%) VIL t tR F tSK tSK

tWH27 tWL27 T27

LLC2 VIH (27 MHz ±7%) VIL

tR tF

Fig. 4–17: Line-locked clock output pins

Micronas 45 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

5. Application Circuit VPC 32x5C

46 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C

5.1. VGA mode with VPC3215C

In 100 Hz TV applications it can be desirable to display While the V-sync is connected to the VGAV pin a VGA-signal on the TV. In this case a VGA-graphic directly, the H-sync has to be pulse-shaped and ampli- card delivers the H, V and RGB signals. These signals tude adjusted until it is connected to one of the video can be feed "directly" to the backend signal process- input pins of the VPC. The recommended circuitry to ing. The VPC can generate a stable line locked clock filter the H sync is given in the figure below. for the 100 Hz system in relation to the VGA sync signals.

+5V analog

100 Ω 47pF 680 nF 1kΩ Video Input VPC 270 Ω 540 Ω H 31kHz BC848B

1N4148 2kΩ

1N4148

GND analog GND analog

Fig. 5–1: Application circuit for horizontal VGA-input

Micronas 47 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET

6. Data Sheet History

1. Preliminary data sheet: “VPC 3205C, VPC 3215C Video Processor Family, Aug. 15, 1997 6251-457-1PD. First release of the preliminary data sheet.

2. Preliminary data sheet: “VPC 3205C, VPC 3215C Video Processor Family, Oct. 19, 1998, 6251-457-2PD. Second release of the preliminary data sheet. Major changes: – Fig. 4–1: Outline Dimensions for PLCC68 changed. – Additional information contained in Supplement No.3 / 6251-457-3PDS, Edition May 25 1998 has been included.

Micronas GmbH All information and data contained in this data sheet are without any Hans-Bunte-Strasse 19 commitment, are not to be considered as an offer for conclusion of a D-79108 Freiburg (Germany) contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability P.O. Box 840 and delivery are exclusively subject to our respective order confirmation D-79008 Freiburg (Germany) form; the same applies to orders based on development samples deliv- Tel. +49-761-517-0 ered. By this publication, Micronas GmbH does not assume responsibil- Fax +49-761-517-2174 ity for patent infringements or other rights of third parties which may E-mail: [email protected] result from its use. Internet: www.micronas.com Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. Printed in Germany No part of this publication may be reproduced, photocopied, stored on a Order No. 6251-457-2PD retrieval system, or transmitted without the express written consent of Micronas GmbH.

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Datasheets for electronics components.