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Characterization and Modeling of TSV Based 3-D Integrated Circuits

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Characterization and Modeling of TSV Based 3-D Integrated Circuits Characterization and Modeling of TSV Based 3-D Integrated Circuits by Ioannis Savidis Submitted in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy Supervised by Professor Eby G. Friedman Department of Electrical and Computer Engineering Arts, Sciences and Engineering Edmund J. Hajim School of Engineering and Applied Sciences University of Rochester Rochester, New York 2013 ii © 2013 Copyright by Ioannis Savidis All rights reserved iii Dedication To my family. My achievements are but an indication of your love and support. iv Biographical Sketch Ioannis Savidis was born in Rochester, New York in December 1982. He received the B.S.E. degree in electrical and com- puter engineering and biomedical engineer- ing from Duke University, Durham, NC, in 2005. He received the M.Sc. degree in electrical and computer engineering from the University of Rochester, Rochester, NY, in 2007. He pursued his research in high performance integrated circuits for the Ph.D. degree in electrical and computer engineering under the guidance of Professor Eby G. Friedman. He interned at Freescale Semiconductor Corporation, Austin, TX during the summers of 2006 and 2007, where he worked on the electrical characterization and modeling of interplane 3-D vias. During the summers of 2008, 2009, 2010, and 2011 he interned at v the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he worked on elec- trical characterization and modeling, reticle design, and DC and high frequency electrical measurements of test vehicles implementing various interplane 3-D via topologies. His research interests include analysis, modeling, and design methodologies for high perfor- mance digital and mixed-signal integrated circuits, emerging integrated circuit technolo- gies, and interconnect related issues, with an emphasis on electrical and thermal modeling and characterization, signal and power integrity, and power and clock delivery for 3-D IC technologies. The following publications were a result of work conducted during his doctoral study: Publications Book Chapter [1] I. Savidis and E. G. Friedman, “Physical Design Trends for Interconnects,” On-Chip Communication Architectures System on Chip Interconnect, S. Pasricha and N. Dutt, Morgan Kaufmann Publishers, Elsevier, Chapter 11, pp. 403-437, 2008. Journal Papers [1] I. Savidis and E. G. Friedman, “Experimental Analysis of Thermal Coupling in TSV- Based 3-D Integrated Circuits,” IEEE Transactions on Electron Devices, (in submis- sion). [2] I. Savidis, S. Kose, and E. G. Friedman, “Power Noise in TSV-Based 3-D Integrated Circuits,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 2, pp. 587-597, Febru- ary 2013. [3] B. Ciftcioglu, R. Berman, S. Wang, J. Hu, I. Savidis, M. Jain, D. Moore, M. Huang, E. G. Friedman, G. Wicks, and H. Wu, “3-D Integrated Heterogeneous Intra-Chip vi Free-Space Optical Interconnect,” Optics Express, Vol. 20, No. 4, pp. 4331-4345, February 2012. [4] V. Pavlidis, I. Savidis, and E. G. Friedman, “Clock Distribution Networks in 3-D Integrated Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Sys- tems, Vol. 19, No. 12, pp. 2256-2266, December 2011. [5] J. Wang, I. Savidis, and E. G. Friedman, “Thermal Analysis of Oxide-Confined VC- SEL Arrarys,” Microelectronics Journal, Vol. 42, No. 5, pp. 820-825, May 2011. [6] B. Ciftcioglu, R. Berman, J. Zhang, Z. Darling, S. Wang, J. Hu, J. Xue, A. Garg, M. Jain, I. Savidis, D. Moore, M. Huang, E. G. Friedman, G. Wicks, and H. Wu, “A 3-D Integrated Intra-Chip Free-Space Optical Interconnect for Many-Core Chips,” IEEE Photonics Technology Letters, Vol. 23, No. 3, pp. 164-166, February 2011. [7] I. Savidis and E. G. Friedman, “Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance,” IEEE Transactions on Electron Devices, Vol. 56, No. 9, pp. 1873-1881, September 2009. Conference Papers [1] I. Savidis and E. G. Friedman, “Test Circuits for 3-D Systems Integration,” Proceed- ings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 181-184, March 2012. [2] H. Wu, B. Ciftcioglu, R. Berman, S. Wang, J. Hu, I. Savidis, M. Jain, D. Moore, M. Huang, E. Friedman, and G. Wicks, “Chip-Scale Demonstration of 3-D Integrated Intra-Chip Free-Space Optical Interconnect (Invited Paper),” Photonics West: Pro- ceedings of SPIE Optoelectronic Integrated Circuits XIV, Vol. 8265, pp. 82650C-1 82650C-10, February 2012. [3] I. Savidis, V. Pavlidis, and E. G. Friedman, “Clock Distribution Models of 3-D Inte- grated Systems,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2225-2228 May 2011. [4] I. Savidis, S. Kose, and E. G. Friedman, “Power Grid Noise in TSV-Based 3-D Inte- grated Systems,” Proceedings of the Government Microcircuit Applications & Criti- cal Technology Conference (GOMACTech), pp. 129-132, March 2011. vii [5] B. Ciftcioglu, R. Berman, J. Zhang, Z. Darling, A. Garg, J. Hu, M. Jain, P. Liu, I. Sa- vidis, S. Wang, J. Xue, E. G Friedman, M. Huang, D. Moore, G. Wicks, and H. Wu, “Initial Results of Prototyping a 3-D Integrated Intra-Chip Free-Space Optical In- terconnect,” Proceedings of the Workshop on the Interaction between Nanophotonic Devices and Systems (WINDS 2010), December 2010. [6] J. Xue, A. Garg, B. Ciftcioglu, J. Hu, S. Wang, I. Savidis, M. Jain, R. Berman, P. Liu, M. Huang, H. Wu, E. Friedman, G. Wicks, and D. Moore, “An Intra-Chip Free-Space Optical Interconnect,” Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA), pp. 94-105, June 2010. [7] J. Xue, A. Garg, B. Ciftcioglu, S. Wang, I. Savidis, J. Hu, M. Jain, M. Huang, H. Wu, E. G. Friedman, G. W. Wicks, and D. Moore, “An Intra-Chip Free-Space Opti- cal Interconnect,” Proceedings of the 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI ’09) held in conjunction with the 36th Inter- national Symposium on Computer Architecture, June 2009. [8] I. Savidis, E. G. Friedman, V. F. Pavlidis, and G. De Micheli, “Clock and Power Distribution Networks for 3-D Integrated Circuits,” Proceedings of the Workshop on 3D Integration, Design, Automation & Test in Europe Conference, March 2009. [9] V. F. Pavlidis, I. Savidis, and E. G. Friedman, “Clock Distribution Architectures for 3-D SOI Integrated Circuits,” Proceedings of the IEEE International Silicon-on- Insulator Conference, pp. 111-112, October 2008. [10] V. F. Pavlidis, I. Savidis, and E. G. Friedman, “Clock Distribution Networks for 3-D Integrated Circuits,” Proceedings of the IEEE Custom Integrated Circuits Confer- ence, pp. 651-654, September 2008. [11] I. Savidis and E. G. Friedman, “Electrical Modeling and Characterization of 3-D Vias,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 784-787, May 2008. Workshop Poster Presentations [1] I. Vaisband, S. Kose, I. Savidis, and E. G. Friedman, “On-Chip Power Delivery,” CEIS University Technology Showcase, Rochester, New York, April 6, 2011. viii [2] B. Ciftcioglu, R. Berman, J. Zhang, Z. Darling, S. Wang, J. Hu, J. Xue, A. Garg, M. Jain, I. Savidis, D. Moore, M. Huang, E. G Friedman, G. Wicks, and H. Wu, “3-D Integrated Intra-Chip Free-Space Optical Interconnect,” IEEE International Solid- State Circuits Conference (ISSCC) Student Research Forum, February 2010. [3] I. Savidis and E. G. Friedman, “Clock Distribution Topologies for 3-D Integrated Circuits,” CEIS University Technology Showcase, Rochester, New York, February 12, 2009. [4] V. F. Pavlidis, I. Savidis, and E. G. Friedman, “Clock Distribution Networks for 3-D Integrated Circuits,” Massachusetts Institute of Technology Lincoln Laboratorys 3-D Integrated Circuit Multi-Project Wafer Review, Boston, Massachusetts, September 15, 2008. ix Acknowledgments As I began writing this section, it became quite evident to me that it is very difficult to express gratitude to all the individuals who have affected my life throughout the years. Various family members, teachers, professors, and close friends have each contributed in molding me into the person that I currently am. Without your support, patience, and en- couragement, I would not be where I am today I would like to begin by sincerely thanking my advisor and mentor, Professor Eby G. Friedman, for his continuous support, encouragement, and direction during the course of my Ph.D. studies. His knowledge, experience, insight, and enthusiasm towards his work has provided me with a model that will guide me through my own research pursuits. The knowledge I have gained goes beyond the basic process of research. Lessons learned on running a laboratory efficiently and productively, properly funding projects, academic writ- ing style, verbal expression, and other nuggets of knowledge that are essential for produc- tive research laboratories are all attributed to my adviser’s tutelage. Professor Friedman, it was a pleasure completing my thesis work under your supervision. I would like to thank Professor Engin Ipek, Professor Hui Wu, Professor Michael Gage, Professor Diane Dalecki, and Professor John Lambropoulos for serving on my proposal and defense committees. Your insightful comments, critical reviews, and helpful advice enhanced both my research and thesis dissertation. I have had the pleasure of working in an environment with a diverse group of individ- uals coming from different professional and cultural backgrounds. Members of the High x Performance Integrated Circuit Laboratory made my Ph.D. experience much more pleasur- able and enjoyable. I would like to thank previous and current members of the laboratory: Dr. Guoqing Chen, Dr. Mikhail Popovich, Prof. Vasilis F. Pavlidis, Prof. Emre Salman, Dr. Jonathan Rosenfeld, Dr. Renatas Jakushokas, Prof. Selcuk Kose, Ravi Patel, Inna Vaisband, Shen Ge, Boris Vaisband, and Alex Shapiro. The long discussions on a variety of topics have expanded the scope of my professional and personal knowledge. I would also like to thank RuthAnn Williams for her endless effort on my behalf, allowing me to focus my time on my research.
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