The International Magazine for the Semiconductor Packaging Industry Volume 15, Number 6 November December 2011

DicingDicing 101:101: LEDS,LEDS, Laser,Laser, MEMSMEMS TrendsTrends DrivingDriving WLPWLP andand 3D3D DirectDirect CopperCopper BondingBonding forfor HighHigh DensityDensity ApplicationsApplications ElectrolessElectroless PlatingPlating forfor ImprovedImproved TesTestt SolderSolder inin thethe AgeAge ofof 3D3D InternationalInternational DirectoryDirectory ofof SolderSolder andand FluxFlux SuppliersSuppliers

CONTENTS

November December 2011 Volume 15, Number 6

The International Magazine for Device and Wafer-level Test, Assembly, and Packaging Addressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS,

The International Magazine for the Semiconductor Packaging Industry Volume 15, Number 6 November December 2011 MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century.

Dicing 101: LEDS, Laser, MEMS FEATURE ARTICLES Trends Driving WLP and 3D Direct Copper Bonding for High Density Applications Electroless Plating for Improved Testt Solder in the Age of 3D Innovation Trends Driving WLP and 3D Packaging 14 InternationalInternational DirectoryDirectory ofof SolderSolder andand FluxFlux SuppliersSuppliers Steve Anderson, STATS ChipPAC Direct Copper Bonding Of High-Density 3D Assemblies 18 Gilbert Lecarpentier, SET, Marc Legros and Mayerling Martinez, CEMES-CNRS, In the midst of tremendous technological changes Alexis Farcy and Brigitte Descouts, STMicroelectronics, Emmanuel Augendre and in manufacturing methods, semiconductor assembly and test houses are still relying on Thomas Signamarcheix, CEA-LETI, and Vincent Lelièvre and Aziz Ouerd, ALES known and reliable processes. Solders and 22 fluxes have evolved into new forms, but the Laser Processing: A Robust Solution for Dicing Ultra-Thin Substrates principle of forming electrical interconnects Kip Pettigrew, Matt Knowles and Michael Smith, ESI from a self-leveling, molten solder joint cleaned by an appropriate semiconductor Solder in the Age of 3D Semiconductor Assembly 25 grade flux remains a core element of the Dr. Andy C. Mackie, Global Product Manager and Tae-Hyun Park, Country assembly process. Front cover image Sales Manager, Indium Corporation courtesy of Indium Corporation.

• Ultra thin package profi le • Scalable heterogeneous integration • Ultra fi ne pitch and maximum I/O density • Low cost solutions • Excellent electrical & thermal performance • High bandwidth wide I/O 3D incorporating TSV

0.5mm down to 0.8mm 3D [.8mm]

down to [.8mm] down to 2.5D 2D [.5mm]

For more information, visit www.STATSChipPAC.com/eWLB

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 1 2 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 3 4 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] CONTENTS

FEATURE ARTICLES Test Improvement via Electroless Plating 31 Terence Collier, CVinc How to Dice Fragile MEMS Devices 34 Alissa M. Fitzgerald, Ph.D. and Brent M. Huigens, AMFitzgerald & Associates Dispensing Advantages for MEMS Wafer Capping 36 Akira Morita, Nordson ASYMTEK LED Dicing: The Sapphire Blaze Indeed 38 Jeffrey Albelo, Quantum-Group Consulting, Ltd. DEPARTMENTS From the Publisher 2011 in Retrospect 6 Kim Newman, Chip Scale Review Patents Changes to Patent Legislation 9 Jason Mirabito, Mintz, Levin, Cohn, Ferris, Glovsky and Popeo, P.C. Guest Editorial Backside Illumination Highlights Direct Bonding Technology 10 Kathy Cook, Ziptronix Industry News 12 Chip Scale Review staff International Directory of Solder and Flux Suppliers 29 Ron Molnar, Az Tech Direct LLC Product Showcase 46 Editors Outlook ACT IV. 47 Ron Edgar, Chip Scale Review Contributing Editor Advertiser Index, Advertising Sales 48

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 5 FROM THE PUBLISHER The International Magazine for Device and Wafer-level Test, Assembly, and Packaging Addressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS, MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century.

STAFF Kim Newman Publisher [email protected] Ron Edgar Technical Editor [email protected] 2011 in Retrospect Françoise von Trapp Senior Technical Editor [email protected] Sandra Winkler Contributing Editor [email protected] he past 12 months have been a busy time for everyone at Chip Scale Dr. Thomas Di Stefano Contributing Editor Review. As this is our last issue of 2011, it seems to be a good time to [email protected] Treflect on our progress and look forward to what 2012 will bring for us and for the Paul M. Sakamoto Contributing Editor Test industry at large. [email protected] Jason Mirabito Contributing Legal Editor 2011 brought many things to the table for us all. Once again, we successfully [email protected] published six spectacular issues of Chip Scale Review in both print and digital covering technology advancements in established semiconductor packaging SUBSCRIPTION--INQUIRIES processes and technologies, as well as a myriad of innovations being pursued by Chip Scale Review research institutes all over the world (SEMATECH, Ga Tech, ITRI, and CEA Leti). T 408-429-8585 F 408-429-8605 Additionally, our eNL CSR Tech Monthly, still in its infancy, has gained momentum Carrie Stalker as a supporting media buy to the print for CSRs advertisers. 12 issues of the CSR [email protected] Tech Monthly were broadcast in 2011 with another 12 on the way in 2012. I’m happy to report that the 2012 media kit is hot off the press and available online. Advertising Production Inquiries: Chip Scale Review supported three major trade events in 2011 as the Official Kim Newman [email protected] Media Sponsor for both the BiTS Workshop and the Electronic Components Technology Conference (ECTC); as well as our very own co-sponsored event with EDITORIAL ADVISORS SMTA – the International Wafer-Level Packaging Conference (IWLPC ). You can Dr. Thomas Di Stefano Centipede Systems read up on this year’s IWLPC in the Industry News section of this issue (pp. 12-13) Andy Mackie Indium Corporation or check out the video clips on the CSR website. Guna Selvaduray San Jose State University C.P. Wong Georgia Inst of Technology Also vital to the success of Chip Scale Review our editorial advisors, who help Ephraim Suhir ERS Company navigate the editorial direction and scope of the magazine and assist in recruiting Nick Leonardi Premier Semiconductor Services exclusive technical features throughout the year. On behalf of everyone at CSR, we John Lau Industrial Tech Research Inst (ITRI) continue to appreciate those members who have been long standing advisors over Alissa Fitzgerald A.M. Fitzgerald & Associates the years including: Tom Di Stefano of Centipede Systems; Andy Mackie of Indium Joseph Fjelstad Verdant Electronics Venky Sundaram 3D (PRC) Georgia Inst of Technology Corporation; CP Wong, Regents Professor at Georgia Institute of Technology; Guna Rolf Aschenbrenner Fraunhofer Institute Selvaduray, Professor Materials Engineering at San Jose State University; Ephraim Fred Taber BiTS Workshop Suhir of ERS Company; and Nick Leonardi of Premier Semiconductor. Newcomers Scott Jewler Powertech Technology Inc. to this distinguished list include: Rolf Aschenbrenner, Deputy Head at Fraunhofer

Copyright © 2011 Haley Publishing Inc. Institute; Alissa Fitzgerald of AM Fitzgerald & Associates; Joseph Fjelstad, Verdant Chip Scale Review (ISSN 1526-1344) is a registered trademark of Electronics; Scott Jewler of Powertech Technology Inc; John Lau of ITRI; Venky Haley Publishing Inc. All rights reserved. Sundaram of 3D PRC, Georgia Institute of Technology; and Fred Taber Chairman

Subscriptions in the U.S. are available without charge to qualified of the BiTS Workshop. individuals in the electronics industry. Subscriptions outside of the Chip Scale Review’s past and future success can be attributed to the editors and U.S. (6 issues) by airmail are $100 per year to Canada or $115 per contributors of the columns, the guest editorials and of course the technical features. year to other countries. In the U.S. subscriptions by first class mail I would like to personally thank and acknowledge each and every columnist and are $95 per year. author who contributed their article to CSR. A special thank you to Technical Editor Chip Scale Review, (ISSN 1526-1344), is published six times a Ron Edgar who supported CSR throughout the year and has provided his final year with issues in January-February, March-April, May-June, July- column in this edition entitled “Act IV”. After deliberation Ron has decided to focus August, September-October and November-December. Periodical postage paid at Los Angeles, Calif., and additional offices. on his career at hand. We wish him well and the very best ahead.

POSTMASTER: Send address changes to Chip Scale Review magazine, P.O. Box 9522, San Jose, CA 95157-0522 Kim Newman Printed in the United States Publisher

6 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 7 8 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] PATENTS

Changes to Patent Legislation By Jason Mirabito, [Mintz, Levin, Cohn, Ferris, Glovsky and Popeo, P.C.]

n September 16, 2011, wherewithal to file applications early. issue date. It is permissible to bring President Obama signed Time will only tell whether this becomes any ground or grounds for invalidity Othe Leahy-Smith America Invents Act, an impediment for small companies to to the attention of the USPTO, not just probably the most comprehensive patent file patent applications. limited to prior printed applications. The reform legislation in the last 40 years. European Patent Office has a similar This article focuses on two changes Enacting Post Grant Procedures post-grant review and the change in the that have great impact. The first is a There have been allegations that U.S. law makes U.S. law conform to that fundamental change to the U.S. patent the USPTO allowed patents to issue of the European Patent Office. application filing system and the second that should not have issued in the first Under the second procedure, Inter is a fundamental change to the ability of place. Therefore, Congress decided that Partes Review, any time after the nine third parties to challenge patents. there were not sufficient safeguards month post-grant period expires, a built into the USPTO system to catch requestor can request a reexamination of First-to-File System Enacted “bad” patents. Since at least 1980, the patent; but here the request is limited For many years under U.S. Patent parties have been able to file requests to prior printed publications. While the Law, the U.S .has been under a “first for reexamination. This part of the pre- entire provision does not come into to invent” system. According to this existing patent statute allows third effect immediately, the part that relates system, even if there are two (or parties (even the patent owner) to to the standard under which the USPTO more) persons file for a patent at the present the Patent Office with prior will grant a request for a review comes United States Patent Office (USPTO), art consisting of printed publications into effect immediately. The old test was the earliest of those two inventors and allege that the claims as issued in that of “raising a substantial question of is not necessarily considered to be the patent are not valid on the basis of patentability”. The new test is “whether the inventor. In what is called an this same prior art. Up until recently, there is a reasonable likelihood that interference proceeding, the USPTO the only type of reexamination that the petitioner will prevail with respect determines the first inventor by was permitted was a so called Ex to at least one challenged claim”. This looking at invention records, etc. These Parte Reexamination, where the party will raise the bar and the level of proof interference proceedings are long and requesting the reexamination (the needed before the Patent Office will have been traditionally very expensive. requestor) had very limited participation. grant such a petition. The U.S. has now gone to a first- to- Circa 1999, the so called interpartes A third addition is called Supplemental file system.This means simply, whoever reexamination system came into being Examination, which can be requested gets to the USPTO first and files their that allowed requestors relatively full by the patent owner only and allows application first is the first inventor. participation in the reexamination the patent owner to have the USPTO Period. It is believed that this change process, including the ability to appeal consider information related to the puts the U.S. in the same position as through to the U.S. Court of Appeals for patent. every other country in the world, which the Federal Circuit. Fourth, and finally, the “old” ex parte all have first-to-file systems. During the The just enacted law now provides reexamination law will still continue to pendency of this portion of legislation, four avenues by which requestors can exist and, in fact, coexist with the other there was much criticism of this shift to challenge the validity of the claims of provisions that have been enacted. a first-to-file system by small inventors a patent. The first is the so-called Post It is expected that the new and and some small companies, who argue Grant Review, which will allow third expanded post grant procedures will that this change would benefit larger parties to challenge the validity of a keep the USPTO very busy in the companies that have the money and patent within nine months of the patent coming years.

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 9 GUEST EDITORIAL

Backside Illumination Highlights Direct Bonding Technology

By Kathy Cook, [Ziptronix]

ith backside illuminated mainstream semiconductor application (BSI) sensors in high- in the consumer electronic market space volumeW production and interposers to move into the third dimension in seemingly ready to take off, the time volume production. for 3D integration has finally come. The fact that direct bonding technology Direct bonding has played a key has been licensed commercially and role in enabling BSI image sensor is in high volume production serves manufacturing and will continue to do as confirmation of the strength of the so in other 3D applications.With the patents covering the technology. IP technology now licensed commercially, companies have no choice but to protect there are fewer questions about the their own intellectual property in order to feasibility of direct bonding technology survive, but when large, well-respected than in the recent past. companies take a license, people tend to BSI image sensors have better pay attention. performance than their FSI counterparts. Other types of bonding technologies do The improved performance is due to the not offer the same benefits in the area of fact that the metal interconnect layers are Figure 1. (Top) Front side illuminator technology vs. 3D integration. The closest competition positioned below the photodiode layer as (Bottom) BSI using front-side processes. includes bonding technologies such as opposed to above it (Figures 1a and b). turn produces higher yields and lower cost adhesive bonding or thermo-compression Within the BSI image-sensor per die. bonding. Because there is not a thick later manufacturing space, direct bonding The growth of the BSI market has of additional material required, direct technology enables device manufacturers outpaced original market expectations, bonding technology results in lower to achieve lower distortion than other and according to Yole Développment, it distortion than other technologies – a key technologies (Figures 2a, b and c). The is expected to exceed $16B cumulatively metric for image sensor manufacturers. result is that pixels can be scaled smaller, over the next four years (Figure 3.) resulting in more die per wafer. This in The Technology Implication of Commerical Licensing Direct bonding technology stems from within the Image Sensor Market more than 20 years of material research One proprietary direct bonding resulting in an elegant, but simple and technology has been in existence for highly efficient solution for volume several years, and the technology is manufacturing involving two or more now gaining momentum in the market. separate substrates or devices. These BSI image sensors are the first real processes are designed to use standard semiconductor wafer fab equipment and do not require expensive custom or specialty wafer processing equipment. Wafer bonding equipment options required for direct bonding are varied and range from relatively simple and inexpensive to much more complex. Some of the factors to consider include Figure 2. a) Direct bond technology b) Assembly is flipped and thinned c) Final BSI alignment accuracy requirements

10 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] and level of automation required. As mentioned, direct bonding technology is enjoying wide adoption. The patents involved Figure 3. BSI image sensor projections presented at the Image are broad and Sensors Europe Conference in March of 2011 involve low- temperature bonding of insulators, silicon, III-V and other dissimilar materials. The technology involves planar, homogeneous bonding surfaces, and is currently being used in high-volume manufacturing applications. Bonding can occur at relatively low temperatures due in part to a surface activation/termination step that is one component of the technology. A second area of significant activity is direct bond interconnect and is based on the same principles as the direct bond technology, but includes conductive interconnects, so therefore involves planar, heterogeneous bonding surfaces. This technology gives customers a high-density, scalable interconnect method that leverages high-volume foundry processes. Figure 4 is an SEM image showing the bond interface of a Figure 4. SEM of logic and pixel wafers’ bond connection made between interface using the direct bond interconnect process a pixel wafer and a logic wafer at a pitch less than 2µm. Direct bond interconnect has not yet been licensed in the consumer electronics space, so there still are opportunities for exclusivity within these markets. Beyond the image sensor space, there are several applications for direct bonding technology both with and without interconnects. Other applications include pico projectors, various types of stacked devices, RF front-end applications, MEMS and other heterogeneous applications.

Summary BSI image sensors have paved the way for many 3D integration applications, some of which are already being geared up for volume production. Direct bonding is a key enabler within the 3D technology arena and is garnering much attention, both with and without interconnect, in new, advanced image sensors and a variety of other applications. Wafer stacking made possible by direct bonding is allowing chips to move out of the x-y plane and into the z-direction.

Kathy Cook, Director of Business Development, Ziptronix, may be contacted at [email protected].

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 11 INDUSTRY NEWS

IWLPC 2011 – Exploiting the 3rd Dimension By Ron Molnar [AZ TECH DIRECT]

ointly hosted by SMTA and Chip leader in advanced copper pillar bump and Scale Review, the International packaging technologies which enables Wafer Level Packaging Conference next generation flip chip interconnect. J(IWLPC) held October 3 – 6, 2011 in Santa Clara, CA validated the growing demand for more IC functionality in smaller IC packages by exploiting the 3rd dimension. “The SMTA was very pleased to Figure 2. John Crane of Boschman has a captive see a 20% increase audience from Agilent in attendance Aehr Test, Boschman, EV Group, at IWLPC.” Kyzen, NEXX Systems, Owens Design, Figure 4. Curtis Zwenger, Amkor, discusses the Noted SMTA Pac Tech USA, Promex, Quik-Pak/Gel- company’s latest TSV and copper pillar flip chip Administrator, Pak, Silex Microsystems, TechSearch technologies JoAnn Stromberg, International and Tessera. EV Group, Inc. provides leading- “In conjunction edge wafer processing equipment for with Chip Scale Generous Sponsors MEMS and Microfluidics, advanced Figure 1. SMTA reported a Review we were Helping to make IWLPC the best packaging, compound semiconductor/ 20% increase in attendance able to organize industry conference on wafer level MOEMS, SOI, power devices and nano- at IWLPC 2011 another strong packaging were seven generous corporate technology applications. EVGs product technical program focused on leading-edge sponsors. They were led by the Platinum- portfolio features double sided mask/bond topics such as 3D, wafer level, and MEMS. level sponsors, Amkor Technology, EV aligners, wafer bonders for anodic silicon With a sold out exhibit floor, outstanding Group, and NEXX Systems. Gold level fusion, thermocompression and low temp speakers, and enthusiastic attendees we look sponsors included Nanium, PacTech, plasma bonding, wafer/mask cleaning forward to 2012 and another strong IWLPC.” STATS ChipPAC, and SUSS MicroTec. systems, photoresist spin/spray coaters This year’s event, organized by Conference and developers, hot embossing and nano- Chair, Andy Strandjord of PacTech USA, imprinting systems, and defect and particle and Technical Chair, Luu Nguyen of Texas inspection systems. Instruments, consisted of 29 technical presentations organized in three parallel tracks, two panel discussions, six half-day tutorials, a poster session, two morning plenary sessions, and it was highlighted by an entertaining dinner keynote speech from Raj Master of Microsoft. Figure 3. At the STATS ChipPAC exhibit, Steve Exhibit Hall “Sold Out” Wofford, Sr. director of worldwide marketing The exhibit hall was sold out this communications explains the company’s latest WLP offering to an interested attendee year with booths from 44 companies (up Figure 5. Garret Oakes, director of technology, EV from 38 exhibitors in 2010) – prompting Amkor Technology, Inc. is one of the Group, talks about the company’s recent expansion the hosts to move the event to a larger world’s largest providers of advanced at its world headquarters in Schaerding, Austria venue in 2012. There were 20 new semiconductor assembly and test NEXX Systems has pioneered exhibitors this year. services. They offer a suite of services, economical and flexible solutions Steady supporters that have exhibited including electroplated wafer bumping, addressed specifically to wafer level the last three years in a row include: probe, assembly and final test. Amkor is a packaging (WLP). NEXX has become

12 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] a global leader in the design and Talking Technical Judging by attendance figures, the most manufacture of advanced packaging Three parallel tracks of technical popular session was definitely Session processing systems that enable smaller and presentations were offered again this year 1 – Advanced Wafer Level Packaging faster consumer electronics. covering WLP, 3D and MEMS topics. Technologies, followed closely by In total, there were 29 presentations. (continued on Page 42)

Figure 6. At Nexx Systems - John Bowers VP worldwide sales meets with Michael Schneider of ECI Attendance Grows Nearly 25% Interest and activity in the area of wafer level packaging (WLP) continues to grow. This year’s conference drew 460 attendees – up nearly 25% over the 370 registrants for the 2010 event. Participation from the international community also continues to grow. IWLPC 2011 drew attendees from 15 countries – led by the United States, Germany, Japan, Korea, China and the United Kingdom.

Popular Tutorials The organizers were proud to offer six half-day tutorials to 92 students by a number of well-known and respected industry leaders as a means of educating those unfamiliar with wafer level and advanced packaging technologies. The two most popular tutorials were “Wafer Level Packaging” by Luu Nguyen, Ph.D. of National Semiconductor and “TSV and Key Enabling Technologies for 3D IC/Si Integration and WLP” by John Lau, Ph.D. of Industrial Technology Research Institute (ITRI).

Figure 7. Keith Cooper, SET North America, delivers an interesting talk on updated processes collective hybrid bonding for C2W processes

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 13 Innovation Trends Driving WLP and 3D Packaging By Steve Anderson [STATS ChipPAC]

he market for portable and can be provided that reduces mobile data access devices costs, package thickness, and Tconnected to a virtual cloud access integrates more functions in point is exploding and driving both a single package. increased functional convergence as well as increased packaging complexity 3D vs. Heterogeneous and sophistication. This is driving an Approaches unprecedented demand to increase the While the need to combine variety of wafer level, thin POP, and more mobile functions in TSV/interposer packaging solutions. an efficient, low-profile Figure 1. If flip chip is the current workhorse, solution is fueling the shift Driving Forces Increasing Wafer Level Packaging Growth appear in late 2013 or 2014. TSVs then we can expect to see more exciting towards 3D packaging, challenges still help enable the increased density by interconnect technologies such as TSV, remain in the areas of design, testing, packing a great deal of functionality 2.5D interposers, FO WLP and 2nd mass production, cost effectiveness, into small form factors with multiple generation FO WLP to meet these needs. and materials compatibility. Given that heterogeneous functions such as logic, system-in-package (SiP), package-on- analog, RF, memory and MEMs. This package (POP), and 2.5D interposer 3D and Advanced Packaging Evolution technology provides an alternative Connectivity is the key to both technologies have become more mature to expensive system-on-chip (SOC) business and consumer electronics and widespread, the further deployment development and allows technology growth as huge investments in wireless of embedded wafer level technologies from different nodes to be combined in and 3G/4G networks accelerate and TSV will continue to drive the a single package. development of new packaging migration from 40nm to 28nm. The technology. Particularly important in this heterogeneous integration capabilities next generation of wafer level packaging of these technologies is enabling a more Fan-Out Wafer Level Growth Much of the initial industry work (WLP) is the need for higher bandwidth, holistic design approach by combining to develop and deploy fan-out WLP, improved thermal dissipation and multiple die with memory, integrated (FOWLP) led by embedded wafer materials, and the capability for higher passives, and mixed technology nodes level ball grid array (eWLB), has been current per bump without creating to provide lower cost, thin profiles and on 200mm wafers (Figure 2). The electro migration (EM) failures. more reliable, packaging solutions. focus is now on 300mm formats that Driving forces behind wafer-level and enable this technology to be more cost silicon-based technologies include smaller Mobile Computing Convergence competitive and scale more efficiently. Driven by the need for higher levels footprint, increased functional integration, FOWLP panel sizes larger than 300mm of integration, improved electrical increased I/O density, improved electrical improve the cost structure, increase performance, or reduction of timing and thermal performance, and lower production efficiencies as well as enable delays, the need for shorter vertical cost due to batch processing (Figure 1). interconnects is forcing a shift from 2D Examples include: to 2.5D and 3D package designs. 3D • Fan-in wafer level bumping with integration is proceeding on three fronts, tighter pitches for shorter signal moving from the package level (die lengths and package stacking) to wafer level, • Embedded fan-out wafer level especially fan-out wafer level packaging solutions (FO WLP), and more recently at the • High-speed memory and processor silicon (Si) level for through silicon va applications with high bandwidth (TSV) and interposers. interconnect that move beyond Co-design between the silicon and today’s POP technology solutions the packaging is required to achieve • Full implementation of TSV 3D an optimized cost and system solution. packaging technology for mobile When co-design can be done with products integrated passives, a new level of WLP 3D TSV technology is slated to Figure 2. eWLB Fan-Out package

14 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] to multi-chip solutions in one-layer routing, to more complex multiple layers, IPD integration, POP versions and ultimately, SiP, SoP, and complete 3D solutions utilizing TSV. Table 1 highlights some next generation eWLB packages and specifications. All of these configurations are well within Table 1. Key focus of next-generation FOWLP the uniquely robust capabilities of packaging development efforts this technology as a solid integration (a) a wider range of single die and multi- platform. The ability to route finer die configurations. The proliferation of lines and spaces enables a wider range FOWLP configurations is expanding of packages ideal for the growing as the demand for increased packaging smartphone and tablet markets. density grows, especially in 3D applications. eWLB with Integrated Passives eWLB is available in both large 2nd Generation FOWLP and small body sizes, allowing for a While first-generation FOWLP wide range of integration capabilities enabled very dense single and enabled by multiple layers of routing multilayer packages, new performance as well as vertical stacking and passive (b) requirements are pushing these integration. (Figure 3). Essentially, this Figure 3a. Embedded inductor and (b) SEM packaging limits toward second enables very thin side-by-side device micrograph of cross-section of 2-layer RDL eWLB generation FOWLP. Achieving and passive integration for powerful mainstream status for FOWLP cost-effective systems. When vertically Multiple die FOWLP (horizontal) technology status requires a broad stacked, eWLB enables very high The integration of one to four die approach with flexible, cost-effective bandwidth and reliable high density along with passive functions provides solutions ranging from single die 2.5D package solutions. significant performance, size reduction,

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 15 way to the next level of thin packaging capability. They provide a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low-warpage 2.5D and 3D solutions. The use of these embedded FO WLP packages in a side- by-side configuration to replace a stacked Figure 4. 12x12mm eWLB packages with two die (a) package configuration, or to utilize as the and double layer RDL with 0.4mm pitch base for a 3D TSV configuration, is critical and device integration critical to 2.5 to to enable a more cost effective mobile 3D system requirements of high yields market capability. A cross-section of this and affordable price points (Figure 4). type of package is shown in Figure 6. As cloud computing gains (b) Combining wide I/O interfaces with the prominence, new designs are emerging Figure 6a. Super thin FOWLP POP – adoption of TSV packaging capability can provide an that require much larger FOWLP body FOWLP technology for 2.5D applications optimum solution for achieving the best sizes than in production today. This large time reduction. This redistribution performance in thin multiple-die stacks die FOWLP will again push material structure reduces the stack height whereby aimed at high-volume manufacturing. and manufacturing requirements to a 12x12mm package can have a total have efficient panel sizes and good stacked die height of less than 1.0mm High-Density Solutions in a manufacturing process control. (Figure 6). The reduced interconnect Heterogeneous Configuration lengths will also provide better electrical The business and consumer drive for eWLB POP driving 2.5D system performance and lower parasitic values. greater portability and data on demand Low-power mobile device is forcing increased packaging density applications are driven by the need Beyond Wafer Level Packaging and more cost-effective 3D solutions. for increased bandwidth and speed. Increased interconnect density is driving While POP technologies are effective Putting this level of computing smaller bond pad pitches, stacked die, for integrating functions in a small performance and networking capability mixed interconnect, and advanced package, they lack the high bandwidth into consumer and lower cost business interconnect technologies such as and low-profile increasingly needed by systems that were once considered high- interposers and TSVs. Footprints the new generation of thin tablets and end is driving a more aggressive push are shrinking driven by reducing more powerful mobile processors. towards advanced WLP solutions and lithography nodes while maintaining or Technical and manufacturing issues 3D packaging, given the limited form increasing the I/O count and driving the are key challenges for 3D stacks. These factors and space required for increased external ball pitch below 0.4mm down include testability and yield, scalability, battery life (Figure 5). to 0.35 or 0.30mm. This trend is driving thermal and standardized IC interface customer ball patterns to manage the challenges. 3D TSV packages are being Super Thin FOWLP POP escape routing and costs for system developed to provide heterogeneous Further integration and form factor boards. Overall package performance integration of memory, logic, graphics, and reduction can be achieved by using a is heavily influenced by electrical and power functions that cannot be integrated vertical FOWLP package where the thermal performance. The modeling and into single die; and to provide improved die and redistribution layer serve as the management of these functions is much electrical performance below 28nm from interposer, eliminating costly laminate more critical as more functionality is very short and high density interconnects build-up substrates and providing cycle absorbed in fewer packages within these between the stacked ICs. Figure 7 shows heterogeneous 3D an example of the transition from 2D to packaging structures. 2.5D and finally to 3D. System performance can be increased and TSV Technology improved if proper 3D TSV technology is driven particularly packaging elements by the need in smartphones and tablets can be implemented. for much faster processing speeds and memory bandwidth in order to manage FO WLP Package as all of the advanced functions required TSV Interposer of these products. For successful Wafer level market penetration, the TSV ecosystem Figure 5. Progression of next generation eWLB technology from 2D to 3D for technologies such as comprising IDM, OEM, OSAT, highly integrated packaging solutions eWLB are leading the foundries, design houses, and PCB

16 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] Figure 7. Transition from 2D packaging to thin 3D TSV suppliers must be properly enabled. The advantages of the TSV packaging approach over SOC are many including higher bandwidth due to the shorter interconnects, power reduction, lower cost, greater miniaturization and greater modularity and flexibility.

TSV Challenges and Design Requirements Extensive retooling for design is not required to create TSV packaging. There appears to be no major roadblocks in process technology. However, new capabilities are required to route and connect fine pitch microbumps . Package co-design and integrated process control is key for successful implementation of widespread TSV usage. While thin wafer backgrinding is available, backside TSV reveal, stealth dicing, and fine pitch thermal compression bump bonding are still under development and testing.

Conclusion Building the 3D packaging infrastructure requires a good system to manage the IC, packaging, and the board design while trying to establish common standards for at least the memory interfaces. An ecosystem consisting of IP suppliers, foundries, OSATS, IDMS, OEMS, and design houses is being developed with co-design and standards collaboration. Cost effectiveness depends on the proper co-design of the chip, package, and board. As the demand for mobile and portable electronics grows, the demand for smaller, lighter, and higher bandwidth packaging will grow evolving from today’s POP configurations to more complex embedded WLP and vertical 3D TSV technology. Differentiation and even product success is being driven by the ever-expanding feature sets, functionality, convergence and adoption of more computing rich gesturing and graphic applications. The additional increase in cloud computing access points requiring improved packaging for the mobile networking market will only further 2.5D and 3D packaging variation adoption. Next-generation packaging such as TSV and next- generation FOWLP is enabling these advances and proves to provide more exciting developments in the future.

Steve Anderson, Senior Director, Product and Technology Marketing – Advanced Technology, STATS ChipPAC, may be contacted at [email protected].

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 17 Direct Copper Bonding Of High-Density 3D Assemblies By Gilbert Lecarpentier [SET], Marc Legros and Mayerling Martinez [CEMES-CNRS], Alexis Farcy and Brigitte Descouts [STMicroelectronics], Emmanuel Augendre and Thomas Signamarcheix [CEA-LETI], and Vincent Lelièvre and Aziz Ouerd [ALES]

uch of today’s activity Contact density may reach tens of Equipment Development to develop cost-effective thousands of connections per square SET created a new design Mmultilayer 3D assemblies in volume millimeter. This is made possible configuration of pick-and-place production focuses on the near-term both by the higher placement equipment by modifying the proven problems and tradeoffs of vertically accuracy in direct bonding, and by the FC300 platform to operate in a Class interconnecting stacked layers of monometallic connections eliminating 10 environment and to meet the devices and sub-systems either with the potential thermal expansion precision placement requirements of through-silicon-vias (TSV) or silicon mismatch stress that may occur direct copper-to-copper bonding. This interposers. However, in 2009 the between different metals. high-placement-accuracy platform has French Government took a longer-term Better electrical performance is been developed as the base of the new view by funding PROCEED, a 2-year attained, with lower ohmic values system, designed for the special needs research project to increase the density per unit area than older bonding of the PROCEED project. of vertical connections through the use approaches. The direct bonding The design changes for accuracy of direct copper-to-copper bonding. approach provides high mechanical have mainly focused on the optics and The goal of the PROCEED project and electrical integrity. Unlike eutectic bond head stages, which move over the is to demonstrate higher density solder assembly, the bonding interface wafer during its population. To meet interconnects with a placement is void-free, resulting in lower electrical the direct metallic bonding cleanliness accuracy of less than 1µm for chip-to- resistance, higher strength, and better requirements, the system was modified to wafer (C2W) interconnections linked reliability. The process provides robust provide a low particulate contamination by direct metallic copper-to-copper self-sealing for C2W stacking without design that meets Class 10 environmental bonding. Higher connection densities requiring any adhesive or underfill. standards. The primary areas needing will be an advantage in assembling C2W stacking results in higher yields modification to achieve the required level high-performance circuits with 3D than wafer-to-wafer (W2W) stacking. of cleanliness were the cable channels, interconnections. Higher connection The low-complexity process the mechanical housing, and the air densities will enable a wide range of described here allows room circulation through the machine. applications in microelectronics as well temperature assembly with ambient The main features of the modified pick- as in optoelectronics and in MEMS. air at atmospheric pressure. Bonding and-place equipment are its suitability Direct copper-to-copper bonding requires only low forces. That to direct bonding and its alignment requires good planarity and excellent combination is an advantage in capability (Figure 1). These were assessed surface quality. The controlled bonding reducing line throughput time, which is independently through particulate environment has to maintain a low level essential for high-volume production. contamination measurements, transmission of contamination from metallic particles electron microscopy (TEM) imaging of and other sources. Both the smooth Team Members and Tasks the bonding interface, and post-bonding finish of the copper pillars and pads The suite of skills essential for alignment evaluation by infrared (IR) and as well as the topography between the this task required the collaborative acoustic microscopy (SAM). copper and oxide areas are critical to efforts of five groups, each with expert achieving good bond strength. skills in some aspect of the problem: handling and bonding equipment Direct Bonding Advantages (SET), bonding surface preparation The C2W direct bonding process has (ALES), bonding (CEA-Leti), several advantages over conventional developing semiconductor solutions eutectic solder bonding and thermo- across the spectrum of electronics compression bonding processes often applications (STMicroelectronics), and considered today for 3D integration. assessing and comparing the results A major advantage of the direct through an industrial test vehicle bonding processes advanced by this (CEMES-CNRS). Each partner’s program is very high density of the contributions are described here in Figure 1. An inside view of the SET FC300 Bonder vertical interconnects it supports. further detail. with direct metallic bonding configuration

18 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] Surface Preparation is fulfilling its usual role of being an for semiconductor C2W assembly. Air Liquide Electronic Systems interface between industry and academic Bonding at room temperature with ambient (ALES) is supplying technology to research and between equipment air at atmospheric pressure avoids the time provide the required surface preparation. suppliers and an integrated device and complexity of vacuum chambers. The approach is based on a wide manufacturer (IDM). The PROCEED Eliminating adhesive materials avoids knowledge of chemical-mechanical project extends this activity to include handling, dispensing, and controlling polishing (CMP) and cleaning solutions 3D integrated system technologies using liquids. Consequently, direct bonding is design. In this program, new chemistries D2W direct bonding already in use at an industrial scale for the were developed to meet very stringent A driving force for 3D integration is the mass production of silicon-on-insulator (SOI) substrates. Direct bonding was also recently demonstrated with conventional damascene surfaces. These are mixed planarized surfaces that include low-pitch copper interconnects in an oxide matrix, creating conductive paths across the bonding interface. Applying damascene direct bonding to 3D integration in a C2W scheme brings in several key benefits compared to current approaches. Copper-to-copper direct bonding enhances bonding accuracy for high- density interconnections by avoiding the potential thermal expansion mismatch Figure 2a. AFM image of a copper surface after a one minute post CMP cleaning with chemical solutions. of bonding different materials. To ensure (b) SEM image of a 2 X 5 µm through-silicon via (TSV) filled with ECD copper using electroplating chemistry void-free bonding, the alignment and requirements of the direct bonding need for an economically viable approach bonding steps must be carried out in surfaces (Figures 2a and 2b). to achieve innovative multifunctional a particle-free environment. This is In addition, development within the systems through the assembly of accomplished by using special materials PROCEED project included a specific heterogeneous existing sub-parts. Through and by careful management of the and easily adjustable dilution and such repartitioning, sub-parts can be kept bonding environment to protect the wafer distribution unit that is capable of both small in size, requiring few mask levels surface while it is being fully populated applying and and yielding shorter interconnects, thereby with dice. Because the bonding process controlling improving yield, cost, performance and takes place at low force and room the surface energy efficiency. Although 3D integration temperature, line throughput is increased, preparation can be achieved through W2W stacking, adding capacity and reducing costs. chemistries performing C2W assembly conveys Low-force bonding process is key to the ( Figure 3) . further benefits in terms of flexibility high throughput required for widespread Depending (namely in sub-part size, technology or adoption of 3D IC integration. on the final supplier) and yield (relying on known The trend towards 3D integration integration good die (KGD) and avoiding long-range originated in the need for an scheme, this overlay issues). economically viable scheme to achieve unit could be Direct bonding has emerged as a innovative multifunction systems through installed in the powerful technique in the field of substrate the assembly of heterogeneous existing equipment in engineering. When the two mirror- sub-parts. Through repartitioning, sub- accordance polished surfaces are put in contact, parts can be kept small in size, requiring with clean room they are initially held together at room few mask levels and yielding shorter specifications temperature by adhesion forces (Van der interconnects to improve yield, cost, and mechanical Waals forces or hydrogen bonds), without performance and energy efficiency. requirements of any additional materials. At that point, the alignment their adhesion is weak and the bonding Applications Development process. is reversible. To strengthen and complete STMicroelectronics is driving the the bonding, the bonded pair is usually application of this technology for high- Bonding given a thermal treatment right after direct density 3D integration and participating Figure 3. 3D drawings of an Development bonding, which causes covalent bond in the elaboration of the specification example of on-board surface In this project, formation, thereby closing the interface. for future high-volume machines. This treatment equipment CEA/LETI Direct bonding is even more attractive role within PROCEED exists in the 3D

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 19 test chip integration for technological demonstrations of the direct bonding process. First, wafers with multiple back- end of line (BEOL) interconnect levels were provided to validate the surface preparation treatment compatibility with CMOS technology, especially considering the topology due to the presence of multiple BEOL levels. Then, a 3D test chip, which embeds several active a b c structures, was integrated according to a Figure 5. TEM images of the copper to copper interface after direct bonding and annealing at various full CMOS 65nm node process flow for temperatures. Note the decreasing flatness of the interface, especially at grain boundaries. a) RT to 100°C; functional demonstration. The electrical b) RT to 300°C; c) RT to 500°C results are expected to validate both microelectronics as well as in 200µm to form TEM-observable foils. the D2W stacking tool and the direct optoelectronics and in MEMS, including The TEM observations clearly show bonding technology. applications requiring high-density that as the annealing temperature The availability of a high accuracy pick- 3D interconnects, such as photonics, increases, the initially flat copper- and-place tool that meets the requirements multimedia and wireless. to-copper interface is gradually of a direct bonding process paves the way However, the need to first explore the transformed into a zig-zag shape. This towards a new generation of 3D integration challenges of providing low roughness change in itself leads to a stronger bond. technology. Improved placement accuracy and zero-defect surface, as well as ultra- Figure 5 shows an example. provides higher contact density and clean D2W stacking compatible with clean Directly annealing a sample inside better electrical performance compared room specifications, makes a research the TEM (in situ TEM) further showed to traditional eutectic bonding for 3D and development project like PROCEED that this zig-zag shape is initiated by system-on-chips. Direct bonding is a mandatory to develop commonality in the rapid diffusion of copper atoms core technology that provides robust self- both tools and processes before ramping along the grain boundaries. Diffusion sealing for D2W stacking. It eliminates the up this technology to industrialization. cones are formed at the intersection of need for any underfill material. As shown these grain boundaries and the copper- in Figure 4, it enables stacking more than Characterization and Metallurgy to-copper interface, and spread until two die. CEMES-CNRS fills the tasks of a thermodynamically stable zig-zag Combining the technologies characterizing the bonding quality and structure is formed. developed within PROCEED and of analyzing previously unobserved The effect of grain orientation on the results from a prior project called changes that occur in the copper diffusion is being further investigated VERDI, which was focused on high- metallurgy during the annealing step. using a new TEM Automatic density TSV integration (diameter Compressive stresses or annealing steps Crystallographic Orientation Mapping 2-5µm) and ultra-thin Si wafers at intermediate temperatures are known system, purchased through the stacking (thickness 10-25µm), will to facilitate the assembly of two wafers PROCEED project. Figure 6 shows how covered with copper films. This this system is able to capture the various is a key step in creating stronger orientations present in the Cu-bonded bonds for a stack of various chips interface before and after the assembly. in 3D. However, the mechanisms that lead to the full bonding of Results the copper-to-copper interface • The pick-and-place equipment are not completely known. developed for this task was shown Investigating these mechanisms to meet the specifications and was an important part of the to perform well in particulate laboratory program. contamination control and Various forms of Transmission alignment accuracy. Electron Microscopy (TEM) • Significant progress was made Figure 4. Three die stacking sample with copper to copper were employed as the main in the die surface preparation bonding pads tools in this investigation. After process, with new and more effective allow development of a full process having annealed copper-covered wafer chemistries created. Additionally, integration flow for the next generation assemblies at temperatures of 100°, a specific adjustable dilution and of high-performance 3D system- 200°, 300° and 400°C, cross-sections distribution system was developed on-chips moving forward. This will were cut perpendicular to the bonding for surface treatment, which could be enable a wider range of applications in interface. They were thinned down to integrated into the final equipment.

20 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] Acknowledgements The PROCEED Minalogic project is a 2.4 million Euros, 24 months undertaking supported by French FUI (Fond Interministériel Unique) with the objective of demonstrating high placement accuracy (< 1µm) of chip to wafer structures by direct metallic bonding.

Figure 6. TEM-ACOM maps of the bonded copper to copper interface before (up) and after (down) direct bonding and annealing at 400°C. The differing colors relate to the different crystallographic orientations of the Gilbert Lecarpentier, SET, may be grains present on both sides of the interface contacted at [email protected]; • Bonding with the new equipment and of copper atoms along the grain Marc Legros, and Mayerling Martinez, new surface treatments was successful boundaries. CEMES-CNRS, may be contacted at in producing functional daisy chains [email protected] and mayemartinez@ with more than 10,000 contacts Conclusion yahoo.com; Alexis Farcy and Brigitte at a 7µm pitch, demonstrating the Project PROCEED has more than met Descouts, STMicroelectronics, may be capability of this approach. its goals. New equipment, materials, contacted at [email protected] and • A dedicated 3D test chip with skills and processes were combined to [email protected]; Emmanuel embedded active structures was demonstrate that high-density copper- Augendre and Thomas Signamarcheix, integrated following a full CMOS to-copper direct bonding is achievable CEA-LETI, may be contacted 65nm node process flow. and practical for 3D assembly, and [email protected] and • Observations of metallurgical has major advantages over older [email protected]; Vincent changes during annealing revealed approaches. The demonstrations were Lelièvre, and Aziz Ouerd, ALES, may previously unknown temperature a success and have opened the gates to be contacted at vincent.lelievre@ dependent changes in surface further progress in high-density direct airliquide.com and Aziz.OUERD@ structure by the rapid diffusion copper bonding of 3D assemblies. airliquide.com.

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 21 Laser Processing: A Robust Solution for Dicing Ultra-Thin Substrates By Kip Pettigrew, Matt Knowles and Michael Smith [ESI]

he incorporation of going through a myriad of materials step further, dicing techniques have increasingly thinner wafers that vary greatly in mechanical been developed that cleanly cut through Tis fundamental to the development properties. Brittle layers such as low-k various electronic stacks on a wafer, of next-generation 3D packages and materials and silicon nitride are easily the base substrate, and underlying electronic devices. Through silicon chipped and damaged. Thick die- films. Multiple wavelength types can vias (TSVs), stacked memory, attach films (DAF), which are used be used to hone a specific process but 2.5D and 3D interposers, MEMS to package die during the assembly for most applications described in this devices, system-in-package (SiP) process, can be viscous and tacky when article a 355nm laser was used. and advanced thermal management cut mechanically. Changes in the base Traditional laser processing moves a are requiring thinner substrates to substrates present an additional dicing pulsed laser beam across the substrate, meet increased electrical needs, challenge. Glass, ceramics and gallium ablating material as it goes. This smaller packaging requirements, and arsenide are examples of popular manner of laser processing is similar to increasingly complex designs. Silicon, substrates that are replacing silicon cutting a material with a saw. Slow laser the traditional base substrate for for many applications and present processing generates heat affected zones semiconductor and micro-fabrication, unique mechanical challenges to dice (HAZ) that induce stress in the substrate becomes increasingly fragile as its and machine. and subsequent layers. Much like stress thickness decreases making mechanical Improving wafer utilization, from mechanical processing, prolonged dicing more challenging. Besides the eliminating process steps and thermal stress can damage the electrical challenge of working with thinner minimizing costs are crucial for any stack, change material properties, and devices, there is a push to improve yield, electronics manufacturer to stay jeopardize structural integrity. develop increasingly complex stacks and competitive. Any discarded part of To avoid these thermal effects, better utilize wafer real estate all while a wafer could have accommodated a “zero overlap” technique was maintaining cost of ownership (CoO). To an additional die and brought in developed to remove material along a address these challenges, developments revenue. Not all devices have identical desired dicing path. This allows heat for laser processing techniques for laser- footprints and it becomes progressively to dissipate and thereby minimizes only dicing are underway. more challenging to singulate every thermal impact and induced stress. This die on a wafer while simultaneously method precisely places individual Dicing Challenges minimizing waste. pulses along a line at a high rate in As device wafer thickness decreases, such a way that pulses are never laid new challenges arise when dicing. Techniques for Laser Processing down adjacent to one another. Spacing Silicon, which is normally a rigid Laser processing involves using a the pulses also prevents energy losses material, becomes flexible. Below a specific wavelength of coherent light from laser interaction with ablated thickness of 50µm, a silicon wafer to ablate material in a bends like a piece of paper rather than controlled manner. This the rigid substrate most are accustomed type of processing has been to. Thinner wafers have a higher widely used for many years probability of generating significant in macro-scale drilling, cracks and cleaving from the smallest cutting, and engraving. of defects. Similarly, deflections in the As control systems and substrate during dicing induces stress optics have improved, that increases the likelihood of defects laser techniques have been and die failure. applied to sub-micron While substrate thickness is resolution machining such decreasing, the associated electronics as memory repair fuse and mechanical devices are becoming blowing, wafer & LED increasingly complex. Dicing a scribing, and wafer scoring. semiconductor product wafer requires Taking these processes a Figure 1. Laser Diced 50um, 75µm and 100µm silicon substrates

22 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] Laser dicing methods are not constrained to perpendicular dicing lanes. Hexagons, asymmetric device shapes, curved patterns, through holes and partial cuts are easily performed without cutting into adjacent devices or having to sacrifice wafer real estate. Examples of nontraditional dice shapes easily produced with laser dicing are Figure 3. Example of laser dicing through very shown in Figure 4. Hexagons are an dissimilar layers: 50µm silicon and organic die-attach easily repeatable pattern that better film conform to the rounded wafer edges. process. Parameters such as power, Similarly, using a mix of octagons Figure 2. Laser diced device and substrate wavelength (355nm), speed, focus and squares allows for two die to be material, and allows maximum power height, pulse rate and spot size (8µm produced at the same time and have a delivery to the target. 1/e2) are adjustable. As each layer flexible wafer footprint. Asymmetric Precision galvo-control enables of the device is diced, laser dicing patterns allow for a wider array of 1-2µm spot placement accuracy (relative parameters can be tailored to address layout options as well as the flexibility to other spots) at up to 4.5 m/sec. Laser the specific material requirements. to incorporate integral cooling dicing techniques have been perfected For example, a three stage recipe technologies to battle the thermal for wafers under 100µm in thickness, is the best approach to dice a stack challenges inherent with 3D designs. while cutting through a wide variety consisting of standard semiconductor The width of a dicing line, or kerf, of devices and films. Figures 1 and films and layers, a silicon substrate has historically been set by the width of 2 show cross sections of laser diced and a DAF. The delicate electrical the blades needed to dice the material 50µm blank substrates and a scribed components may be diced at lower without excessively damaging the device wafer respectively. power to better control the removal substrate. With laser dicing, the spot of thinner and fragile dielectrics and size is limited by optics and the space Material Selectivity metals. After the electrical stack, the needed to effectively eject ablated Selective processing and integrating power is increased to cut through the material from the dicing lane. Dicing new materials into electrical devices silicon with an adjusted pulse rate to kerf widths of ~20-30µm cut with is essential to new technology optimize throughput. Finally, when the micron resolution precision are easily development. However, while DAF is reached, dicing parameters can achieved when using a 355nm laser a material may have a desired be adjusted again to meet the material to singulate 50µm thick wafers. Thin engineering property, this benefit often specifics. One could go further to use dicing lines also free up additional real comes with additional processing multiple lasers at different focus heights estate to the wafer. As the number of challenges. This is commonly seen or spot sizes. The selectivity of the laser die and required dicing lanes increase, when developing processes including recipe’s parameters to different materials minimizing the kerf width allows for ceramics, glass, low-k materials, could then be changed to protect some more die to fit on each wafer. organic films, and rare materials materials and target others while such as diamond. Similarly, a device minimizing processing time. Figure 3 Working with Complex, SOI or containing differing materials with shows a cross section of a diced wafer Fragile Substrates drastically different properties creates with device layer, silicon, and DAF. MEMS dicing is challenging because the dicing challenge of not damaging both electrical and mechanical design are any single layer while still quickly Making the Most of Wafer Real Estate critical to producing the next generation cutting through the entire stack. Scribing and then cleaving silicon Dicing in stages has been the tried along the natural lattice structure and true method of dealing with is a common way to dice wafers. material complexity, but with thinner While cleaving works when dicing wafers, thicker electrical stacks, and the pure silicon, it becomes increasingly addition of viscous materials such as difficult with the addition of fragile DAF, a more versatile solution for all electrical stacks and patterned the layers simultaneously is necessary. features, and is limited to cross-wafer Laser-only dicing addresses a dicing and rectilinear dicing patterns. diverse material stack by shifting Semiconductor substrates, however, are the dicing parameters (power, speed, traditionally circular. Square die result Figure 4. Laser diced die patterns with 35µm dicing etc.) continuously throughout the in increased waste near the wafer edge. lanes

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 23 of devices. Many MEMS devices such There are several ways currently For wafers with a thickness greater than as gyroscopes and accelerometers have used to address the DBS weakening 50µm, specific device requirements such complex 3D structures that themselves in thin substrates either by annealing as non-rectangular die or mixed use need to be integrated into a 3D the die or by “healing” the areas where applications may still drive customers stack. Other devices, such as MEMS damage may have occurred. As part of to select laser processing over saws. As microphones, have fragile membranes the post laser dicing process, a short mentioned throughout this article, there that are easily ruptured. The laser’s XeF2 etch may be used to remove are advantages to both and ultimately lack of mechanical contact enables thermally stressed HAZ material and the requirements and materials of the processing on fragile substrates without improve overall die performance. XeF2 device stack must be considered to any significant jarring to the wafer. preferentially etches exposed silicon determine the best dicing option. The concept of dicing should not be and stressed areas. A post-etch chamber limited to through wafer processing. was integrated to the laser dicing tool to Conclusion Silicon-on-insulator (SOI) wafers are minimize processing time and maintain As devices become increasingly commonly used to build devices on a high throughput. complex and micro-fabrication becomes buried oxide layer. Traditionally, the Laser-diced wafers without any post more competitive, it is crucial to finished devices must be singulated processing have minimal chipping and continually develop new tools and using deep reactive ion etching somewhat lower DBS as compared to solutions to allow innovative designs (DRIE) before they are released from mechanical techniques, typically of to come to fruition. Laser dicing is a the buried oxide. This requires an order 250MPa. With the added XeF2 robust solution to the challenges of additional masking process, involving post processing, DBS over 500MPa are thin-wafer dicing, working on fragile expensive equipment on potentially easily achieved. substrates, maximizing wafer real delicate devices. Partial laser dicing estate and permitting the inherent through only the device layer of an Weighing the Pros and Cons creativity required to meet the needs of SOI wafer is a fast and maskless There are pros and cons to using a demanding electronics market. process that permits the releasing of laser processing that largely depend devices without additional lithography, on the devices being singulated. The Acknowledgements vacuums, or post processing. biggest limitation is the thickness that Special thanks to Daragh Finn, Jim For complex MEMS devices, laser one can dice quickly with a laser. As Dumestre, Chi-Cheng Lin, Bong Cho, processing has the advantage of being wafers get thinner, the speed at which David Lord and Jim O’ Brien of ESI’s able to cut on any plane parallel to the a traditional saw dices a wafer must semiconductor applications team for all wafer surface. Material can be removed decrease to minimize damage to the their work, help and experience. from the center of a recessed area by substrate. Conversely, the thicker the shifting the focus of the dicing beam, wafer, the more passes it takes a laser to Kenneth (Kip) Pettigrew, senior eliminating the need for a mask or dice completely through the substrate. marketing engineer, semiconductor complex 3D lithography. Holes can Evaluating silicon wafers, the CoO, products division, ESI, may be contacted be diced into the middle of a die at the and potential for wafers diced per hour, at [email protected]. Michael Smith. same time as the primary dicing lines, laser vs. saw dicing are competitive applications engineer, ESI, may be saving process steps and lead time. Step at a wafer thickness of 50µm with contacted at [email protected]. Matthew etching and generating through holes rectangular die, all other things being Knowles, senior product marketing in a device are common processes, equal. The general trend of this CoO vs. manager, ESI, may be contacted at especially in fluidic designs and wafer thickness is shown in Figure 5. [email protected]. integrated cooling solutions.

Maintaining Die Break Strength Die break strength (DBS) is commonly characterized using a three- point bending test. Chips and defects in the die result in faster fracture of the substrate and a lower DBS. Laser dicing, when running at high dicing speeds, can produce small defects in the substrate akin to mechanical dicing at high velocities. These defects lower the DBS of the die and must be addressed in post processing to eliminate this concern. Figure 5. Laser verses mechanical dicing Cost of ownership as a function of wafer thickness

24 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] Solder in the Age of 3D Semiconductor Assembly By Dr. Andy C. Mackie, Global Product Manager and Tae-Hyun Park, Country Sales Manager [Indium Corporation]

he cutting edge of the copper pillar and solder bump flip-chip metallurgy of the final reflowed joint. semiconductor packaging for the top 14 companies is showing The standard method of turning the Tindustry is seeing what is probably the an 18.6% annualized growth rate7 from often misshapen solder deposits into largest series of simultaneous changes 2009-2012, with growth in copper coplanar, hemispherical microbumps in both its assembly methodologies pillar as the main market driver. Table [Figure 1], is to use a semiconductor- and basic infrastructure since the move 1 shows several means of putting grade wafer bumping flux after the final from thermionic valves to silicon over solder onto underbump metallization resist-strip step, followed by cleaning. fifty years ago. The advent of 2.5D and (UBM) pads. The flux is applied to the wafer surface 3D assembly processes is accompanied One processor manufacturer like a photoresist by a spraying/ by significant process complexities dispensing process, Solder Application Method Common Usage caused by through silicon vias (TSVs), then “spun down” to thinned die, 450mm wafers, ever more Solder paste printing Wafer and substrate (SOP) produce the desired fragile interconnect-layer dielectrics, (paste type 5,6,7,8) bumping down to 125µm pitch thickness. For some and the criticality of doing all this while Flux print Wafer level CSP down to 0.3mm wafer bumping houses, maintaining acceptable yields. The and solder ball-drop pitch, and some wafer bumping the high-aspect ratio of relentless driver is the “price-elastic down to 80µm pitch microbumps on copper growth of the electronics industry” 1, the pillars has necessitated IBM / Suess C4-NP Wafer bumping down to 20µm basic principle behind Moore’s Law 2. some changes in the (liquid solder) pitch or less One common factor underlies these way wafer bumping changes: there must be reliable electrical Solder plating Wafer bumping down to 20µm fluxes are applied, interconnects between the devices. pitch or less making flux rheology It is becoming apparent that extant Table 1. Solder application methods a much more critical materials and processes are evolving announced that for many of their control parameter. to meet the challenges; providing multicore die, the I/O pitch will see Resin-based fluxes are essential for extensions of known quantities, rather a modest reduction from 180µm to high-melting alloys and have been than relying on the process engineer 165µm pitch for the foreseeable future, the traditional means of reflowing to implement yet one more change and will continue using standard flip- 90Pb/10Sn and 95Pb/5Sn solder amongst many. As has been pointed chip assembly processes. Meanwhile, bumps. With these alloys, even at out, “the essential process in [all] solder their portable products are already at the the very low oxygen levels used for joining is the chemical reaction between 40µm pitch node using copper pillars, wafer bumping flux reflow (usually

[substrate metallization] and tin to and will presumably shrink in pitch less than 10ppm O2) water-soluble flux form intermetallic compounds having a further into the future. chemistries remain difficult to clean. strong metallic bonding” 3. Copper pillars on wafer surfaces However, as “eutectic” (63Sn/37Pb) The focus of this paper is solder are almost always capped with and tin/silver (Sn/Ag) bumps have and flux usage in these more advanced “microbump” solder. Although there become prevalent, water-soluble fluxes technologies, with special focus are some instances in larger pitch have become the standard. on those processes where solder is applications (80µm and above) where Note that although there are known immediately adjacent to the die surface. pure tin (Sn) has been used as a instances where a reactive atmosphere As will be seen, despite competing gas- microbump solder, the most common approach may be used to reflow solder phase4 and solder-free5 processes, flux solder in this application is an off- bumps8, the limited capability of and solder are definitely not going away eutectic tin/silver (Sn/Ag) in the near term. alloy, which is most often applied by plating since it Flip-Chip Background is then just the final plated The history of flip-chip assembly layer in a sequence. The goes back to the earliest days of tape alloy target ranges from 1.5 automated bonding and the IBM C4 to 2.5% Ag, depending on 6 process . Market projections show that the plating process control Figure 1. Wafer-Bumping flux turns the misshapen solder deposits into flip-chip wafer starts for combined capability and the desired coplanar, hemispherical microbumps (Courtesy of Amkor)

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 25 the process to has led to significant solids content and can be easily resistance to adoption for finer-pitch cleaned off, even with tighter pitch wafer bumping applications. Just some constraints. By using a heated of the technical issues reported are9: spray nozzle, a higher solids- • “Soccer ball” sphere shape defects loading flux can be applied with • Oxides and organic/residual a lower viscosity, yet on cooling photoresist contamination is viscous enough to prevent drift • Inability to remove wafer probe- and skew of larger die. marks 2. Dipping the solder bumps on Each of these defects can, of course, the chip into a flat reservoir of play a role in subsequent voiding during more viscous flux of a controlled flip-chip assembly. depth is more suited to larger Figure 3 . One of the ways in which TC bonding is being implemented for D2D assembly (multicore) die. Improvements in Flip-Chips and Interposers process control of doctor-blading The reflow process is carried out in a So-called 2.5D (interposer-based and dipping processes, along controlled atmosphere using a Japanese assembly) is an enabling technology for with specialized flux chemistries, thermocompression bonding tool, and the increasingly fragile ultra low-k (ULK) mean that a stable dip depth down cleaning with deionized water and an dielectric materials in the interconnect to as low as 10µm can now be added cleaning chemistry to reduce layer on the chip surface. The interposer consistently guaranteed for rotary surface tension. essentially replaces the use of capillary systems. The subsequent reflow The move from standard oven-based underfills as a primary stress reliever for process is carried out in a reflow flip-chip reflow processes to TCB chips fabricated with sub-32nm devices. oven at less than 50ppm oxygen. for 3D assembly is based on several However, underfill will probably still By combining processes 1 and 2, it different factors, but the primary continue as an added reliability enhancer is possible to get a flip-chip assembly difference is the issue of surface tension in the chip-interposer stack up. The process that avoids intermittent contact of small solder bumps. The addition of interposer is usually either itself made of non-wet (CNW) issues, has zero die pressure to the reflow bonding process silicon, or a glass/ceramic material with a skew, and is insensitive to incomplete ensures elimination of “head in pillow”- CTE close to that of silicon. By matching spray flux wet-out onto varying like defects, or CNW. CTEs, the interposer reduces the stress substrate photoresist surfaces. Figure 3 shows just one of the many on the microbump interconnects. The Although uncommon, one large different ways in which TC bonding is processes used for forming low-oxide, processor manufacturer even uses a being implemented for D2D assembly. coplanar solder bumps on interposers high-viscosity flux: printing it directly The TC bonding head temperature setting are exactly the same as those used for onto the substrate before flip-chip attach is usually just above the melting point of forming solder bumps on wafers, with and reflow. the solder, so minimal brittle tin/copper plating being predominant. intermetallics are formed, and solder joint Copper-Pillar Flip-Chip and Die- starvation caused by solder wetting up and Standard Flip-Chip Attach Processes Bonding down the copper pillars is also minimized. In flip-chip die-attach processes, two Die to die (D2D) is the preferred The bonding pressure also has to be kinds of flux may be used (Figure 2): assembly process and is capable of optimized to prevent CNW issues (too low 1. A low viscosity flux sprayed or high-yield manufacturing. The process pressure) and solder “squeeze out” (too jetted onto the substrate is very uses either standard flip-chip assembly high pressure)4. effective for smaller die with high and reflow, or thermocompression As I/O pitches decrease below 40µm I/O counts, as long as wetting bonding (TCB). The term TCB as (for D2D and D2W applications), cleaning onto the substrate is consistent. applied to flip-chip bonding is These fluxes typically have low relatively new10, although the tooling has been available for a number of years. As an example of the extensibility of current processes, one Taiwanese OSAT has established a 40µm pitch microbump D2D process using a dipped flip-chip flux. The keys to the success of the flux are the flux rheology and the Figure 2 . In flip-chip die-attach processes, two types solubility of the post-reflow Figure 4 . Flux applied in standard flip-chip, 2.5D (interposer) and of flux may be used residue in deionized water. future 3D (memory cube on logic) assembly

26 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] out flux from between the stacked die imec has stated that by 2015, stacked (interposer) and future 3D (memory becomes impractical for all but the wafers, such as those used in memory cube on logic) assembly. smallest die. Capillary underfill, as cube applications, will have W2W well as other types of non-conductive clearances of only 500nm (0.5µm). 3D in Power Devices underfilling approaches11, will still be Thermal issues will be the primary Decades ago, power electronics needed to ensure reliable electrical concern here, and alternatives are consisted entirely of discrete components, interconnects into the foreseeable future. already being planned.13 Figure 4 with the die adhesive-bonded or soldered Any flux residues must either encapsulate shows the way that flux may be used to the main leadframe backplane, and the joint and provide added joint strength and applied in standard flip-chip, 2.5D wire bonds to the top surface. The solder (epoxy fluxes), or be compatible with subsequent underfill processes. For standard no-clean fluxes, the presence of even ultralow (3-4%) residue (based on initial flux mass) levels may be enough to block capillary underfill flow, and so 30µm pitch and less 2.5D applications are moving to either near zero residue, <2% (NZR) no-clean dipping or spraying fluxes, or dipping epoxy fluxes.

D2W Die to wafer (D2W) assembly for 3D heterogeneous integration may also benefit from water-soluble fluxes, although the presence of adjacent die on the surface makes both cleaning and underfilling more complex. D2W processing is a less common assembly method, a fact that may be related to subsequent difficulties related to handling and dicing of the thinned wafer.

W2W The current understanding is that wafer-to-wafer (W2W) bonding will be used primarily to manufacture the multi- stack die for so-called “memory cubes”, since the die are all the same size. The standard W2W bonding processes for TSV stacking are:12 • Copper / Copper (high temperature) • Copper / Copper oxide / Copper (moderate temperature) • Copper / Tin / Copper (much lower temperature) The first two processes are solid-state diffusion bonding processes. The last of the three (a transient liquid phase intermetallic process) is a target for a no-clean flux-based process using a jetting, dipping, or similar deposition technology. Cleaning materials out from between the bonded wafers is clearly impossible for standard cleaning processes, although supercritical fluid approaches may be feasible.

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 27 used in these instances has typically been 2. http://arstechnica.com/hardware/ either a clean, oxide-free (SSDA) wire news/2008/09/moore.ars that is applied by a special machine that 3. King-Ning Tu “Solder Joint feeds the wire onto the heated leadframe Reliability” Publ. Springer, 2007, p. 1 in a forming gas (H2/N2) atmosphere, or 4. Zhan et al. “Development of Fluxless a dispensed solder paste that is also often Chip-on-Wafer Bonding Process for reflowed in forming gas or nitrogen, then 3DIC Chip Stacking with 30micron Pitch cleaned. Low cost, high temperature- Lead-Free Solder Micro Bumps and tolerance and reliability are key factors Reliability Characterization” ECTC 2011 for the interconnect material, which 5. M. Knoerr and A. Schletz, “Power explains the continuing usage of solder Figure 5 . Power components rely on thin die and SemiconductorJoining through Sintering here. flat clips for interconnect Silver Nanoparticles” CIPS Conference 2010 Power electronics in the 2010s Product Quality 6. K. Gilleo “Flip-Chips Tutorial 6” also includes LED's, GaN die and Finally, OSATs and others engaged in http://www.flipchips.com/tutorial06.html IGBT modules, with different form semiconductor packaging are becoming 7. J. Vardaman et al., “2010 Flip- factors, and changes such as multiple increasingly aware that product quality Chip and WLP: Market Projections thick aluminum wire bonds (and even is a key part of supplier qualification for and New Developments”, Techsearch flexible circuitry) to the top surface. semiconductor-grade solder paste and International Report Meanwhile, the electrical interconnect fluxes. There are myriad failure modes, 8. Wei Lin and Y. C. Lee: “Study of requirements remain fundamentally but the primary issue is one of correlating Fluxless Soldering Using Formic Acid the same, but with an increasing drive the measured quality parameters of Vapor”, IEEE Transactions on Advanced towards increased service life; higher the material to the final functionality, Packaging, Vol. 22, No. 4, November 1999 operational temperatures (200°C is now especially in emerging applications such 9. Data from three separate Taiwanese becoming a need); and the corollary of as 2.5D and 3D interconnect. Some of customers’ experiences: further details more extreme thermal cycling. the more critical issues here are: were shared with author in confidence By their very nature, since many • Flux and paste rheology 10. http://blogs.indium.com/blog/ power semiconductor devices are • Solder powder particle size semiconductor-and-power-semi- designed to pass current in the Z-axis distribution assembly/thermocompression-bonding- through the chip, it has always been • Halogen-content15 for-microbump-flip-chip feasible to stack these devices on each • Surface insulation resistance(SIR) 11. M. Kelly and W. Do, “3D Packages other, using a thin leadframe interposer and electrochemical migration with TSV Silicon Interposers”, TP-11, “clip”. Such packages are truly 3D • “Particles” – gel, crystals, foreign iMAPS Arizona, February 2011 chip stacks, per the JEDEC definition.14 matter and so on 12. P. Garrou, “3D IC Integration: Status The thinner packages eliminate wire • Controlled (low and ultralow) alpha and Overview” PDC, iMAPS Arizona, bonds: getting rid wire-loops, and also particle emissions February 2011 significantly increasing the current- Both users and suppliers also face 13. http://www.electroiq.com/blogs/ carrying capacity. the formidable issue of an absence of insights_from_leading_edge/2011/09/ Power management devices in portable applications-relevant test methods for iftle-66-3m-ibm-seek-to-improve- electronics need to be of small and low many of the above properties. It is usually thermal-underfills-tsmc-in-back-end- profile form factor as much as their digital assumed by both sets of parties that packaging-again.html cousins. Power components therefore “standard” (often assumed to be IPC16) 14. JEDEC Publication JEP158 “3D also rely on thinned die and the use of standards and test methods, designed Chip-Stack with Through Silicon flat clips (Figure 5) rather than “bulky” primarily for SMT assembly materials, Vias…” p. 4 thermosonic ball and wedge wirebonds. are extensible to semiconductors. 15. JEDEC/ECA Joint Standard: JS- The use of clips also eliminates extra Increasingly, they are not. 709 “Defining Low-Halogen Passives process steps by combining all reflow In the midst of this uncertainty, it is and Solid State Devices (Removal of in a single process. Solder pastes with therefore critical to be able to partner BFR/CFR/PVC)” – August 2011, but residues compatible with overmolding with suppliers who are leading the currently under revision. compounds have been used in clip- industry in development of testing 16. IPC “The Association Connecting bonding applications, so that even the methodologies, and who can truly supply Electronics Industries”: http://www.ipc.org residue cleaning step can be eliminated. “semiconductor grade” materials. Lead-free (Pb-free) alloy development Andy C Mackie, PhD, Global Product is of critical concern and we are nearing References Manager, Semiconductor and completion of a major project on Pb- 1. W. Bottoms: Presentation “Roadmaps and Advanced Assembly Materials Indium free solder wire for automotive stacked- the Revolution in Packaging”, MEPTEC Corporation, may be contacted at die power semiconductor products. Roadmap Packaging Meeting 2010, p. 22 [email protected]

28 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] "Electronics Consulting Network" (480) 215-2654 www.aztechdirect.com Submit all Directory inquiries and updates to [email protected] International Directory of Solder and Flux Suppliers Directory data was compiled from company inputs and/or website search and may not be current or all-inclusive as of the date of publication. COMPANY FLUX SOLDER BGA/CSP SOLDER HEADQUARTERS PRODUCTS PRODUCTS SPHERES

Company Chemistries Alloys Specifications Street Address Halide Free (HF) Leaded (PB), Lead Free (LF) Alloys City, State, Country No Clean (NC) Low Alpha (LA) Sphere Diameter Telephone Rosin (R) Forms Diameter Tolerance Website Rosin, Activated (RA) Anode (A), Bar (B), Foil (F) Melting Point Rosin, Mildly Activated (RMA) Paste (Pa), Powder (Po) VOC Free (VF) Preform (Pr), Sphere (S) CM = Contact Manufacturer Water Soluble (WS) Wire - Cored (CW), Solid (SW)

AIM HF, NC PB, LF Alloys: PB, LF 9100 Henri Bourassa Est. RA, RMA A, B, F, Pa, Po, Pr, S Diameter: CM Montreal, Quebec H1E 2S4, Canada VF, WS CW, SW Tolerance: CM Tel: +1-514-494-2000 Melting Point: 138 - 356°C www.aimsolder.com

AMTECH ( Mfg. by SMT International, LLC) HF, NC PB, LF Alloys: PB, LF 500 Main Street, Suite 18, P.O. Box 989 RA, RMA B, Pa, Po, Pr, S Diameter: 3 - 45 mils Deep River, CT 06417 VF, WS CW Tolerance: CM Tel: +1-860-526-8300 Other Melting Point: CM www.amtechsolder.com

BALVER ZINN Josef Jost GmbH & Co. KG NC PB, LF Alloys: CM Blintroper Weg 11 RMA A, B, F, Pa, Po, Pr, S Diameter: CM 58802 Balve, Germany VF, WS CW, SW Tolerance: CM Tel: +49-23-759150 Melting Point: CM www.balverzinn.com

Bow Electronic Solders (Div. of Kaydon Corp.) HF, NC PB, LF Alloys: PB, LF, Metal Core, Cu 1 Crossman Road R, RA, RMA B, F, Pa, Pr, S Diameter: 1 mil Min. Sayreville, NJ 08872 VF, WS CW Tolerance: +/-0.2 mils Tel: +1-732-316-2100 Melting Point: CM www.solders.com

Cookson Electronics, Semiconductor Products HF, NC PB, LF Alloys: PB, LF 3950 Johns Creek Court, Suite 300 WS Pa, S Diameter: 10 - 35 mils Suwanee, GA 30024 Tolerance: +/-0.5, 1.0 mil Tel: +1-678-475-6900 Melting Point: 179 - 302°C www.cooksonsemi.com

DKL Metals Ltd. HF, NC Pa, S Avontoun Works, Linlithgow RA, RMA B, Pa West Lothian, Scotland EH49 6QD VF, WS CW, SW Tel: +44-1506-847710 www.dklmetals.co.uk

EasySpheres WS PB, LF Alloys: PB, LF 12675 Danielson Court, Suite 403 S Diameter: 0.2 - 1.0 mm Poway, CA 92064 Tolerance: CM Tel: +1-858-486-4068 Melting Point: 179 - 302°C www.easyspheres.com

Fukuda Metal Foil & Powder Co., Ltd. LF Alloys: LF, Cu Core 20, Nakatomi-cho, Nishinoyama, Yamashina-ku Po Diameter: 80 - 760 um Kyoto 607-8305, Japan S Tolerance: +/-10, 20 um Tel: +81-75-593-1590 Melting Point: 190 - 227°C www.fukuda-kyoto.co.jp

How Tsen Int'l Electronics Metal Co., Ltd. PB, LF Alloys: PB, LF No. 12, Ln. 130, Sec. 2, Zhung San E. Rd., Sin Wu S Diameter: 70 - 889 um Taoyuan, 327 Taiwan Tolerance: +/-5, 10, 15, 20 um Tel: +886-3-477-7517 Melting Point: 133 - 227°C www.howtsen.com

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 29 "Electronics Consulting Network" (480) 215-2654 www.aztechdirect.com Submit all Directory inquiries and updates to [email protected] International Directory of Solder and Flux Suppliers Directory data was compiled from company inputs and/or website search and may not be current or all-inclusive as of the date of publication. COMPANY FLUX SOLDER BGA/CSP SOLDER HEADQUARTERS PRODUCTS PRODUCTS SPHERES

Company Chemistries Alloys Specifications Street Address Halide Free (HF) Leaded (PB), Lead Free (LF) Alloys City, State, Country No Clean (NC) Low Alpha (LA) Sphere Diameter Telephone Rosin (R) Forms Diameter Tolerance Website Rosin, Activated (RA) Anode (A), Bar (B), Foil (F) Melting Point Rosin, Mildly Activated (RMA) Paste (Pa), Powder (Po) VOC Free (VF) Preform (Pr), Sphere (S) CM = Contact Manufacturer Water Soluble (WS) Wire - Cored (CW), Solid (SW)

Indium Corporation HF, NC PB, LF Alloys: PB, LF 34 Robinson Road R, RA, RMA B, F, Pa, Pr, S Diameter: 0.1 - 1.27 mm Clinton, NY 13323 VF, WS CW, SW Tolerance: +/-10, 15, 20 um Tel: +1-315-853-4900 Melting Point: 183 - 302°C www.indium.com

Kester, Inc. (an Illinois Tool Works Co.) HF, NC PB, LF 800 West Thorndale Avenue RA, RMA B, Pa, Pr Itasca, IL 60143 VF, WS CW, SW Tel: +1-630-616-4000 www.kester.com

Nihon Superior Co., Ltd. HF, NC PB, LF Alloys: PB, LF NS Bldg. 1-16-15 Esaka-cho, Suita City RMA A, B, Pa, Pr, S Diameter: 0.1 - 0.76 mm Osaka 564-0063, Japan WS CW, SW Tolerance: +/-5, 10, 20 um Tel: +81-6-6380-1121 Melting Point: CM www.nihonsuperior.co.jp

P. Kay Metal, Inc. HF, NC PB, LF 2448 E. 25th Street R, RA, RMA B Los Angeles, CA 90058 VF, WS CW, SW Tel: +1-323-585-5058 www.pkaymetal.com

Pure Technologies PB, LF, LA 177 U.S. Hwy 1, Suite 306 A, F Tequesta, FL 33469 Po, Other Tel: +1-404-964-3791 www.puretechnologies.com

Qualitek International, Inc. HF, NC PB, LF Alloys: PB, LF 315 Fairbank Street RA, RMA B, Pa, Po, S Diameter: 10 - 35 mil Addison, IL 60101 VF, WS CW, SW Tolerance: +/-0.5 - 1.0 mil Tel: +1-630-628-8083 Melting Point: 183 - 302°C www.qualitek.com

Senju Metal Industry Co., Ltd. HF PB, LF Alloys: PB, LF, Cu or Ag Core Senju Hashido-cho 23, Adachi-ku RA, RMA B, Pa, Pr, S Diameter: 0.02 - 0.76 mm Tokyo 120-8555, Japan WS CW, SW Tolerance: +/-3 - 20 um Tel: +81-3-3888-5151 Melting Point: 183 - 302°C www.senju-m.co.jp

30 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] Test Improvement via Electroless Plating By Terence Collier [CVinc.]

luminum die pads will of pad material in the X and Y direction. always lead to yield loss. Just like stepping in mud, smearing AIts inevitable. Aluminum pads form does not displace all the material in natural oxides that are accelerated by the path of penetration. Therefore, a fab and assembly processes. Stick a combination of cantilever and vertical piece of fresh aluminum in oxygen and probing is a good solution, but probes it will quickly grow 20Å-50Å of Al(O) are costly, and there is still some in some form or fashion. Add a little yield loss at probe and more yield fluorine from a plasma asher and it will loss at assembly due to additional saw grow around 250Å to 500Å. Place it in corrosion. So how does one completely the wafer saw and you might find up to eliminate the issue of bond pad 1000Å. If one is not careful, electrically corrosion and mitigate the yield loss conductive aluminum might not be minimized optimum electrical test? detected until 150Å to 200Å understand It is important to first identify the Figure 2. Optical image verifies that Al (white) is fab processing conditions. root cause, then review the process sparse and that there is Fluorine corrosion regrowth Depending on which probe constraints and propose a solution. The in the probe mark technology is chosen, it might be solution should not add more cost to the the corrosion that affixes to the probe difficult to achieve yields that reflect wafer than the yield loss, or additional needles leads to increased probe yield 85% of known good die (KGD). cycle time gained with reprobe of wafers loss as this material is difficult to There are probe technologies that use (reprobe will be explained later). The remove from the probe needles as well cantilevers and others with straight/ solution should be easy to implement as the bond pads. blunted needles. Cantilever probes and not impact the fit, form, or function scrape across the pad, removing the top of the product. Most fabs do not wish Process Constraints contamination layer of the pad to make to make any changes that will lead to What are the constraints? The fab is electrical contact with the subsurface requalification (internally or by the not going to change the fluorine etch gas. electrically conductive aluminum customer). Requalification of product is Improving yield requires removal of the both timely and expensive. Even corrosion layer without interfering with changing probe technology can probing or requiring new qualifications lead to requalification since pad in fabrication or assembly. So the process parameters can change (probe constraints are that the fluorine etch marks “damage” the pad and gas will not be changed and the probe change the way wirebonds stick technologies will not be modified (or to the pads). cannot be modified). As long as fluorine is present, the corrosion layer will Figure 1. Example of a cantilever probe Root Cause continue to grow (Figure 3). ( Figure 1). This displacement As stated earlier, corrosion on the technology can damage pads and the pads begins in fab processing (Figure 2). under lying structures. There is also a One of the last stages is die passivation limit on the pad size and spacing with with protective oxide (nitride, oxide or cantilever technology. oxynitride). That oxide is opened with Vertical probes minimize the scraping fluorine plasma, which imbeds itself motion and allow for smaller pad into the aluminum metal matrix. The size and pitch. Whereas cantilever fluorine serves as a catalyst to promote probing occurs primarily in the X-Y accelerated bond pad corrosion. Instead direction with some Z travel, most of of a typical 50Å corrosion layer of the travel with vertical probing is in oxides, the thickness can grow to a the Z-direction. Unfortunately, vertical spongy layer up to 500Å. At this point, Figure 3. Notice the area under the curve shows technology relies on probe displacement probing proves difficult. Removal of more OF corrosion (oxyfluoride) than pure aluminum

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 31 Contact resistance (CRES) is intermetallics, causing mechanical stress chemically bonded, fresh metal layers directly related to the degree of bond on the silicon that leads to fracturing that are robust and oxide-free. pad oxidation, contamination, and and chipping (failures) in the die. Since Since fabs are unlikely to change corrosion. Reducing CRES improves the oxides and corrosion products are the aluminum metal or etch gas, both assembly and test yield. With not conductive but highly resistive, ENIG/ENIPIG provides the best high CRES, false failures occur during removal is the process improvement alternatives. Added benefits are not testing as probe needles come in contact that is sought. just at test. With the NiAu layer, with non-conductive CRES layers. In some instances, aluminum can wirebond is also improved, which Penetrating this CRES layer requires be ashed to remove oxides with argon increases back-end assembly yield. But higher force on the probe needles, plasma or etched with acids/bases to electroless processes are not without risking damage to both die and the remove the corrosion layers. Layers their drawbacks. One problem with test hardware. Substituting the CRES can also be etched with oxide-only electroless finishes involves shorting layer with an alternative material that etchants such as BPS100 from Air of closely spaced bond pads during the is highly conductive and inert (non- Products. Ashing is time consuming plating process. reactive), such as gold, could prove and can damage the die. Etching with beneficial. Unlike other metals, gold chemicals other than BPS100 can etch Wafer Level Test does not oxidize over time or reoxidize too much metal. BPS will etch only the Earlier we stated the improvement like aluminum layers do. oxide and is a good solution. But even cannot cost more than the time at retest BPS100 is only good for a of couple and overall process cost of test or Solutions weeks, since aluminum will regrow its cleaning to improve test. Typically, a One solution is to change the pad native oxide in time. Once the wafers wafer probe has a first pass test on all metal structure, but not the aluminum progress to dicing and are exposed to die for opens and shorts. This quick test since that would be a critical change DI water, other process improvements can provide an expedited pass/fail test in technology. Hundreds of cycle runs are required since DI water is a known without the complete parametric test and and requalification of almost every fab corrosive agent on aluminum. associated cycle time. Once the opens/ process currently in production would short test is complete, full parametric be required. While copper is being The Benefits of ENIG test is performed. At some point during used in bond pad metallization, the One other improvement gaining parametric testing, the probe needles primary pad metal is still aluminum. a lot of attention for improving have to be cleaned due to contract Most fabs and processes are not test and assembly yield involves resistance (combination of dirty probe going to switch from aluminum on replacing a portion of the aluminum needles and wafer CRES). Parametric the bulk of their processes any time layer using electroless nickel plus probing resumes at some interval prior too soon. Changing the aluminum immersion gold (ENIG). A number of to cyclic cleaning. When the parametric metal would essentially shut down the die suppliers are migrating towards testing is complete, the probe needles semiconductor industry. However, there electroless metal finishes on bond are cleaned once again, followed by are process “enhancements” that can be pads. Finishes of electroless nickel retest of previously failed open/short implemented to eliminate or minimize followed by immersion gold or units. Those units that pass are then the corrosion layer. Effectiveness varies palladium + immersion gold (ENIG tested for full functionality (parametric). by process. In some cases, only a short and ENIPIG) improve both test and On a 300mm wafer, this cleaning and term gain is realized but that gain might assembly yields, as well as long-term retest can add up to hours per wafer lot. be significant for various operations. reliability (Figure 4). As part of the At hundreds of dollars/hour for test time electroless processes, the top layers and thousands of dollars per test card, Protecting the Pads of aluminum, aluminum oxides, and eliminating corrosion on the bond pad Protecting the aluminum pads with a other aluminum corrosion by-products is critical. Also remember that every noble metal, such as gold, would be a are removed and replaced with strong, good die is not recovered. In other benefit. Since gold pads typically have words, false failures cause good die to no oxide, CRES goes down significantly be scrapped. This yield loss can cost (probe tips can still have oxide), companies millions of dollars. probe force is minimize and test yield Adding an ENIG process must cost increases. less than retest, the reduction in life of One might ask, why not deliver probe cards due to excess cleaning, and die with the gold layer already on the the loss in profit of false failures. And it aluminum pad? Unfortunately, CMOS does. ENIG can be as cheap as tens of wafer fab processes don’t allow gold dollars per wafer. This cost per wafer to be used in the same facility as for ENIG is greatly offset just by the silicon. Mixing the two can create bad Figure 4. 8µm ENIG on Al pads cycle time of cleaning probe cards.

32 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] The advantage of ENIG over standard electroplating is that ENIG is a maskless process. Electroless finishes adhere only to the target metals on the die, thus eliminating the time and cost of creating and exposing masks to pattern the deposit. The increasing cost of gold also gives electroless finishes a growing cost over conventional sputtering and plating for typical electrolytic finishes. Figure 5. NiAu pillars grown in an aluminum island NiAu island (Figure 5) can be created in The Downside to ENIG the middle of the pad with the aluminum The major problem with electroless serving as a solder barrier. finishes, shared with electrolytic plated finishes, is that the deposited Summary layers grow wider at the same rate This paper has identified the as they grow higher. The result is a root cause of bond pad corrosion mushroom shape over the target area. beginning in the wafer fab. Using Pads with tight pitch will short. This fluorine etchants to open windows in is a limitation for tightly packed bond the passivation over the aluminum pads at a time when closer packing is a pads leaves residual fluorine in the major goal. The present method to work aluminum matrix. This incorporated around this is depositing and curing fluorine accelerates corrosion and organic insulators such as polyimide Al(O) growth leading to high contact (PI) or polybenzoazole (PBO) prior resistance (CRES). High CRES to electroless processing. The organic contributes to poor probing including insulators, typically 4um thick, provide reprobe/retest, reduces life on probe the isolation and barrier to prevent hardware and false failures of KGD. mushroom shorts during electroless As discussed earlier, the fluorine plating. A 2um layer of Ni can then be etch will not be eliminated, thus the plated on the bond pads. CRES problem needs to be addressed The added cycle time and cost of with other processing. Chemical PBO/PI processing almost eliminates etching and plasma were introduced as the benefits of ENIG processing. intermediate solutions. To for longer PBO/PI materials are not cheap. PBO/ term improvement, ENIG and ENIPIG PI processing may include up to two were introduced as solutions. Electroless addition days of cycle time. PBO and processing removes the surface PI also increase mechanical stress, aluminum and its corrosion layers are which can lead to electro-mechanical replaced by a layer of nickel followed failures, particularly on thinned by a more robust and noble gold layer. die. A further drawback is the high Probing on gold is much more robust, processing temperatures required for yielding improvements at test and also curing the PBO and PI, approaching in the final assembly processing. 375°C on some materials. The To overcome the issue of closely associated stresses as a result of spaced pads there are alternatives to temperatures and polyimide raise mitigate shorting between the pads. concerns for test failures that could CVInc has identified processed that mitigate any process improvements. don’t require PI/PBO processing To avoid those costs and problems, a assuring a good cost effective solution process replacing the PBO/PI approach, with no increases in cycle time for with significant reductions in cycle time ENIG processing. and cost is required. A process has been demonstrated up to 10um nickel thickness Terence Q. Collier, Founder and CEO, without bridging to adjacent pads. This CVINC, may be contacted at tqcollier@ process also allows pad size reduction. A covinc.com.

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 33 How to Dice Fragile MEMS Devices By Alissa M. Fitzgerald, Ph.D. and Brent M. Huigens [AMFitzgerald & Associates]

n the world of micro- electromechanical systems I[MEMS],silicon wafer processing is used to create micro-mechanical structures that have a wide variety of functions depending on their size and shape. To function as a sensor or actuator, a MEMS device must have a moving part; generally a cantilevered or suspended beam or plate. Microfluidic chips, while structurally robust, have narrow, meandering channels and Figure 1. Examples of fragile MEMS structures which can easily be damaged by dicing slurry and grit. Left: A reservoirs or hidden cavities that must micro-cantilever. Right: Array of electrostatically actuated pixels remain free of contaminants. All of these delicate features make MEMS wafers very tricky to dice. Traditional wafer sawing is a violent, messy process. A high-speed diamond grit wheel makes orthogonal cutting passes on the wafer, while bathed generously with water to keep the wafer and cutting wheel from overheating. The wheel literally grinds its way through the silicon like a more sophisticated version of the mason’s tile saw. At the end of the process, the diced wafer is Figure 2. Left: Stealth dicing uses a focused infrared laser beam to locally melt silicon. Right: Micrograph of a completely covered with a slurry of fine chip edge which reveals the multiple laser passes silicon grit which must be washed off. wafer with a diamond scribe and then Stealth Dicing and How it Works Engineers have devised clever tricks taking advantage of crystal planes to In the last 7 years, a new technology to protect their MEMS devices during snap the die apart. Any misalignment called "stealth" dicing* has emerged.1 sawing, most of which are manual and of the scribe line with the crystal plane, In stealth dicing, an infrared laser beam don’t scale well for volume production. however, would cause the resulting crack is focused to an ~2µm spot within the To protect fragile suspended mechanical to run through the die and destroy it. depth of the silicon wafer and scanned structures, or to keep grit out of narrow Engineers have also resorted to along the dicing lanes. Focused heating areas (Figure 1), engineers might flood using deep reactive ion etch (DRIE) from the laser creates highly localized the wafer with photoresist or wax to fix to singulate wafers. Although this is and brief melting, transforming crystal the parts temporarily and later dissolve effective, it is an order magnitude more silicon into flawed polycrystalline silicon the photoresist in solvents. For wafers expensive process step. As a last resort, surrounded by a field of concentrated with cavities or complex microfluidics the MEMS device might be designed stress.2 The laser is sequentially focused that might get clogged with slurry, heat/ such that it could be diced while still at different depths in the wafer, so that UV release tapes might be applied to monolithic, and then a lower-level a vertical plane of polysilicon is formed the top of the wafer before dicing to sacrificial material layer would be in the dicing lane within the thickness of prevent slurry from entering. After etched away post-dicing to release the the wafer (Figure 2). In striking contrast dicing, the protective tape must be delicate MEMS structure. In some cases, to traditional laser cutting, where the manually removed from each chip, such a release step can be performed laser intensely heats the surface of the which can damage fragile features while the wafer is still attached to dicing wafer, burns its way through, and leaves due to residual adhesion and/or high tape, but for many etch chemistries, the behind slag and rough edges, stealth electrostatic forces. Scribe and break chips must be removed from the tape dicing leaves no visible marks on the is a tecnique that involves scoring the and processed individually. wafer's outer surface.

34 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] After laser scanning, gentle as well as unusual chip shapes, such as needed to program the laser path for mechanical tension, created by radially hexagons (Figure 4). Finally, because each dicing pattern and to tune the laser stretching the dicing tape to which stealth dicing tools are outfitted with spot for wafer thickness and impurities. the wafer has been mounted, will infrared optics, it is possible to align the Stealth dicing service providers will subsequently cause the silicon wafer laser path to either a front or a backside charge NRE for this setup time, which to fracture. Because the polysilicon is wafer pattern. This enables the wafer makes it less economical for small under stress and substantially weaker to be placed face down against the tape wafer batches. than the surrounding crystalline silicon, and still achieve good alignment. These added costs should be carefully the wafer separates cleanly along weighed against factors such as speed, the path that was swept by the laser. Limitations throughput, handling and die yield. Beautifully cleaved die are produced At the moment, stealth dicing may In the case of fragile MEMS devices, stealth dicing is almost always worth its extra expense.

Conclusions Stealth dicing technology eliminates a problematic and yield- killing step for many types of MEMS devices. At our company, we have used stealth dicing to singulate chips of electrostatic actuators, cantilevers, thin membranes and narrow microfluidic channels with great success. Stealth dicing is a superior Figure 3. Stealth dicing enables non-Manhattan wafer layouts. Left: Traditional sawing requires alignment of solution, eliminating the many all dicing lanes. Right: Dicing lanes can be staggered to maximize die per wafer inefficient and manual tricks that with minimal kerf loss, no grit and no must otherwise be used to safeguard chipping. The tape can be kept in its MEMS during traditional wafer expanded state so that the die may be sawing. As stealth dicing technology easily plucked by machine or by hand. becomes more widely known and utilized, cost will decrease. With Advantages time, we fully expect stealth dicing Stealth dicing offers significant to become the de facto dicing method advantages. The complete elimination of for fragile MEMS devices. the vibration, liquids and grit associated with traditional sawing is very attractive, *a term coined by Hamamatsu Photonics if not essential, for dicing of most types of MEMS. But stealth has much to offer References any silicon wafer-based technology. 1. F. Fukuyo et al., "Stealth Dicing Because a laser is used instead of a saw Figure 4. Unusual die shapes are possible with Technology and Applications", blade, dicing lanes can be shrunk from stealth dicing Proceedings of the 6th the typical 100µm down to only 10µm. only be used on silicon wafers. The laser Symposium on Laser Precision For wafers with small die, switching to path must be transparent to infrared light, Microfabrication(LPM2005), (2005). stealth dicing will enable more die per so this means that the dicing lanes must 2. E. Ohmura et al., "Internal modified- wafer by recovering space once needed be free of oxides, nitrides and any metals. layer formation mechanism into for dicing lanes. Bonded wafers may not be fully diced silicon with nanosecond laser", Journal Stealth dicing also accommodates by stealth, although hybrid approaches of Achievements in Materials and complex layouts and unusual die shapes. (sawing through a top wafer, followed Manufacturing Engineering 17, 381(2006). Traditional sawing is rectilinear, so by stealth) are certainly possible. Dicing chips must be in Manhattan grid format. lanes must also be relatively smooth, to Alissa M. Fitzgerald, Ph.D., Founder For larger chip sizes, this generally prevent the laser light from scattering. and Managing Member, AMFitzgerald means that not all of the wafer area & Associates, may be contacted at can be utilized, or if it is, sub-dicing is Costs [email protected]; Brent M. required. (Figure 3) The stealth dicing As it is a new technology, stealth Huigens, Associate, AMFitzgerald & laser rasters along a pre-programmed dicing is more expensive than traditional Associates, may be contacted at bmh@ path, so offset grid formats are feasible, wafer sawing. Longer set-up time is amfitzgerald.com

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 35 Dispensing Advantages for MEMS Wafer Capping By Akira Morita [Nordson ASYMTEK]

here are many applications sealant can be a UV cure adhesive, for fluid dispensing in MEMS low-temperature solder, covalent, or a Tdevice manufacturing. In MEMS glass frit. The MEMS structure is then packaging, one area where dispensing capped with the glass wafer. A UV plays a significant role is in wafer light penetrates the glass wafer to cure capping MEMS before dicing. the adhesive. The wafer is then diced. MEMS are extremely fragile. The cap keeps the MEMS protected The slightest touch, vibration, or during the wafer dicing process. contamination can damage them. The The equipment used in MEMS wafer dicing process is full of obstacles capping is a dispensing work cell that Figure 2. Dispensing onto a wafer because the flow of water used in dicing consists of an automated fluid dispensing are manufactured in large volumes, and the particulates discharged in the system integrated with a same-side so wafer handlers, automated fluid process can destroy or contaminate the film-frame loader/unloader. This single dispensers, and the software that drives MEMS. Therefore, MEMS devices need work cell minimizes the footprint and them must automatically monitor and a protective covering to shield them maximizes throughput. The system is control fluid viscosity, dispense weight, during the dicing process. Thus, wafer fully enclosed with interlocked doors pressure, line widths, and placement at capping is done before dicing. and windows (Figure 1). the speed required to achieve desired MEMS wafer capping is a process MEMS are 1 to 100µm in size, and throughput while maintaining high yields. that has been around for about 10 years. MEMS devices generally range in Reduction of manufacturing costs is However, back then, most of the MEMS size from 20µm to 1mm. The volumes also important because packaging is a devices were used in applications where of fluid dispensed must be at the determining factor for the production cost the package had to be hermetically sealed micron level and dispensed precisely of MEMS (Figure 2). and extremely reliable. The process was in very thin lines. The corners must quite costly, so wafer capping wasn't be extremely defined so each cavity Jet Dispensing for Wafer Capping a common practice. Today, MEMS section covers the MEMS, ensures the In addition to all the advantages are used in consumer products like MEMS device is well seated, and the inherent in jet dispensing technology, microphones in mobile phones and glass connects properly to the wafer. there are three distinct advantages for the mouse for PCs. Since these new Volumetric control must be maintained MEMS wafer capping: applications do not require MEMS to be to ensure fluid deposition is accurate • speed hermetically sealed, new manufacturing and within tight tolerances. Many of the • the ability to dispense fine lines and methods and challenges have arisen. end products that contain these devices sharp corners One of these new methods is dispensing • elimination of the knit line or "dog- the sealant and adhesives in the wafer bone" effect capping process. Jet dispensing systems The precision, accuracy, and speed have been designed to specifically handle that jetting provides meshes well MEMS wafer capping. with MEMS requirements. Jetting is the process where fluid is rapidly The Wafer Capping Process ejected through a nozzle, using the The package structure for MEMS fluid momentum to break free from the wafer capping consists of a substrate, nozzle. A discrete, controlled volume a wafer with MEMS, and a glass wafer of material is ejected with each jetting (or another silicon wafer) containing cycle. Jetting is fast because when the cavities that cap the MEMS. Die- moving from one dispense location to attach adhesive, such as silver epoxy, the next, it is not necessary to move is dispensed in thin horizontal and up and down in the Z-axis. Dispense vertical lines onto a film-frame wafer speeds ranging from 20mm-70mm/sec to attach the MEMS devices. A layer for MEMS applications, depending on of sealant is jetted around the rim of Figure 1. Integrated workcell with a loader and the fluid and application requirements, each cavity on the glass wafer. The dispenser for MEMS wafer capping offer higher throughput than needle

36 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] dispensing. For example, in a typical Other MEMS Dispensing and Jetting module assembly. Jet dispensing is an application, a jet can dispense at 80mm/ Applications ideal way to deliver that underfill. Finally, sec as compared to 30mm/sec with a In addition to wafer capping, jetting is the SmartPhone alone has at least 15 parts needle. Because jetting is a non-contact used in many other MEMS manufacturing that utilize MEMS where automated fluid process, it is less sensitive to the dispense applications. For example,jetting dispensing is required. gap for “potato chip” wafer topology of silicone isolates the MEMS chip from wafers that aren't perfectly flat. the environment by encapsulating the Akira Morita, Business Development Jet valves can dispense dots to form wire bonds. MEMS packages on flex Manager, Nordson ASYMTEK, may line widths as narrow as 300 or 400µm printed circuit board require underfill for be contacted at akira.morita@ (Figure 3). Innovations like calibrated the CMOS image processor of a camera nordsonasymtek.com. process jetting (CPJ) significantly reduce process variability. Pressure is adjusted to maintain constant mass per dot and proprietary software and hardware automatically compensate the dispensing process for both fluid viscosity changes over time and batch- to-batch variations. These factors are especially important for working with MEMS as CPJ increases dispense accuracy, delivers higher yields, and ensures consistent Takt time (pace set

Figure 3. DispenseJet® valve jets dots to form 400µm lines for industrial manufacturing lines) for improved process capability, resulting in a highly repeatable process. Set-up to set-up and line-to-line variations are minimized and the need for operator interaction eliminated. Jetting is faster and makes better lines and sharper corners than other technologies. A significant concern in dispensing is the knit line — the beginning and end- point of the dispensed line. There needs to be a seamless connection and the line width must not vary. For example, if too much material is dispensed at the beginning or end of the line, or the end doesn’t break cleanly, the result is referred to as the “dog-bone effect,” because the extra fluid at the ends of the line resemble a dog bone. This often happens with needle dispensing due to excess fluid left when the needle is retracted. In contrast, a jet dispenser shears the material, eliminating the dog-bone effect and providing a seamless connection.

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 37 LED Dicing: The Sapphire Blaze Indeed By Jeffrey Albelo [Quantum-Group Consulting, Ltd.]

ubies are red and sapphires boring and pretty colors, the LED are blue and it’s all because industry exists. Band-gap-engineered, Rof 10dq. With the notable exception of multilayer junctions sitting atop very emeralds, most gemstones are based on clean sapphire make for an interesting transition metal impurities suspended in juxtaposition between Mother Nature a crystalline corundum (Al2O3) matrix. and human efforts. Mother Nature 10dq, or more formally, ∆10dq, which creates value by making her sapphire refers to the energy gap imposed upon dirty. Human-kind takes great pains to formerly degenerate energy levels keep its sapphire squeaky clean and (Figure 1) by the presence of ligands highly refined to create value on LED, Figure 2. LED yield considerations, the 3-legged (moieties coordinated to transition metal (Si on Sapphire (SOS) for RF devices piano stool, very stable, but each leg is equivalently ions in inorganic and organometallic where analog and digital processing important in delivering stability. complexes). It is the oxygen atoms can be handled on a single monolith), aimed at LED packaging applications, surrounding Cr3+ in the case of rubies, or other hybrid applications. In terms an area where laser-based products have of value creation, Mother yet to make a showing. One might even Nature wins, with about $30B imagine solutions where etch-based in annual gem sales compared singulation might be considered, but it with the combined engineered is not yet commercially available. sapphire market at around $16B. Take heart, even though Laser-based scribing she who must be obeyed has Although advances in mechanical been at it for an age we win scribing have been deployed, the Figure 1. A conceptual representation of crystal field splitting in the end, with the advent industry has shifted to laser-based of green lighting solutions processes. This shift has been dictated or Ti4+ and Fe2+ as a charge transfer coming on the heels of government by the need to raise LED yields to pair in sapphires, that account for mandates for same, the five year CAGR improve the distribution between the the crystal field splitting exhibited >20% far outstrips projected gem sales two basic (somewhat tongue-in-cheek) in these gemstones and thence their growth by nearly 2:1. LED categories: high-quality LEDs and characteristic colors. Once formed, using whichever Christmas lights. The issue associated The size of this splitting determines process, (please ignore that “lift-off” with laser-based processes is the the absorption wavelength upon noise from behind the curtain) these damage induced by the laser beam, as excitation by visible light and is devices must be singulated. At last it is invariably focused either onto the analogous to the band gap in LED and count, there were three commercially surface or into the bulk via very high other similarly conceived devices. The viable choices for affecting singulation: NA lenses. The problem with this laser larger the gap the more energetic the mechanical scribe-and-break, laser approach is the inherent limitations photon (hν ≥ ∆10dq) must be to promote scribe-and-break, and laser full-cut; or in imposed by basic physics that serve electrons from the lower energy orbitals other words “slow, slower, and slowest” to bind the ultimate throughput and to the higher. More practically, the depending upon one’s perspective. At damage performance. Tamhankar and size of ∆10qd is directly proportional present, there is not a solution to address Patel presented data at 2010’s ICALEO to the observed color of the crystal; the cost-of-ownership (CoO) equation suggesting limitations encountered in ns ruby (red) for instance, has a larger gap in an ideal manner. Particular attention, processes, Figure 3, where increasing than its sapphire counterpart (blue). from a dicing solution perspective, has fluence showed diminishing returns in Put another way, the increase in the been paid to the three yield categories scribe depth. energy gap between d-orbitals causes depicted in Figure 2, all of which are the absorption of higher energy photons affected by all of the commercially Although their proposed solution and a corresponding red shift for the available dicing solutions. There is yet involved splitting the laser beams to observed or transmitted color, since another possibility. Evidence shows increase throughput, the scribe depth the observed or transmitted color is the that rapid bulk etching of alumina may was limited to ~50µm, which still complementary color of the absorbed be economically feasible. The etch requires reasonably high breaking wavelength. Somewhere between really solutions presently being deployed are force, generates debris, and causes

38 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] and quality, one must reduce the force required to free these dice from their mother substrate. This means a laser process must be created that enhances the defect formed in the sapphire, without requiring more time, impeding the electrical performance, or optically damaging the Figure 3. Diminishing returns. Hitting the sapphire substrate. Figure 4. Stressed out. Side (L) and top-down view of the Stealth harder ultimately yields scribes of unremarkable defects in Si. Stress in the crystal is a result of deposited energy depth and induces loss in quantum efficiency and Stealth dicing which distorted the crystal and is a result of exceeding the optical breaking yield. (Image courtesy of Spectra-Physics) By now everyone (even breakdown threshold in the material, which even when induced by crystal damage. The experienced in the that guy in the desert with short pulses, still creates thermal damage. (Image courtesy of Disco) audience are thinking, this limitation is the coke bottle that fell from the sky in pulses, the joules dropped onto the imposed by pulse width; a correct, but The God’s Must be Crazy) has heard surface or into the bulk ultimately end ultimately incomplete answer. about stealth dicing and opinions are up somewhere. If one must employ a The present bestiary contains as common as post-dicing defects. process that requires multiple passes, commercial solutions using picosecond Fans and detractors alike will agree the advantage of the short pulse laser lasers that fare better in terms of light the process takes too long and still has is somewhat negated as the crystal still loss, but struggle with Distributed Bragg legions of casualties as a result of post “feels” somewhat roughly handled. Reflector (DBR) layers, CoO, or are singulation failures in one (only one?) To wit, even Disco reports there is a ultimately limited by the breaking yield of the three aforementioned quality stress field associated with the stealth by virtue of the applied force required areas. The reasons for this are related defect (read: Optical Breakdown, OB) to affect singulation. To improve yield to deposited energy, even with short delivered into single crystal material.

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 39 Although Figure 4 is for silicon, the concept is a well-placed coffin nail for sapphire, in that the surface faces of the dice will bear the morphology associated with the stress field so-created. In addition to, or perhaps because of this stress, the surface faces are rough and non-uniform, resulting in electrical performance issues associated with increased operating temperature. This increase in temperature is a result (among other factors) of reflected light into the device. Why, one might ask, does the crystal care if the defect is formed neatly beneath the surface? The mechanism of formation requires exceeding the optical breakdown threshold of the material, and herein lies the problem with the bigger hammer approach. Silicon substrates lend themselves to optically induced damage because, within limitations, the final performance of the device being singulated is not affected by the optical quality of the edge (micro-cracking notwithstanding). For LEDs, the situation is quite different. Figure 5 portrays the evolution of light from the device as a mathematical model of intensity vs. position; a fair amount of light passes into and through the substrate. If the light has difficulty escaping, the substrate temperature rises. The junction efficiency decreases with rising temperature, so the extracted light fraction per watt of electrical energy falls. This takes the devices in the opposite direction of all the cap-ex to date, where even small efficiency gains were pursued with abandon. At this juncture, it is useful to call to mind that deposited laser energy is transferred to the lattice as electronic interactions and as heat via collisions with phonons. Both processes, for very short pulses, can be temporarily decoupled since the main energy transfer occurs via the hot electron sink after the pulse has stopped. For pulses longer than a few tens of picoseconds, the mechanism involves heating conduction- band electrons by the laser pulse and transferring this energy to the lattice in a photon-electron-phonon interaction. Damage occurs by a conventional heat deposition process resulting in a phase transformation of the dielectric material. To achieve OB (the stealth defect) the material has to be transformed into an absorber by having its electrons “pumped” by subsequent laser pulses to the point of so-called avalanche onset, where free electrons are created and dielectric breakdown occurs. Without breaking into a full derivation (‘Meet the Fokker- Plank equation’ leaps to mind), the reader must accept on face value that the OB phenomenon is bounded by a critical fluence, Fcr, which is directly proportional to the natural log of the

Figure 5.Snow Cones. Despite marketing efforts to the contrary, physics requires all processes to play by the same set of rules. From L to R, the simplified light cone model, the interaction with the sapphire substrate and finally, the fully populated light evolution model, illustrating the complexity of extracting light from these devices and the volume of light traveling into and through the sapphire.

40 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] population inversion (from a number density point of view) caused by multi-photon processes. 1 p 2 F =I t 1 cr 0 2 ( ln2) Therefore, this threshold fluence falls Figure 7. Where angels tremble while they gaze. The as the pulse width decreases, so the edge view of 100µm sapphire singulated with the proposed filamentation approach. The visible edge astute reader solves the present problem has been scribed and diced, visible on either side, is by simply applying a femtosecond laser the modified regions wherein the defect has been to the issue of LED singulation, figuring created by plasma induced ablation of the material. that lower delivered fluence will yield less substrate damage. A correct Figure 6. A not so winding road. AFM roughness can deliver LEDs of higher quantum observation, but again, at its core, it is of the Sapphire substrate following singulation efficiency simply by virtue of their an incomplete answer. using the proposed filamentation technique. Note singulation. As it turns out, this the RMS roughness is < 200 nm. This roughness is adjustable over a range that makes it perfectly approach is adjustable, over a range A novel approach feasible to program the dice edges to deliver optimal from <200nm up to 1000nm in RMS While collateral damage can be light transmission, thereby solving one mode of LED edge roughness by simply choosing the reduced by judicious choice of pulse yield loss, while also addressing the other two post appropriate condition. singulation yield issues. width, the act of singulation still requires perturbation of the lattice and come to pass. This Pcr, is given by, Conclusion 2 2 that requires some minimum amount d 2 p(0.61) l In all the ways the LED singulation F cr= p( ) I= of damage. In order for the yield to 2 8n0n2 process can go awry, this approach remain commercially acceptable, the where n0 and n2 are the linear and creates a finished product, a singulated amount of force applied “to break” nonlinear refractive indices of the die that is superior to conventional must fall below some upper limit, material. Filamentation occurs due dicing methodology. It bears imposed by, among other things, to self-focusing that transpires under investigating this phenomenon more substrate thickness. Exceeding this these power conditions and is balanced fully, as there is ample commercial limit will produce an unacceptable against defocusing that occurs as a impetus to do so. Figure 7 is an edge level of device failures and/or broken result of the weak plasma formed by view of sapphire singulated at 600mm/ pieces. Keeping extracted quantum the multi-photon processes, which sec. where the defect persists from efficiency firmly in mind, one is left should sound familiar from the top surface to bottom surface, through to conclude that there is a maximum previous discussion of OB. Depending the substrate’s 100µm thickness. This yield for this process, above which one on fluence, these transients can defect is clearly visible as it extends cannot aspire, unless a novel approach form and persist for many 10’s of throughout the bulk of the sapphire. is contemplated. meters in air. Their condensed matter Figure 7 is an edge view of sapphire Most of the LED devices presently cousins can similarly persist for singulated at 600mm/sec where the produced are either singulated using millimeters in transparent media. Upon defect persists from top surface to a plain vanilla ablative technique choosing the proper conditions, one can bottom surface, through the substrate’s to affect surface scribes or an OB envision a process where the damage 100µm thickness. This defect, so technique (Stealth, et al.) relying on problem is eliminated by formation rendered, is clearly visible as it extends internal breakdown of the dielectric of plasma dense enough to vaporize throughout the bulk of the sapphire. from very tightly focused beams. Both a gossamer thin tube of material; it Thomas Gray, English Poet and approaches create device failures, can be accomplished at a previously Professor at Cambridge (1716-1771) via one or more well-known and unheard of rate and as a bonus it can once wrote, “… the living throne, the oft lamented mechanisms. A novel eliminate the reflection problems sapphire-blaze, where angels tremble approach might employ a closely associated with traditional methods. while they gaze, he saw, but blasted related phenomenon known as It is this latter piece that bears minor with excess of light, closed his eyes in filamentation. Studied extensively exposition. In the same fashion that endless night.” It is likely this is not back in the 1970s, Marburger, a Ronchi grating operates to enhance to be, in that there exists a solution to et al, discussed the formation of light passage across a barrier, one deliver the “excess of light”. One need filaments in air. A condensed matter can, using this new technique, match only seek a suitable commercialization model and experimental was not the wavelength of the device with the route to realize its advantages. undertaken until much later, and has spacing of the edge roughness. As only recently become commercially Figure 6 shows, die-edge roughness Jeffrey Albelo, president and CEO interesting as the advent of reliable can be controlled by judicious choice Quantum-Group Consulting, Ltd., may and affordable short pulse lasers has of process conditions and therefore be contacted at [email protected].

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 41 INDUSTRY NEWS

(continued from Page 13) Session 2 – 3D Process Advancements was that integration incorporates through Part I, Session 4 – Fan-Out Wafer Level silicon vias (TSVs). Dr. Lau covered the Packaging Technologies and Session 8 – origin and evolution of 3D integration, 3D Process Advancements Part II. technology development roadmaps, and he proposed a few generic, low-cost, and thermally-enhanced 3D IC integration System-in-Packages (SiPs) with various passive TSV interposers for small form factor, high performance, low power and wide bandwidth applications. Figure 11. The 3D Panel discussed 2.5D vs. 3D technologies. (L-R) Phil Marcoux, consultant, PPM ; Ron Huemoeller, Amkor ; Scott Jewler, Powertech Lively Panel Discussions Technologies ; Rao Tummala, Georgia Tech’s 3D PRC ; and moderator, Francoise von Trapp with timely jokes, amusing examples, and Figure 8. Peter Ramm, Fraunhofer EMFT, introduces funny illustrations while describing the very plenary speaker, Matt Nowak Qualcomm. serious thermal management challenges Stimulating Plenary Sessions facing 3D IC packaging and integration as Prior to each day’s technical sessions, computing products strive to operate faster attendees were treated to a stimulating and shrink in size. Thermal management can morning plenary speech. The first was no longer be addressed solely at the system “High Density TSV Chip Stacking: Figure 10. An unidentified attendee queries the level using heat sinks and fans inside the Fabless Infrastructure Status” by Matt infrastructure panel, which was moderated by Simon product enclosure. Heat must be dissipated Nowak of Qualcomm. He presented McElrea, Invensas at the device level and must be capable of some examples of several chip This year’s IWLPC program included withstanding shock, drop impact, and bending stacking partitions that are reportedly two panel discussions that provoked quite often encountered by portable products. in development for productization, and a few questions and debate among the discussed the progress made with respect panelists. “3D Infrastructure Issues for to previously perceived challenges. Mr. Technology Adoption”, moderated by Nowak went on to say, “Especially critical Simon McElrea of Invensas Corp. brought for the productization of high density together a distinguished panel consisting TSV technology for high volume mobile of Sesh Ramaswami, Ron Leckie, Peter wireless applications will be the readiness Ramm, Ph.D., Andre Rouzaud, Ph.D., Jan of the fabless supply chain infrastructure, Vardaman, and Jim Walker. including industry standards, supply chain “Will 2.5D and 3D Compete or Figure 12. Raj Master, General Manager for IC business models for stacked memory Coexist?” was the title of the second Packaging, Silicon Operations, Quality and Reliability cubes, and competitive pricing.” discussion with panelists Scott Jewler, for all hardware products at Microsoft entertains the The second plenary talk was “Evolution, Ron Huemoeller, Phil Marcoux and Rao dinner crowd with his keynote speech titled “Thermal and Power Considerations in Consumer Electronics.” Challenge and Outlook of 3D Si/IC Tummala, Ph.D., moderated by Francoise Integrations” by John Lau, Ph.D., of ITRI. von Trapp of 3D InCites. Each panelist For the first time this year, IWLPC He explained the difference between 3D made a short presentation and stated provided video coverage of some of the IC packaging and 3D IC or Si integration their case before the floor was opened for plenary talks, keynotes, and platinum questions The consensus opinion favored sponsors. Clips can be viewed at www. coexistence of 2.5D and 3D integration. iwlpc.com and www.chipscalereview.com.

Entertaining Keynote Save the Date Following Wednesday night’s dinner, Raj IWLPC 2012 will have an expanded Master, General Manager for IC Packaging, exhibition hall when it moves to the Silicon Operations, Quality and Reliability for Doubletree Hotel in San Jose, CA on all hardware products at Microsoft gave an November 5 – 8, 2012. Many of today’s entertaining keynote speech titled “Thermal WLP challenges will be addressed in the Figure 9. Vern Solberg of Invensas, is among a full and Power Considerations in Consumer coming year. Don’t miss next year’s event house tuned in to John Lau’s plenary talk Electronics.” He kept the audience laughing to learn about all the progress.

42 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] Nordson Corporation Establishes Adamson was very active in the he was awarded the Daniel C. Hughes, Steve Adamson Memorial Annual International Microelectronics And Jr. Memorial Award by IMAPS, which Scholarship Fund Packaging Society (IMAPS), serving as is presented to the individual who Steve Adamson, former Nordson President in 2008 and as chairman of the has made the greatest contribution ASYMTEK marketing specialist and IMAPS Microelectronic Foundation in to IMAPS and the microelectronics electronics industry mentor, passed 2009. In 2010, he received the IMAPS packaging industry, including technical away October President’s Award in recognition to his and/or service contributions. Donations 28, 2011, after a lifelong efforts for the organization. to the fund in his honor can be made at: 15-month battle with Most recently, in early October 2011, www.microelectronicsfoundation.org. cancer. Nordson ASYMTEK honors his life by funding a $3,000 annual scholarship in Adamson’s name with the IMAPS Educational Foundation, whose role is to support student activities related to the study of microelectronic packaging, interconnect and assembly. “This donation supports the mission of the educational fund, which Steve was instrumental in establishing. We are glad we can honor the memory of Steve in this way,” said Michael O’Donoghue, Executive Director IMAPS. Adamson started with Nordson ASYMTEK in 1998 as applications lab manager, and most recently was market development manager for the semiconductor packaging and hard disk drive industries. Over his career with Nordson ASYMTEK, Adamson contributed to the success of several important projects, including the Axiom and DispenseJet product lines. Adamson previously held positions with Kodak, Motorola in the U.S., and Plessey, International Computers Ltd in the U.K. He was awarded five US and two UK patents. Originally from the UK, he held a Higher National Certificate in Electrical Engineering from Stockport College of Technology. In 2005 he was presented an award by the San Diego Engineering Council for “Outstanding Service to Electrical Engineering”. “We will miss Steve’s creativity, intellectual curiosity, and friendship. And the industry will miss his active participation and leadership,” stated Greg Hartmeier, vice president, Nordson ASYMTEK.

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 43 Deca Technologies: Changing Packaging by 10x By Francoise von Trapp, Sr. Technical Editor queried, “Start with a large fortune.” At an exclusive launch party held at the home and vineyard of Cypress CEO, T.J. But where Rodger’s is willing to take Rodgers, the story unfolded about Deca Technologies, a disruptive packaging a loss for the sake of the wine, he’s not start-up backed by Cypress and its solar child, SunPower. Francoise von Trapp, willing to take a loss for the sake of Sr. Technical Editor, was there to tell the tale. technology improvements. For example, he abandoned a project on solid state lighting when he realized that the end product couldn’t compete with standard ovember 9, 2011 just might the brink of collapse in 2003 to one that lighting on asking selling price (ASP). go down in semiconductor reported revenue of $2.2B in 2010. So he That’s why Cypress invested in SunPower, Nhistory as the date the whole game approached TJ Rodgers, CEO of Cypress, because he saw opportunity to improve changed for semiconductor assembly, with the idea. With $35M in seed money manufacturing processes to reduce the cost packaging and test. This day marked the from Cypress, work got underway. of a wafer from $1000/wafer to $10/wafer. official launch of Deca Technologies, Transferring that technology knowledge to an interconnect technologies company Cypress Involvement Deca Technologies for WLCSP, Rodgers that intends to offer a novel approach to Cypress CEO, TJ Rodgers, has vision is looking beyond the initial product manufacturing processes for wafer level and likes to take risks. An engineer with offering of the WLCSP to the next product packaging, based not on semiconductor degrees in chemistry and physics, he’s on the drawing board; silicon substrates, manufacturing but the solar cell always looking for a better way to do which up until now have been too costly manufacturing processes introduced by things. When he’s not running Cypress, to become mainstream. “If you can make SunPower Technologies. In an ironic he’s on a quest to produce “the best Pinot a wafer for $10, then you can make silicon twist, where SunPower had leveraged the Noir in the ‘New World.” He’s done a interconnects that you can put chips on,” semiconductor manufacturing knowhow careful and thorough study of French notes Rodgers, adding that it’s about of its benefactor company, Cypress winemaking processes, and has simulated making something both cheaper and better. Semiconductors, to reduce the cost of conditions and processes from France to While WLCSPs are a better performing manufacturing its solar cells; now the produce a high-end wine at his winery, technology than wire bonded packages, semiconductor packaging industry stands Clos de la Tech, in Woodside CA. He’s they are more expensive to make. But to benefit from knowledge based in solar a purist in winemaking; the grapes Deca’s technology takes the cost out, cell manufacturing. are foot crushed and never come into reportedly achieving a cheaper WLCSP The story began in 2009 with a contact with machinery (Figure 1). The while retaining high performance. conversation and a compelling concept. only nod to technology is his custom- According to Deca CEO and founder, designed fermentation controller system Deca’s Secret Sauce Tim Olson, the idea blossomed out of the from Cypress, where he puts Cypress Deca’s success depends on a careful unresolved industry need for solutions engineers to work creating systems to blend of unique manufacturing based on that address cycle time, cost of ownership, gather and analyze data from the tanks, SunPower’s continuous wafer flow line and process flexibility. The inspiration using RF devices to transmit the data to rather than a batch process approach; came by example from SunPower, a computer. No expense is spared in this and custom proprietary equipment which, according to SunPower CEO Tom endeavor. “How do you make a small from suppliers outside the traditional Werner, had developed a low cost way to fortune in the wine industry?” Rodgers semiconductor equipment manufacturing manufacture high-efficiency silicon solar realm. It’s WLCSP process is nearly cells in high volume thanks to lessons parallel to SunPower’s solar cell back- learned from Cypress. Olson recognized end of line (BEOL) processes. “We have that these proprietary processes could special stuff that nobody in the world be adapted to re-engineer core processes has because of SunPower,” notes Olson, for wafer level chip scale packaging adding that exclusivity with suppliers is (WLCSP). Additionally, as a member the key. He said that getting suppliers of Cypress Semiconductor’s technical to agree to exclusivity agreements was a advisory board, Olson had witnessed the daunting task, but in the end, they were company’s ability to breathe life back into able to accomplish just that, with some Figure 1. SunPower, turning it from a company on TJ Rodgers explains wine making to the Press. agreements for an indefinite amount of

44 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] time, and others that are for a minimum 2012 anticipate 24/7 operation. anticipates two remaining customers of five years. Additionally, the company At the time of the launch, Deca has to begin qualification within 90 days. is hyper-careful with its trade secrets, engaged six customers, five of whom The company expects a significant requiring extreme sensitivity throughout report in excess of $1B revenue/ production ramp by Q4 2012. “2013 its workforce and restricting access to the year. Olson said the first customer will be our first big year,” says Olson. manufacturing lines. Olson also said that is qualified for production; the next This will undoubtedly be an exciting they have highly educated technicians three are undergoing qualification. He company to watch. running the processes at the facility, located within SunPower’s complex in the Philippines. “All our manufacturing technologists are English-speaking, degree-level engineers,” he said. Deca’s technology spans interconnect levels from chip to package to system, noted Olson, and offer exponential improvements in speed, cost and flexibility. Its first products are in the WLCSP family (Figures 2).

Figure 2. Deca’s first product is a fan-in WLCSP available in three different configurations Acknowledging that these are “me too” products, Olson explained that the company’s strategy is to enter the market with existing products that are manufactured in breakthrough cycle time; at the lowest total cost of ownership; and can be taken from design to manufacturing in minutes rather than days. This path is the quickest to a solid revenue stream. Next on Deca’s roadmap is the technology that has Rodgers all excited: silicon substrates that could provide the cost improved solution for silicon interposer technology.

Ready out of the Gate With its eye keenly on the analog power management and RF connectivity markets, Deca is ready to roll. “This is not just an idea,” noted Olson. “We are ready to go to production.” He claims the company achieved 97% yield on the first wafer that went through the line. Now they’re achieving above 99% yield. They are fully staffed for one shift and by Q2

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 45 PRODUCT SHOWCASE

46 Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] EDITORS OUTLOOK

ACT IV By Ron Edgar [Chip Scale Review Contributing Editor]

Double, double, toil and trouble; from here? “ . . . carbon nanotube networks recently inaugurated a new Sustainable Fire burn; and cauldron bubble.” may not be the replacement for copper in Manufacturing Program. This is a “To many, the “magic” of the science logic or memory devices, but they may collaboration between a number of major behind, and the manufacturing of, state-of- turn out to be interconnects for flexible manufacturers and several universities. the-art electronic devices might as well be electronic displays or photovoltaics,” Strus Why NIST? In their own words, “This the witches’ brew from Macbeth. Exotic says. program is aligned with the Engineering materials, exacting requirements, all cooked “Eye of newt, and toe of frog, Wool of Laboratory (EL) mission to promote U.S. up for a special purpose. I’ve been revisiting bat, and tongue of dog” . . . Atomic Force innovation and industrial competitiveness NIST (National Institute of Standards and Microscopy (AFM) is a favored method of in areas of critical national priority.” Technology) to see what they have been measurement at the nanoscale but “most Recent studies conducted by Harvard doing recently that is of interest to us. can only produce qualitative images. Business School and the MIT Sloan “Fillet of a Fenny snake, in the In contrast, contact-resonance force School of Management concluded cauldron boil and bake” . . . Carbon microscopy (CR-FM) enables quantitative that sustainable product and process nanotubes show great promise as a possible mechanical-property mapping. CR-FM development across all industry sectors replacement for copper interconnects on involves vibrating the AFM cantilever “is essential to remaining competitive.” ICs. “But—not so fast.” says an article in while its tip is in contact with a sample. Current efforts have, at best, been sporadic NIST Tech Beat, August 16, 2011. “Recent In this way, the resonant modes of the and specific to the organizations who tests at the National Institute of Standards cantilever—the “contact resonances”— were trying to implement such ideas. With and Technology (NIST) suggest device are excited. From measurements of the NIST’s involvement and the effort of the reliability is a major issue.” NIST have contact-resonance frequencies, information contributors it is hoped to create innovative been studying how carbon nanotubes is obtained about the interaction forces methods that can be applied industry- might behave in real electronic devices and between the tip and the sample (e.g., wide in the hope of reducing energy have been focusing on how they interact contact stiffness). Models for the tip- costs, improving processes, encouraging with metal structures and various kinds of sample contact mechanics are then used to cooperation, and increasing profitability. nanotubes structures. In a paper presented relate the contact stiffness to mechanical “For a charm of powerful trouble, at IEEE Nano 2011, Portland, Ore., Aug. properties such as elastic modulus.” like a hell-broth boil and bubble” 17, 2011, by M.C. Strus, R.R. Keller Donna Hurley and her team have the goal . . . Semiconductor research is a vast and N. Barbosa III, Electrical reliability “to provide tools for nanotechnology area and a hard one to keep up with. In and breakdown mechanisms in single- research and development that rapidly an agreement between NIST and AIP walled carbon nanotubes, experiments and nondestructively map the nanoscale (American Institute of Physics), a great with carbon nanotubes interconnecting mechanical properties of new materials and deal of research information is now metal electrodes showed degradation of devices. Measuring localized variations available free of charge. David Seiler the nanotubes interconnect and failure of in properties not only yields valuable of NIST says the available materials the metal electrodes. “The common link is information on material homogeneity and “represent research and overviews of that we really need to study the interfaces,” manufacturability, but also enables early critical topics collected from worldwide says Mark Strus, a NIST postdoctoral identification of subsurface defects. Our experts in the field of semiconductor researcher. In other experiments with methods also provide size-appropriate characterization and metrology.” nanotubes networks, where electrons data critical for the predictive modeling of “hop” between nanotubes, failures were device reliability and performance.” So be sure to visit www.nist.gov regularly seen between nanotubes. Monitoring “Adder’s fork, and blind-worm’s as they are a source of invaluable this provides a means of assessing the sting, lizard’s leg and owlet’s wing”. information. And here’s wishing us all a reliability of a network. So where do we go . . NIST’s Engineering Laboratory has happy and prosperous 2012.

Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 47 ADVERTISER-INDEX ADVERTISING SALES

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