Stealth Dicing Technical Information for MEMS 2 Table of Contents

1. Introduction 2. Problems with dicing in MEMS fabrication processes 2.1 Grinding wheel type blade dicing 2.2 Making dicing a completely dry process 3. Stealth dicing technology 3.1 Basic principle of stealth dicing 3.2 Internal-process laser dicing versus surface-process laser processing 3.3 Range of thermal effects on MEMS devices during internal laser process 3.4 Checking thermal effects on device characteristics 3.5 Limitations when using stealth dicing 4. Stealth dicing boosts profits 4.1 Benefits from a 10 µm kerf width 4.2 Benefits when dicing irregular chip shapes 5. Dicing materials other than 5.1 wafers 6. How green-friendly stealth dicing improves our environment 7. Conclusion

"Stealth dicing features" that will completely rewrite conventional dicing concepts

Wafer dicing

Laser dicing

Blade dicing

Laser ablation dicing Stealth dicing

Processing method Grinding cutting and process Surface absorption laser process Internal absorption laser process (melting, evaporation) (locally selective) Water (cooling / cleaning) Required Required Not required Chipping Occurs Occurs Does not occur Debris generation Generates Generates Does not generate T-shape and round shape dicing Not possible Possible in certain cases Possible High-speed ultra-thin dicing Might be possible in certain cases Possible in certain cases Possible Chip yield Not so good Not so good Good Processing speed Not so good Not so good Good Thermal effect on device Affected (including residual stress) Affected (HAZ*) Not affected * HAZ: Heat Affective Zone

3 1. Introduction 2. Problems with dicing in MEMS fabrication processes Various different kinds of technologies such as mechanical engineering, quantum mechanics, electrical engineering, chemistry, and optics that were thought of as different fields until recently 2.1 Grinding wheel type blade dicing were merged on a fabrication process as microma- Major problems that must be avoided during dicing of MEMS chining technology. This new technology offers tremendous devices with fragile structures include contamination and stress possibilities that are starting to gather much attention. This technol- loads on the functional elements. The following are inevitable ogy has gradually grown along with the spread of etching technol- problems with the dicing process used in typical blade dicing ogy since it could freely form thin film structures, girders and processes. hollow structures with fine accuracy to the micro level on wafers. 1Problem with wet processes These capabilities appealed to the imaginations of MEMS (micro · Fluid pressure applies stress loads on the structure due to use electro mechanical system) designers who are now starting to of cooling water and rinse water during dicing. create totally new functional devices. · Functional elements are re-contaminated by foul cutting fluid Stealth dicing is a completely new laser dicing technology. Stealth · Requires adding a protective film for protecting device dicing offers amazing advantages since it is a "completely dry structures from water and foul water as well as a process to process" yet generates "no debris" and has "zero kerf loss". This remove that film technology was especially developed for the purpose of high-speed 2Problems with contact type processes yet high-quality dicing of ultra-thin semiconductor wafers and its · Contact type cutting processes apply a vibrating load to the features are equally effective in dicing processes for MEMS structure devices. Stealth dicing is already being used for mass producing Figure 1 shows problems that occur when an MEMS device having MEMS devices and is on its way to becoming an industry standard a membrane structure is cut by blade dicing. Photo 1 shows for MEMS device production. damage to membrane structures due to fluid pressure during blade This technical material covers problems encountered in MEMS dicing. dicing as well as principles and processes involved in stealth dicing technology. It also offers a brief look at trends in developing new types of stealth dicing for use on materials other than silicon.

Diamond grinding wheel Cooling / rinse water

Membrane crack Chipping

Photo 1: Membrane damage due to fluid pressure

Debris generation

Structural damage

Debris Kerf loss adhesion

TLASC0022EA Figure 1: Problems with blade dicing

4 2.2 Making dicing a completely dry process Stealth dicing offers both these features 1 and 2 described above. When dicing an MEMS device, dicing technology is needed that In dicing technology using lasers, the ablation method has long applies minimal stress to the delicate structures inside the MEMS been studied as a laser process method 1) 2). Laser ablation, device. At the same time, some measures are also needed to however, produces debris contaminants during processing so prevent the device structures from particle recontamination. These pre-processing is needed to coat a protective film for protecting the problems can be eliminated by switching to a dicing process with device structures from these contaminants, and post-processing the following features: such as wet washing is also required. 1Fully dry processing: Prevents defects caused by wet process The next section briefly describes how stealth dicing is performed and reduces man-hours needed for production/inspection in a completely dry process. 2Non-contact dicing process: Eliminates stress applied to the device structures due to vibration accompanying the cutting process

3. Stealth dicing technology in the interior of the wafer, which extend towards both surfaces of the wafer. These cracks are an indispensable element for dividing the wafer into chips and should not twist broadly around the chip 3.1 Basic principle of stealth dicing or be prevented from developing towards both surfaces. When In stealth dicing, a laser beam at a light wavelength semitranspar- cutting a thick silicon wafer device such as MEMS devices, it is the ent to the material is focused on a point inside that material to form most important step to form SD layers and joint them vertically a cleaving start point (transformed area: hereafter called SD layer), while making multiple scans depth-wise in the wafer, so that an and external pressure then applied to the wafer to separate it into optimal SD layer for cutting is formed. multiple chips 3) 4). How these cracks relate to the SD layer is shown in Figure 3, along This technology therefore includes two processes. One is a "laser with the three states that we should understand for deciding the process" to form a cleaving start point (SD layer) on the interior of processing conditions. the wafer for separating it into chips; and the other is a "separation SD layers can be made into the three states according to the process" to divide the wafer into small chips. Figure 2 above shows purpose and application. These states can be combined to form an an overview of the laser process. ideal combination. Optimal processing conditions can be found via the device state such as the wafer thickness, chip shape, and 1Step 1 - Laser process whether a metallic film is used, etc. Once these conditions are A laser beam is focused on points inside the wafer to form an SD found they can be systematized in a database for use according to layer for cutting the wafer. Cracks are also formed on this SD layer the particular user and device.

Laser beam SD layer and cracks

Scan direction

Wafer Tape

TLASC0023EA Figure 2: Step 1 - Laser process

a) ST: Stealth b) HC: Half-cut c) BHC: Bottom side half-cut Cracks have not reached top or bottom Cracks have reached laser irradiation surfaces (internal crack state) surface (surface crack state)

SD layer SD layer SD layer

Cracks Cracks Cracks

Cracks have reached laser irradiation bottom surface (surface crack state)

TLASC0025EA Figure 3: Interrelation of SD layer and cracks formed in laser process

5 An overview of the "separation process" is next shown in Figure 4. towards the wafer periphery, so that a pulling or tensile stress propagates along the wafer and the stress concentrates at the tip of 2Step 2 - Separation process the crack. This concentrated stress causes the crack to instantane- Expanding a tape-mounted wafer already formed with an SD layer ously reach the wafer surface, and the wafer then splits into small towards the periphery of the wafer applies a tensile stress to the chips. 4) internal cracks in the wafer. This stress causes the internal cracks Photo 2 shows a cross section of an MEMS chip having a to develop towards both surfaces of the wafer and separates the membrane structure that was cut by stealth dicing. Both the front wafer into small chip shapes. and back surfaces of the chip have sharp and clean dicing lines Figure 5 shows a schematic view of the process up to separating with no chipping. The membrane structure in the chip center the wafer into chips by extending the SD layer cracks formed section also shows good quality dicing with no traces of damage or inside the wafer. debris that known to cause defects. The tape expansion process Forming an HC (half-cut) or a BHC (bottom side half-cut) during effectively applies stress to the crack tips without causing mutual forming of the SD layer will make it easier to separate the wafer interference with chips adjacent to each other. into chips. When the tape is then expanded towards the periphery of the wafer while in this state, the HC or BHC surface is pulled

Separated chip

Compression stress Tape expansion Tap expansion Tensile stress

TLASC0024EA Figure 4: Step 2 - Separation process

Wafer Crack extension

Tensile stress

Tape expansion BHC Tape Tape expansion

Wafer Crack extension

Tensile stress

Tape expansion Tape Tape expansion

Crack has reached upper surface Wafer Tensile stress

Tape expansion Tape Tape expansion

TLASC0026EA Figure 5: Crack extension principle Photo 2: Photograph of chip cut by stealth dicing

6 3.2 Internal-process laser dicing versus surface- that point. This cutting principle is clearly different from the process laser processing surface ablation method that carves a groove on the wafer by The difference between stealth dicing and ordinary laser surface making the laser beam be absorbed in the surface of the material. process is briefly described next. Stealth dicing is a clean cutting technology that emits no molten Photo 3 shows processing results when using different laser focus particles such as silicon dust onto the wafer surface during laser positions. This photograph allows comparing results from surface process. The range of thermal effects from laser process in terms of process by focusing the laser beam on the surface of a wafer with heat distribution on the internal and front surface reportedly differs results from focusing the laser beam on an internal point of the greatly according to the laser beam depth.6) Directing the laser wafer.5) beam on the interior of the wafer during laser process was found A unique feature of stealth dicing is that the laser beam first more effective in keeping a small heat distribution area than the irradiates an internal point in the material and starts cutting from conventional surface-focused laser process.

Stealth dicing Surface ablation process (Internally focused laser process) (Surface focused laser process)

Laser beam

Debris

Laser beam

SD layer

Silicon wafer Silicon wafer

TLASC0035EA

Surface Surface

Si Molten silicon Si

10 µm 10 µm

Cross section Cross section

Modified layer (SD layer) (Laser internal process) 10 µm 10 µm

Photo 3: Comparing stealth dicing (internally focused laser dicing) with laser surface process

7 3.3 Range of thermal effects on MEMS devices during Figure 7 shows these results applied to an actual device wafer. On internal laser process a typical device wafer, the width of the so-called dicing street is The first area of concern during laser dicing process is what about 50 µm to 70 µm. A look at Figure 7, however, shows that the thermal effects the laser process will have on the active area. thermally affected area remains small during stealth dicing Making a localized measurement of the actual temperature during compared to a typical dicing street. This shows that stealth dicing laser process is not an easy task. Here we briefly discuss the technology is capable of narrower dicing streets which in turn will internal temperature distribution in silicon during stealth dicing by allow a greater chip yield per wafer. using a report 7) from a simulation made to analyze thermal effects in silicon material based on temperature dependence of the laser Device area light absorption coefficient in monocrystalline silicon material. Figure 6 shows results derived from a thermal simulation analyzing the heat distribution within silicon material at each pulse near the Dicing street focused beam point during laser process to form an SD layer. This was performed by focusing the laser beam at a position whose depth is 60 µm from the surface of a 100 µm thick silicon wafer. Examining the maximum temperature distribution range in Figure 6 shows that the range where the temperature in the silicon rises 200 °C or higher during laser process is confined within ±7 µm centered laterally around the laser beam point. Focal depth 60 µm

25

Thermally affected area 15 µm 30

TLASC0027EA 35 Figure 7: Thermally affected area when forming SD layer

40

45

DEPTH (µm) 50 Temperature (°C) Under 200 55 200 to 500 500 to 1000 60 1000 to 1500 Over 1500 65 -25 -20 -15 -10 -5 0 5 10152025

RADIUS (µm)

TLASB0012EA Figure 6: Temperature distribution range within the silicon wafer per laser pulse

8 3.4 Checking thermal effects on device characteristics 10-6 Effects on characteristics of an actual device wafer were next d=10 (µm) d=150 (µm) -7 verified. A photosensor (photodiode) was used to verify device 10 0 (H) 0 (H)

(A) 500 (H) 500 (H) characteristics. In this verification method, two types of samples D 10-8 were fabricated with respective distances "d" of 10 µm and 150 µm from the device active area to the cut edge of the chip. The extent 10-9 of thermal effects from the laser process during stealth dicing were then investigated. 10-10 The photodiode’s dark current characteristics were investigated by -11 blocking the photosensitive area, applying a reverse bias and 10 measuring the leakage current. DARK CURRENT I DARK 10-12 ■THB (Temperature Humidity Bias) test Humidity and temperature were set to 85 % / 85 °C for a 500 10-13 hour period. 0.01 0.1 1 10 100 ■Temperature cycle (TC test) BIAS VOLTAGE VR (V) Performed for 100 cycles from -55 °C to 125 °C. ■Photodiode Figure 8: THB test results Plastic package type Chip size: 2 mm × 2 mm, chip thickness: 100 µm Figure 8 shows the THB test results. The dark current is about 0.1 10-6 nA at a Vr of 10 V or less. At a Vr higher than 10 V, the dark d=10 (µm) d=150 (µm) current rapidly increases and reaches a breakdown threshold. The 10-7 0 (cycle) 0 (cycle) dark currents were each 0.1 nA and 0.2 nA at d (distances) of 150 (A) 100 (cycle) 100 (cycle) D -8 µm and 10 µm. The dark current only increased a mere 0.1 nA even 10 if the distance from the chip cut edge to the active area was 10-9 changed to 10 µm from 150 µm. The figure also shows there was virtually no change in the test results after 500 hours compared to 10-10 the initial state. Figure 9 shows results from the TC test. Here also there was almost 10-11 no change in the dark current value after 100 cycles of TC testing

DARK CURRENT I DARK -12 even compared to the initial state. 10 These results prove that stealth dicing laser process is a technology 10-13 that exerts no large effects on device service life and durability. 0.01 0.1 1 10 100 This verifies the heat analysis simulation results in Figure 6 where BIAS VOLTAGE V (V) the area heated to 200 °C or higher was limited to ±7 µm in radius, R and also bears out the fact that there are no effects on device Figure 9: TC test results characteristics due to heat when the device is diced at a position 10 TLASB0013EA µm away from the active area. However, these tests do greatly affect the device structure, so the actual effects should be verified on each device that will be actually used.

9 3.5 Limitations when using stealth dicing front surface of wafers when a light-blocking metallic film is Due to its operating principle, stealth dicing is subject to the formed there. In this case, the interior of those wafers is machined following limitations. The laser beam is usually irradiated from the by irradiating the laser beam from the back surface (backside device surface to machine it internally (front-side irradiation irradiation method). Table 1 summarizes laser irradiation method method). However, it is difficult to guide the laser beam onto the according to the state of the device wafer.

Table 1: Laser irradiation methods per device structure Limitations when using front-side irradiation method TEG/metallic film on dicing street These should not be present. No problem with SiO2. Protective film on dicing street The SiN film thickness affects AF characteristics and processing. Consultation is required. Since the SD laser beam has an incident angle, non-light-shielded area is required to guide the beam Street width according to wafer thickness. BOX layer attenuates the laser beam power which causes a drop in the throughput time. Removing SOI wafers the BOX layer may improve the throughput time. Limitations when using backside irradiation method Special SD dicing tape is attached to the wafer backside and stealth dicing performed through the Wafer clamping method tape. However, if this is not possible, then the wafer can be clamped on a suction table and stealth dicing performed from the wafer backside, and tape can be attached to the wafer on the suction plate. Backside grinding roughness #2000 or more BOX layer attenuates the laser beam power which causes a drop in the processing time. Removing SOI wafer this BOX layer may improve the throughput time.

When dicing an MEMS device wafer, some method is also needed the wafer backside is held by the tape. to clamp the wafer if using the backside irradiation method. When The remainder of the process is extremely simple. The wafer is clamping the device surface of a wafer containing this type of removed from the suction plate while still mounted with the tape, delicate structures to a vacuum chuck table (suction plate), porous and then tape is expanded to separate the wafer into chips in a sheets with good cushioning should be used to hold both sides of simple and easy step. Figure 10 shows a concept view of this the device on the suction plate. Using a special dicing tape that backside irradiation method. allows the SD laser wavelength to easily transmit through will New advances being made in peripheral technologies will make allow forming an SD layer inside the silicon through the tape while stealth dicing the ideal solution for all types of devices.

Lens

Transparent tape

Silicon wafer Laser incident surface Si Si SD layer Laser incident surface Porous sheet Transparent Suction plate tape Expander

(a) Backside irradiation through tape (b) Tape expansion after removing the wafer from suction plate

TLASC0028EA Figure 10: Concept view of backside irradiation through tape

10 dicing street made possible by stealth dicing. Preconditions for this 4. Stealth dicing boosts profits calculation are a wafer diameter of 152 mm, a chip size of 2 mm × 2 mm and a conventional blade dicing street width of 80 µm. The Besides making MEMS devices more reliable, stealth dicing offers increased chip yield per wafer from shrinking the dicing street technology advantages with new added values that make business width was first found, and the profit then calculated assuming a more profitable. cost of 30 yen per chip. Based on a monthly production of 2000 wafers and so an annual production of 24,000 wafers, an extra chip 4.1 Benefits from a 10 µm kerf width yield equivalent to 190 million yen can be obtained. In more One important technical advantage is the chip yield obtained from realistic terms, the target production figure can be reached while one wafer. Stealth dicing is a cleaving technology and therefore using fewer wafers because of the increased chip yield per wafer. offers the overwhelming advantage of having absolutely no cutting Converting using the above figures yields a figure of 1585 wafers area. Even if we consider the chip edge straightness during wafer annually. separation, which is usually 2 µm to 3 µm, the dicing street width If irradiating the wafer with laser from the backside, then the laser required by this technology is a maximum of ±5 µm. This means beam spread should be taken into account. It is therefore necessary that the chip yield from a single wafer can be drastically increased. to find an area larger than 10 µm, where there is no metallic film Table 2 shows the chip profit calculated by using a 10 µm wide that blocks the laser beam.

Table 2: Calculated profit from a 10 µm street width Blade dicing Stealth dicing Units Work size 152 mm Dicing street width 0.08 0.01 mm Chip size 2 × 2 mm Effective number of chips 3732 3996 pcs Increased number of chips / wafer — 264 pcs Improved yield — 107.1 % Boosted profits (24,000 pcs per year) — 190,080,000 yen (calculated at 30 yen per chip)

4.2 Benefits when dicing irregular chip shapes Stealth dicing is also effective on chips containing T sections or curves. Stealth dicing also allows improving the chip yield per wafer by arranging chips in zigzag layouts. It also proves effective, for example, on wafers such as TEG wafers where one mask is used to form as many different chip patterns as possible. Besides linear process, stealth dicing can also be used for dicing round shapes. Figure 11 shows forming of dicing patterns for different chip sizes. CH1-12 3 4 Because of the different 2 mm and 10 mm square chip sizes, the dicing lines on the edges of 10 mm square chips do not intersect and form a T shape. No SD layers are formed by turning off the laser beam at the timing when the laser beam reaches each T section, allowing selectively the wafer in 2-dimensions. Controlling the laser beam to turn on and off in this way makes it possible to dice even CH2 non-consecutive device patterns. The on/off positions can be controlled with high precision, allowing accurate dicing within ±25 CH1 µm even at stage speeds up to 300 mm per second.

TLASC0034EA Figure 11: Mixed pattern containing both 2 mm and 10 mm square chips

11 Photo 4 shows results from stealth dicing on a wafer with different chip sizes in Figure 11. Only 3 locations of the T section are shown 5. Dicing materials other than silicon because of the limited space available here. Photo 5 shows stealth dicing of free sizes on a silicon wafer. As Stealth dicing also works on other materials besides silicon. Here can be seen here, stealth dicing can cut both curves and triangular are some example of dicing other materials which are currently shapes and the machined quality of the sliced cross section is the under development. same as normal stealth dicing. 5.1 Glass wafers Glass materials currently being used include quartz glass, borosili- cate glass (such as BK7), pyrex, and non-alkali glass, etc. Dicing of soft and hard glass materials is also under study. Glass wafers often be diced while laminated over a silicon wafer, so one method proposed for those cases forms an SD layer on each material by irradiating laser light for silicon material from the silicon substrate side, and laser light for glass material from the glass substrate side while simultaneously applying stress to separate the wafer into small chips. Photo 6 shows samples cut from an actual glass wafer by stealth CH1-1 CH1-2 CH1-3 dicing. These samples still have problems with the cutting quality. Namely, Photo 4: T-shape dicing example the edge straightness on the front surface where the chip edges were cut tends to weave back and forth about ±15 µm. Compared to silicon wafers where the cutting accuracy is about ±2 µm on both front and back surfaces, glass wafers still need improvements to increase their precision.

Photo 5: Free size dicing 100 µm Photo 6 (a): Surface of glass chip cut from glass wafer

50 µm Photo 6 (b): Cross section of glass chip cut from glass wafer

12 green-friendly contribution rendered by stealth dicing. 6. How green-friendly stealth dicing Let’s assume that 1000 blade dicing units were replaced with improves our environment stealth dicing units, the reduction in carbon dioxide (CO2) would be equivalent to 17,000 tons or equivalent to the natural cleansing effect of 1 million 270,000 trees (cedar trees). Trial calculations Mounting stealth dicing engines in equipment cuts their power also show the quantity of required ultrapure water could be slashed consumption by 68 % (under fixed processing conditions). A main by 6 million tons. feature of stealth dicing is that it is a completely dry process and so The tremendous impact in positive environmental effects from needs no pure water. Figuring in the savings from eliminating pure installing stealth dicing engines in equipment is one marker that a water production and waste water processing gives a drop in power semiconductor manufacturer is truly "Aware of energy and the consumption of 77 %. This helped earn stealth dicing the "Superior environment". So using stealth dicing in the wafer dicing process is Energy-Saving Machines" award from the Japan Machinery a huge status mark for semiconductor manufacturers because it Federation (JMF) in February 2007. (Awarded to Tokyo Seimitsu shows they are doing their share to cut harmful loads on the Co., Ltd.). environment and stay green-friendly. The graph in Figure 12 shows the degree of environmental or

■In one year using one stealth dicing unit

■ *1 Reduces ■ *2 Cuts CO2 Hybrid cars Ordinary home emissions Same savings ultrapure Same quantity used by by obtained from 7.6 cars! water quantity by 21 homes! *1 Switching over an ordinary passenger car 17.7t (gasoline) to a hybrid car is estimated as reducing *2 Figure obtained by calculating the 2.34 tons of carbon dioxide emissions per year (at 6,307t water usage by a single average a driving distance of 19,500 kilometers annually, household at 300 tons per year and fuel consumption of 60 % in 10.15 mode).

■So in 10 years using stealth dicing units 25,000 Cuts CO2 Converting this to 20,000 emissions by natural (cedar tree) EqualEqual toto cleansing 15,000 quantities (t) 25,000t 2 EqualEqual ttoo Reduction 1.91.9 millionmillion 10,000 EqualEqual toto 1.271.27 millionmillion treestrees 630,000630,000 treestrees 5,000 in EqualEqual toto treestrees EqualEqual ttoo 380,000380,000 130,000130,000 treestrees treestrees 0 Reduction in CO CO2 20092009 2012 2012 20142014 20172017 20192019 Ultrapure 0 Water 2 million From one stealth dicing unit 4 million Cuts ultrapure water 6 million quantities by 9 million t 8 million

10 million Reduction in ultrapure water quantities (t) Estimated expanded use 100 Units 300 Units 500 Units 1000 Units 1500 Units of stealth dicing units

TLASC0036EA Figure 12: Scale showing how stealth dicing helps our environment

13 7. Conclusion

MEMS devices such as microactuators, silicon microphones, RF MEMS, and optical MEMS devices are already being actively used in diverse fields. As the markets for these devices steadily expand, more technical innovations will be needed from a management perspective to boost productivity and production efficiency as well as giving MEMS devices more functions and higher value. Stealth dicing was originally developed to solve the serious problems faced when trying to dice ultra-thin silicon devices such as semiconductor memories with conventional technology. So when dicing comparatively thick silicon products such as MEMS devices, stealth dicing must form multiple SD layers along the wafer depth. However, forming these multiple SD (stealth dicing) layers takes time and reduces the product throughput. Future work will therefore concentrate on developing machining processes and hardware for improving the throughput of thick silicon wafers as well as expanding the range of devices where stealth dicing can be used.

14 ■Patents (as of April 1, 2013) ●USA: USP 6992026, 7396742, etc. (a total of 48 patents), and 62 patents pending ●Japan: Patent Nos. 3408805, 3626442, 3761565, 3761567, 3761566, 3624909, 3670267, 3790254, 3822626, 3762409, 3867003, 3867107, 3867109, 3867110, 3867101, 3867102, 3867103, 3867100, 3867104, 3867105, 3869850, 3751970, 3867108, 3935187, 3935188, 3990710, 3935186, 3935189, 3990711, 4050534 (a total of 120 patents), and 70 patents pending ●Taiwan: Patent Nos. I250060, I270431, I289890, I278027, etc. (a total of 32 patents), and 54 patents pending ●Europe (EC): Patent No. 1632997, etc. (a total of 28 patents), and 63 patents pending ●Republic of Korea: Patent Nos. KR10-0667460, KR10-0715576, KR10-0749972, KR10-0766727, KR10-0781845, etc. (a total of 37 patents), and 49 patents pending ●China: A total of 62 patents, and 36 patents pending ●Other Countries: Including patents pending in Thailand, Malaysia, India, Philippines, Singapore, and Israel etc.

■References Naoki Uchiyama, "Chapter 2: Fabrication of MEMS", Latest technologies in MEMS materials, Nov. 2007, CMC Publishing Co., Ltd. (published in Japanese) Naoki Uchiyama, "Chapter 9, section 7", 2008 MEMS technology outlook, separate volume of Electronic Journal, Electronic Journal, Inc. (published in Japanese) 1) B. Richerzhagen, D. Perrottet, and Y. Kozuki, "Dicing of wafers by patented water-jet-guided laser: the total damage-free cut", Proc. of the 65th The Laser Materials Processing Conference, 197-200 (2006) 2) P. Chall, "ALSI's Low Power Multiple Beam Technology for High Throughput and Low Damage Wafer Dicing", Proc. of the 65th The Laser Materials Processing Conference, 211-215 (2006) 3) F. Fukuyo, K. Fukumitsu, N. Uchiyama, "Stealth Dicing Technology and Applications", Proc. 6th Int. Symp. on Laser Precision Microfabrication (2005) 4) K. Fukumitsu, M. Kumagai, E. Ohmura, H. Morita, K. Atsumi, N. Uchiyama, "The Mechanism of Semiconductor Wafer Dicing by Stealth Dicing Technology", Proc. 4th International Congress on Laser Advanced Materials Processing (2006) 5) E. Ohmura, F. Fukuyo, K. Fukumitsu, and H. Morita, "Internal modified-layer formation mechanism into silicon with nano second laser", J. Achievement in Materials and Manufacturing Engineering, 17, 381-384 (July-August 2006) 6) Etsuji Ohmura, Masayoshi Kumagai, Kenshi Fukumitsu, Koji Kuno, Makoto Nakano, and Hideki Morita, "Internal Modification of Ultra Thin Sillicon Wafer by Permeable Pulse Laser", Proceeding of the 8th International Symposium on Laser Precision Microfabrication (2007) 7) Masayoshi Kumagai, Naoki Uchiyama, Etsuji Ohmura, Ryuji Sugiura, Kazuhiro Atsumi, Kenshi Fukumitsu, Advanced Dicing Technology for Semiconductor Wafer-Stealth Dicing, Proc. 15th International Symposium on Semiconductor Manufacturing (2006)

15 SDE (Stealth Dicing) is a registered trademark of Hamamatsu Photonics.

* The contents of this document are current as of MAR, 2014. The contents are subject to change without prior notice due to improvement. HAMAMATSU PHOTONICS K.K. HAMAMATSU PHOTONICS K.K., Electron Tube Division 314-5, Shimokanzo, Iwata City, Shizuoka Pref., 438-0193, Japan, Telephone: (81)539/62-5248, Fax: (81)539/62-2205 TLAS9005E05 MAR. 2014 IP