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Technical Stealth Dicing Information for MEMS

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Technical Stealth Dicing Information for MEMS Stealth Dicing Technical Information for MEMS 2 Table of Contents 1. Introduction 2. Problems with dicing in MEMS fabrication processes 2.1 Grinding wheel type blade dicing 2.2 Making dicing a completely dry process 3. Stealth dicing technology 3.1 Basic principle of stealth dicing 3.2 Internal-process laser dicing versus surface-process laser processing 3.3 Range of thermal effects on MEMS devices during internal laser process 3.4 Checking thermal effects on device characteristics 3.5 Limitations when using stealth dicing 4. Stealth dicing boosts profits 4.1 Benefits from a 10 µm kerf width 4.2 Benefits when dicing irregular chip shapes 5. Dicing materials other than silicon 5.1 Glass wafers 6. How green-friendly stealth dicing improves our environment 7. Conclusion "Stealth dicing features" that will completely rewrite conventional dicing concepts Wafer dicing Laser dicing Blade dicing Laser ablation dicing Stealth dicing Processing method Grinding cutting and process Surface absorption laser process Internal absorption laser process (melting, evaporation) (locally selective) Water (cooling / cleaning) Required Required Not required Chipping Occurs Occurs Does not occur Debris generation Generates Generates Does not generate T-shape and round shape dicing Not possible Possible in certain cases Possible High-speed ultra-thin wafer dicing Might be possible in certain cases Possible in certain cases Possible Chip yield Not so good Not so good Good Processing speed Not so good Not so good Good Thermal effect on device Affected (including residual stress) Affected (HAZ*) Not affected * HAZ: Heat Affective Zone 3 1. Introduction 2. Problems with dicing in MEMS fabrication processes Various different kinds of technologies such as mechanical engineering, quantum mechanics, electrical engineering, chemistry, and optics that were thought of as different fields until recently 2.1 Grinding wheel type blade dicing were merged on a semiconductor fabrication process as microma- Major problems that must be avoided during dicing of MEMS chining technology. This new technology offers tremendous devices with fragile structures include contamination and stress possibilities that are starting to gather much attention. This technol- loads on the functional elements. The following are inevitable ogy has gradually grown along with the spread of etching technol- problems with the dicing process used in typical blade dicing ogy since it could freely form thin film structures, girders and processes. hollow structures with fine accuracy to the micro level on wafers. 1Problem with wet processes These capabilities appealed to the imaginations of MEMS (micro · Fluid pressure applies stress loads on the structure due to use electro mechanical system) designers who are now starting to of cooling water and rinse water during dicing. create totally new functional devices. · Functional elements are re-contaminated by foul cutting fluid Stealth dicing is a completely new laser dicing technology. Stealth · Requires adding a protective film for protecting device dicing offers amazing advantages since it is a "completely dry structures from water and foul water as well as a process to process" yet generates "no debris" and has "zero kerf loss". This remove that film technology was especially developed for the purpose of high-speed 2Problems with contact type processes yet high-quality dicing of ultra-thin semiconductor wafers and its · Contact type cutting processes apply a vibrating load to the features are equally effective in dicing processes for MEMS structure devices. Stealth dicing is already being used for mass producing Figure 1 shows problems that occur when an MEMS device having MEMS devices and is on its way to becoming an industry standard a membrane structure is cut by blade dicing. Photo 1 shows for MEMS device production. damage to membrane structures due to fluid pressure during blade This technical material covers problems encountered in MEMS dicing. dicing as well as principles and processes involved in stealth dicing technology. It also offers a brief look at trends in developing new types of stealth dicing for use on materials other than silicon. Diamond grinding wheel Cooling / rinse water Membrane crack Chipping Photo 1: Membrane damage due to fluid pressure Debris generation Structural damage Debris Kerf loss adhesion TLASC0022EA Figure 1: Problems with blade dicing 4 2.2 Making dicing a completely dry process Stealth dicing offers both these features 1 and 2 described above. When dicing an MEMS device, dicing technology is needed that In dicing technology using lasers, the ablation method has long applies minimal stress to the delicate structures inside the MEMS been studied as a laser process method 1) 2). Laser ablation, device. At the same time, some measures are also needed to however, produces debris contaminants during processing so prevent the device structures from particle recontamination. These pre-processing is needed to coat a protective film for protecting the problems can be eliminated by switching to a dicing process with device structures from these contaminants, and post-processing the following features: such as wet washing is also required. 1Fully dry processing: Prevents defects caused by wet process The next section briefly describes how stealth dicing is performed and reduces man-hours needed for production/inspection in a completely dry process. 2Non-contact dicing process: Eliminates stress applied to the device structures due to vibration accompanying the cutting process 3. Stealth dicing technology in the interior of the wafer, which extend towards both surfaces of the wafer. These cracks are an indispensable element for dividing the wafer into chips and should not twist broadly around the chip 3.1 Basic principle of stealth dicing or be prevented from developing towards both surfaces. When In stealth dicing, a laser beam at a light wavelength semitranspar- cutting a thick silicon wafer device such as MEMS devices, it is the ent to the material is focused on a point inside that material to form most important step to form SD layers and joint them vertically a cleaving start point (transformed area: hereafter called SD layer), while making multiple scans depth-wise in the wafer, so that an and external pressure then applied to the wafer to separate it into optimal SD layer for cutting is formed. multiple chips 3) 4). How these cracks relate to the SD layer is shown in Figure 3, along This technology therefore includes two processes. One is a "laser with the three states that we should understand for deciding the process" to form a cleaving start point (SD layer) on the interior of processing conditions. the wafer for separating it into chips; and the other is a "separation SD layers can be made into the three states according to the process" to divide the wafer into small chips. Figure 2 above shows purpose and application. These states can be combined to form an an overview of the laser process. ideal combination. Optimal processing conditions can be found via the device state such as the wafer thickness, chip shape, and 1Step 1 - Laser process whether a metallic film is used, etc. Once these conditions are A laser beam is focused on points inside the wafer to form an SD found they can be systematized in a database for use according to layer for cutting the wafer. Cracks are also formed on this SD layer the particular user and device. Laser beam SD layer and cracks Scan direction Wafer Tape TLASC0023EA Figure 2: Step 1 - Laser process a) ST: Stealth b) HC: Half-cut c) BHC: Bottom side half-cut Cracks have not reached top or bottom Cracks have reached laser irradiation surfaces (internal crack state) surface (surface crack state) SD layer SD layer SD layer Cracks Cracks Cracks Cracks have reached laser irradiation bottom surface (surface crack state) TLASC0025EA Figure 3: Interrelation of SD layer and cracks formed in laser process 5 An overview of the "separation process" is next shown in Figure 4. towards the wafer periphery, so that a pulling or tensile stress propagates along the wafer and the stress concentrates at the tip of 2Step 2 - Separation process the crack. This concentrated stress causes the crack to instantane- Expanding a tape-mounted wafer already formed with an SD layer ously reach the wafer surface, and the wafer then splits into small towards the periphery of the wafer applies a tensile stress to the chips. 4) internal cracks in the wafer. This stress causes the internal cracks Photo 2 shows a cross section of an MEMS chip having a to develop towards both surfaces of the wafer and separates the membrane structure that was cut by stealth dicing. Both the front wafer into small chip shapes. and back surfaces of the chip have sharp and clean dicing lines Figure 5 shows a schematic view of the process up to separating with no chipping. The membrane structure in the chip center the wafer into chips by extending the SD layer cracks formed section also shows good quality dicing with no traces of damage or inside the wafer. debris that known to cause defects. The tape expansion process Forming an HC (half-cut) or a BHC (bottom side half-cut) during effectively applies stress to the crack tips without causing mutual forming of the SD layer will make it easier to separate the wafer interference with chips adjacent to each other. into chips. When the tape is then expanded towards the periphery of the wafer while in this state, the HC or BHC surface is pulled Separated chip Compression stress Tape expansion Tap expansion Tensile stress TLASC0024EA Figure 4: Step 2 - Separation process Wafer Crack extension Tensile stress Tape expansion BHC Tape Tape expansion Wafer Crack extension Tensile stress Tape expansion Tape Tape expansion Crack has reached upper surface Wafer Tensile stress Tape expansion Tape Tape expansion TLASC0026EA Figure 5: Crack extension principle Photo 2: Photograph of chip cut by stealth dicing 6 3.2 Internal-process laser dicing versus surface- that point.
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