DOCSLIB.ORG

WAFER DICING ( an Introduction to the Process )

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
WAFER DICING ( an Introduction to the Process ) WAFER DICING ( An introduction to the Process ) Presented By : MANISH CHOPRA September 13 , 2007 Continental Device India Limited 1 Process Engineer 1 What is Process ? September 13 , 2007 Continental Device India Limited 2 2 INPUT OUTPUT Process RESOURCES “ Any activity or set of activities that uses resources to transform inputs to output can be considered as Process” September 13 , 2007 Continental Device India Limited 3 3 Type of Semiconductor manufacturing flow • Front end (Wafer fabrication ) • Back end (Assembly, Test and Packaging) September 13 , 2007 Continental Device India Limited 4 4 Front End • The "front-end" is wafer processing which is performed in a Wafer Fab area. • A Fab is one of the most complex industrial facilities to be found anywhere. A state-of-the-art Fab, costing over $1 billion. • It has the cleanest environment in the world - many times cleaner than the best hospital operating theater. • The process of wafer fabrication is a series of 16-24 loops, each putting down a layer on the device. September 13 , 2007 Continental Device India Limited 5 5 Major steps in Front end process Wafer preparation Oxidation Photolithography Diffusion Deposition Metallization Passivation Back Grinding September 13 , 2007 Continental Device India Limited 6 6 Back End Process • The "back-end" is Test, Assembly and Packaging, where the finished wafer is split up into individual die (chips) which are then assembled into packages which can be handled in the final applications. • Full functional Electrical test is performed at both wafer and package level to ensure outgoing quality September 13 , 2007 Continental Device India Limited 7 7 Major steps involved in Back End Process Wafer Probing Die singulation (Dicing) Die Bonding Wire Bonding Molding Lead finish Trim Form Electrical Testing Marking September 13 , 2007 Continental Device India Limited 8 Packing 8 Wafer Dicing / Wafer Singulation Process of reducing a wafer containing multiple identical (Die) chips to dice . In our Process , a 4’’ wafer gives up to 100 k Devices . Kiru September 13 , 2007 Continental Device India Limited 9 9 DICING is not a Cake walk! Process Critical Parameters 30000 RPM Spindle Revolution 25 mil Exposure of Blade Exposure 1 mil Blade Thickness Work piece (Wafer ) Thickness of 8 mil 100 k die / wafer September 13 , 2007 Continental Device India Limited 10 10 5 W’s & 1 H (DICING PROCESS) • What • When •Why •Who • Where •How September 13 , 2007 Continental Device India Limited 11 11 Turtle diagram - Elements of a Process RESOURCES CONTROLS OUTPUT INPUT Dicing Process METHOD KEY CRITERIA chip (HOW) September 13 , 2007 Continental Device India LimitedRELIABILITY 12 12 RESOURCES(WHAT) 1. DAD321 DICING SAW 2. DIAMOND BLADE 3. MYLAR 4. FRAME 5. DI WATER 6. COMPRESSED AIR 7. NITROGEN 8. IONISER 9. TEFLON / VACCUM TWEEZER 10. MICROWASHER September 13 , 2007 Continental Device India Limited 13 Back Next 13 PROCEDURE(HOW) 1. TECHNIQUES 2. DICING PROCESS FLOW 3. METHOD Next September 13 , 2007 Continental Device India Limited 14 14 KEY CRITERIA 1. SEPERATION OF DIE WITH REQUIRED DIMENSION FROM WAFER 2. YIELD MONITORING(THROUGHPUT) 3. CUT QUALITY 4. COST TO PROCESS back September 13 , 2007 Continental Device India Limited 15 15 CONTROL 1. M/C CONTROL 2. SPC Back September 13 , 2007 Continental Device India Limited 16 16 M/C Control • Programmable stopping of machine (based on requirement) for online inspection of product. • Monitoring through Camera. CONTROL September 13 , 2007 Continental Device India Limited 17 17 INPUT DIFFUSED WAFER BACK September 13 , 2007 Continental Device India Limited 18 18 OUTPUT DICED WAFER OR SINGULATED WAFER Back September 13 , 2007 Continental Device India Limited 19 19 CHIP Good Die Bad Die September 13 , 2007 Continental Device India Limited 20 20 Conversions • 1 mil = 25.4 um • 1 um =0.040 mil • 1 inch=25.4 mm=25400 um=1000mil • 1 mm =40mil September 13 , 2007 Continental Device India Limited 21 21 Nomenclature in DICING Kerf Scribe Path Chip September 13 , 2007 Continental Device India Limited 22 22 Nomenclature in Dicing • Scribe path- Thin non-functional spacing in between the functional parts of the chips, where a saw can safely cut the wafer without damaging the chip. • Dicing tape (Mylar) is a PVC sheet with synthetic adhesive on one side to hold both the wafer frame and the wafer. BACK September 13 , 2007 Continental Device India Limited 23 23 Nomenclature in Dicing Wafer frame may be made of plastic or metal, but it should be resistant to warping, bending, corrosion, and heat. Kerf width is defined as the average width of the cut line plus the error attributed to micro chipping. Note :The singulated dice may be left attached to the wafer tape for pick-and-place during die attach or may be individually kept in waffle packs for future assembly. September 13 , 2007 Continental Device India Limited 24 Back Turtle 24 DICING TAPE CONSTITUENTS September 13 , 2007 Continental Device India Limited 25 25 DAD 321 September 13 , 2007 Continental Device India Limited 26 26 DAD 321 Specifications Users perform workpiece loading, alignment and unloading manually. Auto-alignment Air driven Spindle Vaccum Chuck Online monitoring Auto stopping as per Program Workpiece size - 4,5,6 inch September 13 , 2007 Continental Device India Limited 27 27 Blade Nomenclature September 13 , 2007 Continental Device India Limited 28 28 Dicing Blade • A diamond blade is a ring composed of abrasive grits (diamond particles) held together by a binder - either nickel or phenolic resin or metal-powder sintering. September 13 , 2007 Continental Device India Limited 29 29 Parameters for Selecting a Blade ¾ Choosing the right binder ¾ Diamond selection ¾ Dressing After Dressing Before Dressing September 13 , 2007 Continental Device India Limited 30 30 Blade Tradeoff September 13 , 2007 Continental Device India Limited 31 31 Blade Sharpening action September 13 , 2007 Continental Device India Limited 32 32 Blade which we are using? • Disco Blade: Turtle NBC – ZH –1 04 F –SE - K44 - 27H D C B Series Kerf width Aluminium Hub 0.8-1.0 mil Blade Exposure Grit Concentration 20-25 mil low Conc. Grit size Code Grit Size: Mesh size=3000 Mesh size # 3000 Size=2/6 um Size # 2/6 um I.D=19.05mm O.D=55.56mm Brittle Bond Low Backside Chipping Sharp Edge Hub type Customized Inspection September 13 , 2007 Continental Device India Limited 33 33 Techniques – Scribing and Breaking – Mechanical sawing (Dicing Saw) – Laser cutting. September 13 , 2007 Continental Device India Limited 34 34 Application characteristics September 13 , 2007 Continental Device India Limited 35 35 Cost of Process September 13 , 2007 Continental Device India Limited 36 36 Process Flow Wafer DICING Mounting Full-Cut Dicing Return Dicing tape is The dicing saw dices The wafer is applied to the the wafer to Die returned to the backside of wafer singulation cassette. September 13 , 2007 Continental Device India Limited 37 37 Elements in Wafer Dicing September 13 , 2007 Continental Device India Limited 38 38 Method • Application of tape to the backside of Wafer. • Setting up the wafer on the Dicing Saw chuck. • Selecting the cutting program for the device. September 13 , 2007 Continental Device India Limited 39 39 Method Checking the blade status. Aligning the wafer in both the channels. Execute the cutting. September 13 , 2007 Continental Device India Limited 40 40 Method • Remove the Diced Wafer from Chuck. • Clean the Diced Wafer using Micro wash. NEXT September 13 , 2007 Continental Device India Limited 41 41 DICING PROGRAM • MACHINE AND DEVICE PARAMETERS THAT CAN AFFECT THE DICING PROCESS:- • CRITICAL MACHINE PARAMETERS:- 1.Air pressure--85-120psi 2.DI water pressure--40-100psi 3.N2 pressure--30-100psi 4.DI water conductivity--<0.2uS 5.Room temp = +/- 2 degree Celsius. 6.SpindleSeptember 13 , 2007 r.p.m-30000rpm Continental Device India Limited 42 42 DEVICE PARAMETERS:- 1.Work size (wafer diameter) 2.Work thickness (wafer thickness) 3.Chip size 4.Tape thickness Blue mylar-2.8-3.0mil white mylar-4.5-5.0mi 5..Blade height For Blue myler-0.0013-0.0020inch For white myler-0.0030-0.0035inch 6.Feed rate(cut speed)-3inch/s BACK September 13 , 2007 Continental Device India Limited 43 43 Issues affecting wafer mounting process / DICING 1.Air bubbles between Mylar and wafer. 2.Metal mounds at back surface of wafer. 3.Wrinkles in Mylar 4.Wafer cracked in grinding 5.Foreign particles between wafer and Mylar. September 13 , 2007 Continental Device India Limited 44 44 Issues affecting wafer mounting process / DICING 6.Non uniform back surface 7.Particles on the mounting chuck 8.Warpage 9. Inadequate mounter temperature 10. Weak adhesion of tape September 13 , 2007 Continental Device India Limited 45 45 Effects of wafer mounting Process on Dicing – Chips fly off during dicing and microwash. – Chip loss – Crack at the time of fixing the wafer in dicing machine. – Blade breakage. – Back or front side chipping. September 13 , 2007 Continental Device India Limited 46 46 Why Dressing? • To smoothen the exposed diamond grits of blade radially for fine quality cut. • To check the effect of loading of substrate on blade. September 13 , 2007 Continental Device India Limited 47 47 Dressing Program on Dresser Board Dresser board:- Material - Silicon Carbide Grit size - 30 microns Thickness - 1mm Depth of cut – 22 mils Feed Rate No. of cuts 5 mm/sec 2 at 30,000 rpm 10mm/sec 2 at 30,000 rpm September 13 , 2007 Continental Device India Limited 48 48 Precutting •Smoothen the exposed Diamond grits •Minimising the Loading effect
Load more

Recommended publications
  • Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art
    Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art Dapeng Liu Fig. 1 3D SiP with wire bonds and flip-chip bumps [1] Mechanical Engineering, State University of New York at Binghamton, developed. From the geometry point of view, annular or fully P.O. Box 6000, filled vias with different taper angles were manufactured [2]. The Binghamton, NY 13902 filling material might be copper (Cu), tungsten (W), polysilicon e-mail: [email protected] [3], solder material with Cu particles [4], and conductive adhesive [5], etc. Some TSVs serve as electrical connections while some Seungbae Park1 are designed as thermal TSVs (TTSVs) to dissipate the heat and improve thermal management [6,7]. Various manufacturing proc- Mechanical Engineering, esses have been studied to create a void-free TSV as quickly and State University of New York at Binghamton, cheaply as possible. At the current stage, although 3D packages P.O. Box 6000, with TSVs have not been widely used in products, electronic Binghamton, NY 13902 packages with silicon interposers containing TSVs (such as Xilinx e-mail: [email protected] Virtex-7 FPGA [8], etc.) are already on the way to market. Because the coefficient of thermal expansion of the silicon inter- poser is closer to the die, the silicon interposer can prevent the brit- tle ultra-low-j dielectric material of the die from cracking. Three-dimensional (3D) packaging with through-silicon-vias Packages with TSV interposers are regarded as 2.5D packages. Fig- (TSVs) is an emerging technology featuring smaller package size, ure 2 shows a cross section image of the Xilinx Virtex-7 FPGA higher interconnection density, and better performance; 2.5D product, and the Si interposer with TSVs can be clearly seen.
    [Show full text]
  • Dicing 101: LEDS, Laser, MEMS Trends Driving WLP and 3D Direct Copper Bonding for High Density Applications Electroless Plating
    The International Magazine for the Semiconductor Packaging Industry Volume 15, Number 6 November December 2011 DicingDicing 101:101: LEDS,LEDS, Laser,Laser, MEMSMEMS TrendsTrends DrivingDriving WLPWLP andand 3D3D DirectDirect CopperCopper BondingBonding forfor HighHigh DensityDensity ApplicationsApplications ElectrolessElectroless PlatingPlating forfor ImprovedImproved TesTestt SolderSolder inin thethe AgeAge ofof 3D3D InternationalInternational DirectoryDirectory ofof SolderSolder andand FluxFlux SuppliersSuppliers CONTENTS November December 2011 Volume 15, Number 6 The International Magazine for Device and Wafer-level Test, Assembly, and Packaging Addressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS, The International Magazine for the Semiconductor Packaging Industry Volume 15, Number 6 November December 2011 MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century. Dicing 101: LEDS, Laser, MEMS FEATURE ARTICLES Trends Driving WLP and 3D Direct Copper Bonding for High Density Applications Electroless Plating for Improved Testt Solder in the Age of 3D Innovation Trends Driving WLP and 3D Packaging 14 InternationalInternational DirectoryDirectory ofof SolderSolder andand FluxFlux SuppliersSuppliers Steve Anderson, STATS ChipPAC Direct Copper Bonding Of High-Density 3D Assemblies 18 Gilbert Lecarpentier, SET, Marc Legros and Mayerling Martinez, CEMES-CNRS, In the midst of tremendous technological changes Alexis Farcy and Brigitte Descouts, STMicroelectronics, Emmanuel
    [Show full text]
  • Dicing Tape Information
    ULTRON SYSTEMS e Dicing Tape minitron elektronik gmbh Type Description Adhesion Page Silikontrennmittelfreie Folien 1003R Blue Adhesive Plastic Film (PVC), Silicone Release Agent-Free, High 370 / 550 * 6 Adhesive Strength, 135 µm thick, no backing film. Mainapplication: Dicing of Silicon and Ceramicsubstrates 1004R Blue Adhesive Plastic Film (PVC), Silicone Release Agent- 170 / 50 * 7 Free,Medium- High Adhesive Strength, 130 µm thick, no backing film- Mainapplication: Dicing of Silicon and Ceramicsubstrates 1005R Blue Adhesive Plastic Film (PVC), Silicone Release Agent-Free, Medi- 100 / 150 * 8 um-High Adhesive Strength, 15 µm thick, no backing film. Mainapplication: Dicing of Silicon and Ceramicsubstrates 1007R Blue Adhesive Plastic Film (PVC), Silicone Release Agent-Free, Medi- 76 / 130 * 9 um Adhesive Strength, 80 µm thick, no backing film Mainapplication: Dicing of Silicon wafers 1008R Blue Adhesive Plastic Film (PVC), Silicone Release Agent-Free, Medi- 100 / 160 * 10 um-High Adhesive Strength, 80 µm thick, no backing film Mainapplication: Dicing of Silicon wafers 1009R Blue Adhesive Plastic Film (PVC), Silicone Release Agent-Free, Low 34 / 85 * 11 Adhesive Strength, 80 µm thick, no backing film Mainapplication: Dicing of Silicon wafers 1011R Blue Adhesive Plastic Film (PVC), Silicone Release Agent-Free, Very- 19 / 3 * 12 Low Adhesive Strength, 80 µm thick, no backing film Mainapplication: Dicing of Silicon wafers 1030R Hochreine „Fisheye-free“ Sägefolie aus PVC, Klebkraft: niedrig, 50 / 70 * 13 Dicke 80µm, mit Schutzfolie, Hergestellt in Klasse 100 Reinraum Mainapplication: Wafers backgrinding * Adhesion after 30min and 4h mesured on Si, in g/5mm Type Description Adhesion Page UV-sensitive Tape 1020R UV-sensitive tape (PVC), 95 µm thick, with backing film.
    [Show full text]
  • Low‑Cost Silicon Wafer Dicing Using a Craft Cutter
    Microsyst Technol DOI 10.1007/s00542-014-2198-4 TECHNICAL PAPER Low-cost silicon wafer dicing using a craft cutter Yiqiang Fan · Arpys Arevalo · Huawei Li · Ian G. Foulds Received: 14 April 2014 / Accepted: 23 April 2014 © The Author(s) 2014. This article is published with open access at Springerlink.com Abstract This paper reports a low-cost silicon wafer dic- than three decades (Efrat 1993; Takyu et al. 2006; Zhou ing technique using a commercial craft cutter. The 4-inch et al. 2013). However, due to the natural physical contact silicon wafers were scribed using a crafter cutter with a between the dicing blade and the wafer’s surface, chip- mounted diamond blade. The pre-programmed automated ping and cracking were hard to avoid. When the indus- process can reach a minimum die feature of 3 mm by try started to use thinner wafers, which are more fragile, 3 mm. We performed this scribing process on the top pol- mechanical dicing was no longer suitable for the wafer ished surface of a silicon wafer; we also created a scribing dicing process. In the mean time, with the development method for the back-unpolished surface in order to protect of laser techniques, laser ablation was found to be a use- the structures on the wafer during scribing. Compared with ful alternative for performing wafer dicing (Jianhua et al. other wafer dicing methods, our proposed dicing technique 2007; Kumagai et al. 2007; Venkatakrishnan et al. 2008). is extremely low cost (lower than $1,000), and suitable for Compared to mechanical wafer dicing, laser dicing usu- silicon wafer dicing in microelectromechanical or micro- ally has a higher dicing speed, no physical contact, and a fluidic fields, which usually have a relatively large die narrower dicing street.
    [Show full text]
  • Stealth Dicing Technology and Applications
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------ TECHNICAL INFORMATION ------------------------------------------------------------------------------------------------------------------------------------------------------------------ MAR. 2005 Stealth Dicing Technology and Applications 1. Introduction By optimizing the laser and optical system characteris- tics to cause the nonlinear absorption effect just in the Stealth dicing process has now evolved to a practical vicinity of the focal point inside the semiconductor wafer, level that makes it the next generation in dicing technol- only localized points in the wafer can be selectively la- ogy. Stealth dicing offers the following advantages over ser-machined without damaging the front and back sur- conventional dicing methods. faces inside semiconductor wafer. · High-speed dicing The semiconductor wafer can be diced by using a stage · High quality (no chips & dust-free) or similar mechanism that moves the relative positions of · Superior breakage strength (ultra-thin chips) the laser beam and wafer in order to scan the wafer at · Low kerf loss (better chip production yield) high speeds according to the desired dicing pattern. · Completely dry process Fig. 2 shows spectral transmittance characteristics1) of a · Low running costs monocrystalline silicon wafer not doped with any impuri- Stealth dicing was initially developed for use in ties, measured at a room temperature environment.
    [Show full text]
  • Damage Free Dicing Method for MEMS Devices Letter
    Letter Damage Free Dicing Method for MEMS Devices ＊ Yoshinori Matsumoto Member ＊ Yoshio Awatani Non-member ＊ Kei Kato Non-member This paper presents a dicing method for MEMS devices without dameges during the dicing process. The method is based on bonding and detachment of a glass cap plate by using thermoplastic adhesive. Sand blast technique was used for the fabrication of glass cap plate which has concavities in the depth of 100µm. The thermoplastic adhesive was screen printed on the glass plate. The plate was thermocompression-bonded to silicon wafer at 210℃ and diced to individual chips without damages from water or dicing dusts. The chip was mounted in the package while the glass cap was removed at 330℃. Keywords : dicing, damage free, MEMS, thermocompression-bonding, thermoplastic adhesive 1. Introduction Wafer bonding In recent years, many MEMS devices have been developed in many fields such as sensor, Optical MEMS, RF-MEMS, etc. Release process is a key process for the fabrication of micro mechanical structures(1). The release process is performed in wafer process because of mass productivity and reducibility, then the wafer is diced to individual chips. However, conventional dicing machine uses water to cool rotating blade during the dicing process. The water or dicing dusts damage the micro structures and contaminate the MEMS devices. Wafer dicing Covering the silicon wafer with UV-tape during the dicing process can protect the surface of MEMS devices. The tape’s adhesive strength can be reduced with UV light after dicing, but weak adhesive force is remained on the tape. The weak force is enough to break the micro mechanical structures such as accelerometer and optical mirror, etc.
    [Show full text]
  • Backside Chippings Improvement Through Wafer Dicing Parameter Optimization and Understanding the Anistropic Silicon Properties
    Journal of Engineering Research and Reports 20(7): 144-152, 2021; Article no.JERR.68094 ISSN: 2582-2926 Backside Chippings Improvement through Wafer Dicing Parameter Optimization and Understanding the Anistropic Silicon Properties Aiza Marie E. Agudon1 and Bryan Christian S. Bacquian1* 1STMicroelectronics, Inc., Calamba City, Laguna, 4027, Philippines. Authors’ contributions This work was carried out in collaboration among all authors. All authors read and approved the final manuscript. Article Information DOI: 10.9734/JERR/2021/v20i717350 Editor(s): (1) Dr. Harekrushna Sutar, Indira Gandhi Institute of Technology, India. (2) Dr. Neha Munjal, Lovely Professional University, India. (3) Dr. Guang Yih Sheu, Chang-Jung Christian University, Taiwan. Reviewers: (1) Himanshu Dehra, India. (2) Anutsek Sharma, University of Kiel, Germany. Complete Peer review History: http://www.sdiarticle4.com/review-history/68094 Received 15 March 2021 Original Research Article Accepted 20 May 2021 Published 25 May 2021 ABSTRACT Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers.
    [Show full text]
  • Adoption of Hybrid Dicing Technique to Minimize Sawing-Induced Damage During Semiconductor Wafer Separation
    Materials Transactions, Vol. 58, No. 4 (2017) pp. 530 to 534 ©2017 The Japan Institute of Metals and Materials Adoption of Hybrid Dicing Technique to Minimize Sawing-Induced Damage during Semiconductor Wafer Separation Seong-Min Lee* Department of Materials Science & Engineering, Incheon National University, 119 Academy-ro, Yeonsu-gu, Incheon, 406–772, South Korea This article demonstrates that the chipping damage resulting from silicon wafer separation can be more effectively suppressed by the adoption of hybrid dicing (a duel process that uses laser ablation prior to mechanical sawing) than single dicing, such as sawing. This work shows that the adoption of the hybrid dicing technique induces sacricial fracture at the laser-induced groove tip to save the regions outside of the groove formed along the scribe region of the wafer. Particularly, this study details how a pre-existing groove (i.e., a laser-induced groove) on the front surface of the wafer interacts with the saw blade penetration-induced trench during the second step of the hybrid dicing process. Ac- cording to the experimental results, the magnitude of the chipping damage in the chips diced from a wafer including a laser-induced groove with a larger aspect ratio was more effectively reduced at a more rapid sawing velocity. However, since a laser-induced groove with a larger aspect ratio could also have a bigger curvature in its tip, adopting a groove with the optimum shape was necessary for effective prevention of dicing-in- duced damage during hybrid dicing. [doi:10.2320/matertrans.M2016366] (Received October 18, 2016; Accepted January 26, 2017; Published February 24, 2017) Keywords: semiconductor, wafer, silicon, chip, dicing, reliability 1.
    [Show full text]
  • A Study of Integrated Circuit Dicing Tape When Used in a Plasma Dicing Environment (Sept 2019)
    TCPMT-2019-390.R1 1 A study of Integrated Circuit Dicing Tape when used in a Plasma Dicing Environment (Sept 2019) Harry Fulton, Oliver Ansell, Janet Hopkins, Martin Hanicinec, Takuo Nishida and Taku Umemoto, Lijie Li, Member, IEEE Abstract— The main objective of this study was to establish which of the many dicing tapes used in the semiconductor industry, would be most suitable for use in plasma dicing. Tape design over the past 40 years has continually evolved through advancements in both dicing technologies and the incessant revision of integrated circuit packaging. Die singulation has traditionally been accomplished using a diamond saw, laser-based technology or combinations of both. The stress on dicing tape was therefore limited to fatigue through the physical nature of saw dicing or heat energies induced during laser dicing. These processes do not expose dicing tape to either high vacuum or a variety of plasma chemistry. This investigative work is a continuation of studies examining dicing tape behavior when employed for use in plasma dicing. Results show that Polyolefin (PO) UV-tape with low to medium adhesion strength exhibit the greatest resilience in harsh plasma etch conditions and that efficient photoinitiated cross-linking (or curing) of the adhesive is triggered if directly exposed to the photonic energies present in a pure SF6 plasma or full plasma dicing process. However, the post plasma dice, post UV cure adhesive strength can still be minimized if the tape manufacturers recommended time limitations between tape mount, plasma dice and the die pick-up process are adhered to. Index Terms— dicing, plasma, singulation, UV-tape, anti-ESD I.
    [Show full text]
  • Multi-Project Reticle Floorplanning and Wafer Dicing∗
    Multi-Project Reticle Floorplanning and Wafer Dicing∗ Andrew B. Kahng, Ion Mandoiu˘ †, Qinke Wang, Xu Xu, and Alex Z. Zelikovsky‡ CSE Department, UC San Diego, La Jolla, CA 92093-0114 †CSE Department, University of Connecticut, 371 Fairfield Rd., Unit 1155, Storrs, CT 06269-1155 ‡CS Department, Georgia State University, University Plaza, Atlanta, Georgia 30303 fabk,qiwang,[email protected], [email protected], [email protected] ABSTRACT 1. INTRODUCTION Multi-project Wafers (MPW) are an efficient way to share the rising As VLSI feature size continues to shrink in the sub-wavelength costs of mask tooling between multiple prototype and low produc- regime, mask costs are predicted to skyrocket, driven up by the tion volume designs. Packing the different die images on a multi- pervasive use of such advanced Reticle Enhancement Technologies project reticle leads to new and highly challenging floorplanning (RET) as Optical Proximity Correction (OPC) and Phase Shifting formulations, characterized by unusual constraints and complex Masks (PSM) [1, 2, 3]. Indeed, mask cost is predicted to more objective functions. In this paper we study multi-project reticle than double at each technology node and reach $10 million by the floorplanning and wafer dicing problems under the prevalent side- end of the decade [3]. These high mask costs push prototyping and to-side wafer dicing technology. Our contributions include prac- low volume production designs at the limit of economic feasibility, tical mathematical programming algorithms and efficient heuris- increasingly motivating the use of Multiple Project Wafers (MPW), tics based on conflict graph coloring which find side-to-side wafer or “shuttle” runs, which allow customers to share the cost of mask dicing plans with maximum yield for a fixed multi-project reticle tooling [4].
    [Show full text]
  • Metallic Glass Coating for Improving Diamond Dicing Performance Jinn P
    www.nature.com/scientificreports OPEN Metallic glass coating for improving diamond dicing performance Jinn P. Chu1,2*, Bo‑Zhang Lai1, Pakman Yiu1,2, Yu‑Lin Shen3 & Chia‑Wei Chang1 This is the frst report on the coating of diamond dicing blades with metallic glass (MG) coating to reduce chipping when used to cut Si, SiC, sapphire, and patterned sapphire substrates (PSS). The low coefcient‑of‑friction (CoF) of Zr‑based MG‑coated dicing blades was shown to reduce the number and size of chips, regardless of the target substrate. Overall, SiC, sapphire and PSS were most afected by chipping, due to the fact that higher cutting forces were needed for the higher hardness of SiC, sapphire and PSS. Compared to the bare blade, the MG coating provided the following reductions in chipping area: Si (~ 23%), SiC (~ 36%), sapphire (~ 45%), and PSS (~ 33%). The proposed coating proved particularly efective in reducing chips of larger size (> 41 µm in chipping width), as indicated by an ~ 80% reduction when cutting sapphire. Small variations in kerf angle and depth demonstrate the durability of the coated blades, which would no doubt enhance consistency in dicing performance and extend the blade lifespan. Finite‑element modeling revealed signifcant reductions in tensile stress and elastic–plastic deformation during dicing, thanks to a lower CoF. Diamond abrasive blades are widely used to cut silicon, SiC, and sapphire dies in the manufacture of semicon- ductors and optoelectronic devices 1–3. Te brittleness of these hard workpieces inevitably leads to chipping and/ or other types of damage, which might also give rise to failure in dies and chips, eventually causes yield loss 4–6.
    [Show full text]
  • Investigation on the Edge Chipping in Ultrasonic Assisted Sawing of Monocrystalline Silicon
    micromachines Article Investigation on the Edge Chipping in Ultrasonic Assisted Sawing of Monocrystalline Silicon Jianyun Shen, Xu Zhu * , Jianbin Chen, Ping Tao and Xian Wu College of Mechanical Engineering and Automation, Huaqiao University, Xiamen 361021, China; [email protected] (J.S.); [email protected] (J.C.); [email protected] (P.T.); [email protected] (X.W.) * Correspondence: [email protected]; Tel.: +86-1870-297-7299 Received: 14 August 2019; Accepted: 13 September 2019; Published: 16 September 2019 Abstract: Monocrystalline silicon is an important semiconductor material and occupies a large part of the market demand. However, as a hard-brittle material, monocrystalline silicon is extremely prone to happen edge chipping during sawing processing. The edge chipping seriously affects the quality and performance of silicon wafers. In this paper, both conventional and ultrasonicassisted sawing tests were carried out on monocrystalline silicon to study the formation mechanism of edge chipping. The shape and size of edge chipping after sawing process were observed and measured. The experimental results demonstrated that different sawing processes present different material removal modes and edge quality. The mode of crack propagation was continuous cracks in conventional sawing process, while the expansion mode in ultrasonic assisted sawing was blasting microcracks. This results in the cutting force of ultrasonic assisted sawing becomes much smaller than that of conventional sawing process, which can reduce the size of edge chipping and improve the quality of machined surface. Keywords: monocrystalline silicon; ultrasonic assisted sawing; edge chipping; edge chipping mechanism 1. Introduction As an important semiconductor material, monocrystalline silicon is widely employed in electronics, communications and energy field [1–4].
    [Show full text]