Concepts Introduced a 1-Bit Logical Unit 1-Bit Half Adder 1-Bit Half

Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM Concepts Introduced A 1-Bit Logical Unit Below is a 1-bit logical unit that performs AND and OR operations. Both the AND and OR operations are always performed, but the output produced depends on the selector to the basic arithmetic/logic unit multiplexor. clocks A 32-bit logical unit for AND and OR operations would just be latches and ip-ops an array of these 1-bit logical units. registers SRAMs and DRAMs Operation a 0 Result 1 b Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM 1-Bit Half Adder 1-Bit Half Adder (cont.) A half adder takes two inputs, a and b, and generates two The circuit for the carry can use an AND gate. outputs, the carry and the sum. The circuit for the sum can use an XOR gate. A half adder is called a (2,2) adder as it takes two inputs and produces two outputs. a a carry sum What type of gate can produce the carry output? b b What type of gate can produce the sum output? The gates can be combined together as one logic block. Inputs Outputs Comments abcarry sum a + = sum 00 0 000 002 b + = 01 0 101 012 10 0 11+ 0 = 01 2 carry + = 11 1 011 102 Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM 1-Bit Full Adder 1-Bit Full Adder (cont.) Only the least signicant bit (LSB) result will use a half adder. Note the carryout and the sum outputs for the full adder dier The addition for the other bits need a third input, which is the from the half adder. CarryIn from the previous bit position. Sum = a·b·CarryIn + a·bCarryIn + a·b·CarryIn + a·b·CarryIn This type is called a full adder or a (3,2) adder since it takes CarryOut = three inputs and produces two outputs. a·b·CarryIn + a·b·CarryIn + a·b·CarryIn + a·b·CarryIn CarryIn stupnI stuptuO a b CarryIn CarryOut Sum Comments 0 0 0 0 0 0 + 0 + 0 = 00two a 0 0 1 0 1 0 + 0 + 1 = 01two 0 1 0 0 1 0 + 1 + 0 = 01two + Sum 0 1 1 1 0 0 + 1 + 1 = 10two b 1 0 0 0 1 1 + 0 + 0 = 01two 1 0 1 1 0 1 + 0 + 1 = 10two 1 1 0 1 0 1 + 1 + 0 = 10two 1 1 1 1 1 1 + 1 + 1 = 11 CarryOut two Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM Sum from Full Adder CarryOut from Full Adder Sum = a·b·CarryIn + a·bCarryIn + a·b·CarryIn + a·b·CarryIn CarryIn CarryOut = a·b·CarryIn + a·b·CarryIn + a·b·CarryIn + a·b·CarryIn = b·CarryIn + a·CarryIn + a·b a ab CarryIn 00 01 11 10 b 0 0 0 1 0 Sum 1 0 11 1 Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM CarryOut from Full Adder (cont.) Sum and CarryOut from Full Adder CarryIn CarryOut = b·CarryIn + a·CarryIn + a·b a CarryIn b Sum a b CarryOut CarryOut Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM Hardware Delay 1-Bit ALU for AND, OR, and Addition This 1-bit ALU performs AND, OR, and addition on a and b. Operation CarryIn Delay is dened as the time from when the input is stable to a the time when the output is stable. 0 Will the full 1-bit adder delay be greater than the half 1-bit adder delay? 1 Result ϩ 2 b CarryOut Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM 32-Bit ALU for AND, OR, and Addition Supporting Subtraction The 32-bit adder, also Operation called the ripple carry CarryIn adder, is created by linking the CarryOut of a0 CarryIn ALU0 Result0 b0 the previous 1-bit adder CarryOut Remember that a − b = a + −b = a + b + 1 in a two's to the CarryIn of the complement representation. current 1-bit adder. a1 CarryIn So to support a − b: ALU1 Result1 Faster adders are b1 CarryOut Invert every bit in b. possible. Add 1 to the result. Add with a. a2 CarryIn ALU2 Result2 b2 CarryOut . a31 CarryIn ALU31 Result31 b31 Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM 1-Bit ALU for AND, OR, Addition, and Subtraction NOR Operation This 1-bit ALU performs AND, OR, and addition on (a and b) or (a and b). By selecting b and setting CarryIn to 1 in the LSB of the ALU, the ALU can perform subtraction of b from a. The NOR operation is equivalent to a' AND b'. Binvert Operation CarryIn aba' b' a AND b aNOR b a' AND b' a 00 1 10 1 1 0 01 1 00 0 0 1 Result 10 0 10 0 0 11 0 01 0 0 b 0 ϩ 2 1 CarryOut Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM 1-Bit ALU for AND, OR, NOR, Addition, and Subtraction Supporting the SLT Instruction This 1-bit ALU performs AND, OR, and addition on (a or a) and (b or b). By selecting a and b,(a NOR b) is produced from (a AND b). Remember that the slt instruction produces a 1 if rs < rt (or Ainvert Operation a < b) and 0 otherwise. Binvert CarryIn So we need to set all but the least signicant bit (LSB) to 0. The LSB is set according to the result of the most signicant a 0 bit (MSB) after performing an a - b operation. 0 1 (a − b) < 0 ) ((a − b) + b) < (0 + b) 1 Result ) a < b b 0 ϩ 2 1 CarryOut Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM Dealing with Overow Checking for Overow When the result of the subtraction is greater than the largest positive representable value or is smaller than the smallest negative representable value, then we have an overow. The MSB of a subtraction result cannot be used when there is The largest positive value is 011...1. an overow. Adding the two largest positive values will give a result of A+B 111...10, which has the MSB set, but the CarryOut is not set. Operand A Operand B Result Overﬂow? The smallest negative value is 100...0. ≥ 0 ≥ 0<0 Adding the two smallest negative values will give a result of ≥ Yes <0 <0 0 000...00, which has the MSB clear, but the CarryOut is set. ≥ 0 ≥ 0 ≥ 0 No <0 <0 <0 ≥ 0<0<0No ≥ 0<0 ≥ 0No <0 ≥ 0<0No <0 ≥ 0 ≥ 0No Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM Checking for Overow (cont.) 1-Bit ALU for All Bits Except the Most Signicant Bit This 1-bit ALU has an extra input called Less that can be used We can detect overow by checking if the CarryIn and for the result of the slt instruction. This 1-bit ALU is used for CarryOut of the MSB dier. all bits except the MSB. MSB MSB Carry In Ainvert Operation MSB MSB Carry Carry MSB Over-XOR Binvert CarryIn AB InOut Result ﬂow? Carry Out Notes a 0 00 0 00No 0 0 1 00 1 01Yes1carries differ 01 0 01No 0 |A| < |B| 1 01 1 10No 0 |A| > |B| Result b 0 10 0 01No 0 |A| > |B| ϩ 2 Operation 10 1Ainvert10No 0 |A| < |B| 1 Binvert CarryIn 11 0 10Yes1carries differ Less 3 a 0 11 1 11No 0 0 1 CarryOut 1 Result Ainvert Operation b 0 Binvert CarryIn ϩ 2 Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM 1 a 0 0 Less 3 1-Bit ALU for the Most Signicant Bit 32-Bit ALU for AND,1 OR, NOR, Addition, Subtraction, SLT Binvert 1 Operation Ainvert This 1-bit ALU for the MSB hasCarryOut an output called Set for the The Set output is the CarryIn Result slt instruction from performing the subtraction. This 1-bit Less inputb for the LSB0 ALU also checks for overow. 1-bit ALU. ϩ 2 a0 CarryIn Result0 Ainvert Operation 1 A zero is input as the b0 ALU0 Binvert CarryIn Less Less signalLess for all CarryOut3 a 0 0 other 1-bit ALUs. Set 1 a1 CarryIn Result1 If Overow is set, Overflow b1 ALU1 Overflow detection 0 Less 1 then the Set result for CarryOut Result the MSB should be inverted. b 0 a2 CarryIn ϩ 2 Result2 b2 ALU2 1 0 Less CarryOut Less 3 . CarryIn Set a31 CarryIn Result31 Overflow Overflow b31 ALU31 Set detection 0 Less Overflow Basic ALU Design Clocks Flip-Flops Regs RAM Basic ALU Design Clocks Flip-Flops Regs RAM Supporting the BEQ Instruction Final 32-Bit ALU Bnegate Operation The Zero Ainvert result is To support a beq instruction, we can get the result of a0 CarryIn a − b Result0 used for b0 ALU0 and check if the result is zero. Less the beq CarryOut (a − b = 0) ) a = b instruction. a1 CarryIn Result1 b1 ALU1 0 Less .

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