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Half Adder, Which Finds the Sum of Two Bits

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Half Adder, Which Finds the Sum of Two Bits CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 21, SPRING 2013 TOPICS TODAY • Circuits for Addition • Standard Logic Components • Logisim Demo CIRCUITS FOR ADDITION 3.5 Combinational Circuits • Combinational logic circuits give us many useful devices. • One of the simplest is the half adder, which finds the sum of two bits. • We can gain some insight as to the construction of a half adder by looking at its truth table, shown at the right. 30 Half Adder • Inputs: A and B • Outputs: S = lower bit of A + B, cout = carry bit A B S cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 • Using Sum-of-Products: S = AB + AB, cout = AB. • Alternatively, we could use XOR: S = A ⊕ B. ! ! ! ! 1 3.5 Combinational Circuits • As we see, the sum can be found using the XOR operation and the carry using the AND operation. 31 3.5 Combinational Circuits • We can change our half adder into to a full adder by including gates for processing the carry bit. • The truth table for a full adder is shown at the right. 32 Full Adder • Inputs: A, B and cin • Outputs: S = lower bit of A + B, cout = carry bit A B cin S cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 • S = A BC + ABC + AB C + ABC = A ⊕ B ⊕ C. • cout =MAJ3=AB + BC + AC. ! ! ! ! 2 3.5 Combinational Circuits • Heres our completed full adder. 34 3.5 Combinational Circuits • Just as we combined half adders to make a full adder, full adders can connected in series. • The carry bit ripples from one adder to the next; hence, this configuration is called a ripple-carry adder. Todays systems employ more efficient adders. 35 3-7 Chapter 3: Arithmetic Constructing Larger Adders • A 16-bit adder can be made up of a cascade of four 4-bit ripple- carry adders. a15 a14 a13 a12 a3 a2 a1 a0 b15 b14 b13 b12 b3 b2 b1 b0 c12 c4 c0 c16 4-Bit Adder #3 . 4-Bit Adder #0 0 s15 s14 s13 s12 s3 s2 s1 s0 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 3-8 Chapter 3: Arithmetic Full Subtractor • Truth table and schematic symbol for a ripple-borrow subtractor: ai bi bori diffi bori+1 bi ai 0 0 0 0 0 bori 0 0 1 1 1 0 1 0 1 1 Full sub- 0 1 1 0 1 tractor 1 0 0 1 0 1 0 1 0 0 bori+1 1 1 0 0 0 diffi 1 1 1 1 1 (ai – bi) Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 3-10 Chapter 3: Arithmetic Combined Adder/Subtractor • A single ripple-carry adder can perform both addition and subtrac- tion, by forming the two’s complement negative for B when sub- tracting. (Note that +1 is added at c0 for two’s complement.) b3 b2 b1 b0 ADD / SUBTRACT a3 a2 a1 a0 c0 Full Full Full Full adder adder adder adder c4 s3 s2 s1 s0 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 3-21 Chapter 3: Arithmetic Carry-Lookahead Addition • Carries are represented in terms of Gi (generate) and Pi (propagate) expressions. Gi = aibi and Pi = ai + bi c0 = 0 c1 = G0 c2 = G1 + P1G0 c3 = G2 + P2G1 + P2P1G0 c4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 3-22 Chapter 3: Arithmetic Carry Lookahead Adder b3 a3 b2 a2 b1 a1 b0 a0 • Maximum gate delay for the carry genera- G3 P3G2 P2G1 P1G0 tion is only 3. The full adders introduce two more gate de- lays. Worst case path is 5 gate de- lays. c3 c2 c1 c0 c4 0 Full Full Full Full adder adder adder adder s3 s2 s1 s0 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring STANDARD LOGIC COMPONENTS 3.5 Combinational Circuits • Decoders are another important type of combinational circuit. • Among other things, they are useful in selecting a memory location according a binary value placed on the address lines of a memory bus. • Address decoders with n inputs can select any of 2n locations. This is a block diagram for a decoder. 36 3.5 Combinational Circuits • This is what a 2-to-4 decoder looks like on the inside. If x = 0 and y = 1, which output line is enabled? 37 3.5 Combinational Circuits • A multiplexer does just the opposite of a decoder. • It selects a single output from several inputs. • The particular input chosen for output is determined by the value of the multiplexers control lines. • To be able to select among n inputs, log2n control lines are This is a block needed. diagram for a multiplexer. 38 3.5 Combinational Circuits • This is what a 4-to-1 multiplexer looks like on the inside. If S0 = 1 and S1 = 0, which input is transferred to the output? 39 A-31 Appendix A: Digital Logic Demultiplexer F 00 0 D AB F0 F1 F2 F3 01 F1 D 0 0 0 0 0 0 0 10 F2 0 0 1 0 0 0 0 11 F 3 0 1 0 0 0 0 0 0 1 1 0 0 0 0 A B 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 F 0 = D A B F 2 = D A B 1 1 1 0 0 0 1 F 1 = D A B F 3 = D A B Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring A-32 Appendix A: Digital Logic Gate-Level Implementation of DEMUX F0 F1 D F2 F3 AB Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 3.5 Combinational Circuits • This shifter moves the bits of a nibble one position to the left or right. If S = 0, in which direction do the input bits shift? 40 Username: RICHARD CHANG Book: The Essentials of Computer Organization and Architecture. No part of any book may be reproduced or transmitted in any form by any means without the publisher's prior written permission. Use (other than pursuant to the qualified fair use privilege) in violation of the law or these Terms of Service is prohibited. Violators will be prosecuted to the full extent of the law. NEXT TIME • 2-bit ALU • Flip-flops .
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