International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN 2249-684X Vol. 3, Issue 1, Mar 2013, 87-96 © TJPRC Pvt. Ltd.

DESIGN OF HIGH SPEED AND LOW POWER SIX TRANSISTOR FULL ADDER USING TWO TRANSISTOR XOR GATE

B. DILLI KUMAR, K. CHARAN KUMAR & T. NAVEEN KUMAR M. Tech (VLSI), Department of ECE, Sree Vidyanikethan Engineering College (Autonomous), Tirupati, India

ABSTRACT

Full adder is one of the major components in the design of many sophisticated hardware circuits. In this paper the full adder has been designed by using a new efficient design with less number of transistors. A 2 transistor XOR gate has been proposed with the help of two PMOS (Positive Metal Oxide Semiconductor) transistors. By using this 2T XOR gate the size of the full adder has been decreased to a large extent which can be implemented with only 6 transistors. The proposed full adder has a significant improvement in silicon area and power delay product when compared to the previous 8T full adder circuits. Further the proposed adder requires less area to perform a required logic function. Further, the proposed full adder has less power dissipation which makes it suitable for many of the low power applications and because of less area requirement the proposed design can be used in many of the portable applications also .

KEYWORDS: Full Adder, XOR, Less Area, Speed, Low Power, Delay, Less Transistor Count, Low Power VLSI

INTRODUCTION

Full adder is one of the basic building blocks of many of the digital VLSI circuits. Several refinements has been made regarding its structure since its invention. The main aim of those modifications is to reduce the number of transistors to be used to perform the required logic, reduce the power consumption and increase the speed of operation. One of the major advantages in reducing the number of transistors is to put more devices on a single silicon chip there by reducing the total area.

In the recent days the use of portable electronic devices like cellular devices, laptops has been increased exponentially. The main requirement of these portable devices is reduced power consumption, small area and high speed of operation. To achieve these requirements research efforts in the field of low power VLSI (very large scale integration) have increased many folds. As the number of transistors on a single silicon chip increases, the package density also increases. With the rise in chip density, power consumption of VLSI systems is also increasing and this further, adds to reliability and packaging problems. Packaging and cooling cost of VLSI systems also goes up with high power dissipation. So, the low power consumption along with minimum delay and area requirements is one of important design consideration for IC designers in designing portable electronic devices and many sopisticated hardware circuits.

A basic full adder has three inputs and two outputs which are sum and carry. The logic circuit of this full adder can be implemented with the help of XOR gate, AND gates and OR gates. The logic for sum requires XOR gate while the logic for carry requires requires AND and OR gates. The basic equations for sum and carry of a full adder are

Sum = A ӨBӨC (1)

Carry = AB + BC + CA (2)

The basic logic diagram for full adder using its boolean equations with basic gates can be represented as shown below 88 B. Dilli Kumar, K. Charan Kumar & T. Naveen Kumar

Figure 1: Logic Circuit for Full Adder

The XOR gate is the basic building block of the full adder circuit. The performance of the full adder can be improved by enhancing the performance of the XOR gate. Several refinements has been made in its structure in terms of transistors to increase the performance of full adder. The early designs of XOR gates were based on eight transistors or six transistors that are conventionally used in most designs. The main intention of reducing this transistor count is to reduce the size of XOR gate so that large number of devices can be configured on a single silicon chip thereby reducing the area and delay. In the proposed work the XOR gate is implemented with only two transistors which reduces the area to a large extent and power consumption.

The truth table for full adder is

Table 1: Truth Table for Full Adder

The full adder design in static CMOS (Complementary Metal Oxide Semiconductor) using complementary pull up pMOS network and pull down nMOS network is the most conventional one, and it also has the advantage of very low power consumption. However, it has as many as 28transistors and thus requires considerable chip area for its implementation. The full adder design based on CMOS transmission gates and CMOS inverters uses 20 transistors. The circuit can operate with full output voltage swing.

The designs were further reduced to only 16 transistors while maintaining the full output voltage swing operation. To further minimize the number of transistors, pass transistor logic can be used in lieu of transmission gate. Pass transistor logic based XOR and XNOR circuits were used and as a result the full adder design consists of only 14transistors. In this design, an inverter is employed to generate the function A ӨB. The full adder can be implemented in terms of two half adders. It can be represented in the form of modules as Design of High Speed and Low Power Six Transistor Full Adder Using Two Transistor XOR Gate 89

Figure 2: Structure of Full Adder

In the present paper the full is implemented with only 6 transistors which reduces the area required to a great extent so the large number of full adder devices can be placed on a single silicon chip which in turn helps to reduce the size of hardware circuitry required in most complex systems.

EXISTING 3 TRANSISTOR XOR GATE

In the existing system the XOR gate can be implemented with the help of three transistors. In the existing system the 3 transistor XOR gate can be implemented with two pMos transistors and one nMos transistor. The Boolean equation for XOR gate is

Y = A Ө B (3)

The logic circuit for a three transistor XOR gate is

Figure 3: Design of 3 Transistor XOR Gate

The design is based on a modified version of a CMOS inverter and a PMOS pass transistor. When A=B=0, the transistors M2 and M3 are in OFF state while the transistor M1 is in ON state which results in logic low output. When A=0 and B=1, the transistor M2 is in ON state while the transistors M1 and M3 are in OFF state which results in logic high output. When A=1 and B=0, the transistor M1 and M3 are in ON state while the transistor M2 is in OFF state which results in logic high output. When A=B=1, the transistor M1 is in ON state while the transistors M2 and M3 are in OFF state which gives logic low output. From the overall operation it can be understood clearly that this 3T XOR gate exhibits the same operation of normal 2 input XOR gate.

When the input B is at logic high, the inverter on the left functions like a normal CMOS inverter. Therefore the output Y is the complement of input A. When the input B is at logic low, the CMOS inverter output is at high impedance. However, the pass transistor M3is enabled and the output Y gets the same logic value as input A. The operation of the whole circuit is thus like a 2 input XOR gate. However, when A=1 and B=0, voltage degradation due to threshold drop 90 B. Dilli Kumar, K. Charan Kumar & T. Naveen Kumar occurs across transistor M3 and consequently the output Y is degraded with respect to the input. The voltage degradation due to threshold drop can be considerably minimized by increasing the W/L ratio of transistor M3. A problem of current feedback through transistorM1 also occurs when A=1 and B=0. The output of the pass transistor is fed back through transistor M1 which is operating in the active region since its gate has a logic high input. This difficulty can be overcome by decreasing the W/L ratio of transistor M1.

EXISTING 8 TRANSISTOR FULL ADDER

In the existing full adder design, the basic logic for sum and carry can be implemented with the help of 8 transistors making the 3 transistor XOR gate as its main building block. The circuit diagram for 8 transistor full adder is

Figure 4: Design of 8 Transistor Full Adder

The logic can be implemented by using the following basic equations

Sum= A ӨBӨC (4)

Carry = AB+BC+CA (5)

The modified equation for carry is

Carry = (A ӨB) C+AB (6)

The sum logic is implemented by using equation 4 while the carry logic is implemented by using equation 6. From the figure it can be realized that two stage delays are required to obtain sum output and at most two stage delays are required to obtain carry output as well. The design was done using 0.15µm and 0.35µm technologies to establish the technology independence of the proposed design. The voltage drop due to the threshold drop in transistors M3 and M6 was minimized by suitably increasing the aspect ratios of the two transistors.

It shows the better performance than the earlier designed full adder and acquires less silicon area. The small silicon area of the existing full adder makes it potentially useful for building compact VLSI circuits on a small area of chip. The power dissipation of the proposed adder is much less compared to many of the previously designed adders

PROPOSED 2 TRANSISTOR XOR GATE

The XOR gate is the basic building block of full adder circuit. It is used in generating the sum output of full adder circuit. The size of the full adder circuit mainly depends on the number of transistors to be utilized in order to perform the required logic. Reducing the transistor count may reduce the physical area required by the full adder for the same logic. If the XOR gate can be realized with less number of transistors then it may be possible to reduce the number of transistors in realizing the full adder thereby reducing the size of the overall chip. The main intention of reducing this transistor count is Design of High Speed and Low Power Six Transistor Full Adder Using Two Transistor XOR Gate 91

to reduce the size of XOR gate so that large number of devices can be configured on a single silicon chip thereby reducing the area and delay.

In the present work a high speed, small size XOR gate has been proposed. In the proposed logic the XOR gate can be realized with the help of two transistors only which uses two pMOs transistors. The circuit diagram for 2 transistor XOR gate is

Figure 5: Design of Two Transistor XOR Gate

The basic operation of the proposed 2 transistor XOR gate is when A=B=0, both the transistors MP1 and MP2 are in ON state results in logic low output. When A=0 and B=1, then the transistor MP1 is in OFF state and the transistor MP2 is in ON state results in logic high output. When A=1 and B=0, the transistor MP1 is in ON state and the transistor MP2 is in OFF state results in logic high output. When A=B=0, the both the transistors MP1 and MP2 are in OFF state results in logic low output.

The truth table for a basic 2 input XOR gate is

Table 2: Truth Table for XOR Gate

By using the proposed 2 transistor XOR gate, the size of the full adder can be reduced to a great extent as it requires less number of transistors. If the size of the device can be decreased then it may be possible to integrate large number of devices on a single silicon chip which reduces the area and increases the speed of operation. This proposed 2 transistor XOR gate also minimizes the delay and the power to be dissipated to a great extent. Compared to the existing 3 transistor XOR gate the proposed 2 transistor XOR gate is advantageous one because the 2 transistor XOR gate requires less number of transistors compared to the 3 transistor XOR gate for the same logical operation. Both the two techniques implement the logic similar to 2 input XOR gate. The delay associated with the sum output of the 2 transistor XOR gate is also less than the delay associated with the sum output of 3 transistor XOR gate. With these advantages the proposed XOR gate may be used in many of the consumer electronic goods and portable electronic devices where less power and delay is the primary requirement. 92 B. Dilli Kumar, K. Charan Kumar & T. Naveen Kumar

PROPOSED 6 TRANSISTOR FULL ADDER

Full adder is the most widely used element in many of the arithmetic operations. A basic full adder circuit has three inputs and two outputs and the two outputs are sum and carry. Further full adder is the basic element in many of the low power VLSI devices where low power and less area is the primary requirement. To reduce the area of the overall chip the elements inside the chip are to be designed as small as possible. The size of the individual elements inside the chips can be minimized by modifying their basic logical representation in a meaning full manner so that the desired logic can be obtained with less size.

In the proposed paper we are concentrating mainly on full adder implementation as it finds use in many of the low power applications. A basic full adder can be implemented with XOR gate, AND gates and OR gate. The logic for sum can be realized using XOR gate whereas the logic for carry can be realized using AND and OR gates. It shows that the entire full adder logic is based on its sum and carry outputs. Reducing the transistor counts in sum and carry logic may reduce the size of the full adder. For that purpose a 2 transistor XOR gate has been proposed which uses only two pMOs transistors to perform the required logic similar to two input XOR gate.

In the proposed logic, the full adder is designed with a minimum of 6 transistors which is a modified version of the existing 8 transistor full adder. It uses both the pMos and nMos transistors in its hardware circuitry. The 2 transistor XOR gate plays a dominant role in minimizing the transistor count from 8 to 6. In addition to XOR gate the proposed full adder also used one XNOR gate which can be obtained by modifying the basic equations of sum and carry of a full adder which also plays an important role in minimizing the transistor count.

The modified equations for sum and carry of the proposed full adder is

Sum = (A ӨB) C + (A ӨB) C (7)

Carry= (A ӨB) C + AB (8)

The logic diagram for the proposed 6 transistor full adder is

Figure 6: Design of 6 Transistor Full Adder

In the proposed logic the 6 transistor full adder can be implemented with the help of two nMos transistors and four pMos transistors.

The main advantages of the proposed 6 transistor full adder circuit is its small size so that large number of devices can be placed on a single silicon chip results in less area, it has less power dissipation compared to the previously designed Design of High Speed and Low Power Six Transistor Full Adder Using Two Transistor XOR Gate 93

full adder circuits and the speed of operation is also high. The proposed full adder also reduces the two stage delay associated with the sum and carry elements of eight transistor full adder circuit. In order to establish the technology independence of the, the adder has been designed using 0.15µm and0.35µm technologies. The power-delay simulation of the adder has been carried out. Simulation results indicate that the designed full adder has much less power-delay product. Because of these advantages the proposed full adder can be used in many advanced applications where less power is the main requirement.

SIMULATION RESULTS OF PROPOSED FULL ADDER

The simulation results of the proposed six transistor full adder is

Figure 7: Simulation Results of Proposed Six Transistor Full Adder

The post layout simulation of proposed six transistor full adder has been carried out with all combinations of inputs. Each circuit is simulated with the same testing conditions. The netlist of those XOR gates and full adder are extracted and simulated using Mentor Graphics tool . Since a circuit responds differently to different input combinations, so the output is verified for all eight possible input combinations. Some degradations may occur in the output waveforms which may be reduced completely by careful designing of interconnection between the Mos devices.

Table 3: Performance Parameters of Proposed Full Adder

Power dissipation (watts) 182.2649P Latency 0.000% Average number of iterations 2.350515 Memory size (bytes) 43401216 Number of transistors 6

Table 3 shows the performance parameters of the proposed 6T full adder circuit. From this it is evident that the propsed full adder design has less power dissipation which is in the order of pico farads, and it uses only 6 transistors to perform the required sum and carry logic. So, it occupies minimum silicon area on the chip which makes it suitable for building compact VLSI circuits on small area of chip. The average number of iterations required by the design is also low which makes the design less complex.

CONCLUSIONS

The current work proposes the design of 6 transistor full adder, which is by far the full adder with the lowest transistor count. In designing the proposed 6transistor full adder, a 2 transistor XOR gate also been proposed. The 94 B. Dilli Kumar, K. Charan Kumar & T. Naveen Kumar proposed XOR gate also has a much less delay and hence much less power delay product.The main aim of this paper is to design a high performance and low power full adder cell with less power dissipation and acquires least area. Simulation results shows that this proposed full adder achieves better power reduction when compared with other commonly used full adders. Becase of the less power dissipation and less transistor count the proposed logic can be useful in portable and low power applications. Due to less number of iterations the complexity of the design is also low and it require less memory.

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AUTHORS

Mr. B. Dilli kumar , Student, is currently Pursuing his M.Tech VLSI., in ECE department of Sree Vidyanikethan Engineering College, Tirupati. He has completed B.Tech in Electronics and Communication Engineering, in Jawaharlal Nehru Technological University, Anantapur. His research areas are VLSI, Digital IC Design, and VLSI and Signal processing, Testing and Testability.

Mr. K. Charan kumar , Student, is currently Pursuing his M.Tech VLSI., in ECE department of Sree Vidyanikethan Engineering College, Tirupati. He has completed B.Tech in Electronics and Communication Engineering, in Jawaharlal Nehru Technological University, Anantapur. His research areas are VLSI, Digital IC Design. 96 B. Dilli Kumar, K. Charan Kumar & T. Naveen Kumar

Mr. T. Naveen kumar , Student, is currently Pursuing his M.Tech VLSI., in ECE department of Sree Vidyanikethan Engineering College, Tirupati. He has completed B.Tech in Electronics and Communication Engineering, in Visvesvaraya Technological University, Belgaum. His research areas are VLSI, Digital IC Design