Design of High Speed and Low Power Six Transistor Full Adder Using Two Transistor Xor Gate

International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN 2249-684X Vol. 3, Issue 1, Mar 2013, 87-96 © TJPRC Pvt. Ltd. DESIGN OF HIGH SPEED AND LOW POWER SIX TRANSISTOR FULL ADDER USING TWO TRANSISTOR XOR GATE B. DILLI KUMAR, K. CHARAN KUMAR & T. NAVEEN KUMAR M. Tech (VLSI), Department of ECE, Sree Vidyanikethan Engineering College (Autonomous), Tirupati, India ABSTRACT Full adder is one of the major components in the design of many sophisticated hardware circuits. In this paper the full adder has been designed by using a new efficient design with less number of transistors. A 2 transistor XOR gate has been proposed with the help of two PMOS (Positive Metal Oxide Semiconductor) transistors. By using this 2T XOR gate the size of the full adder has been decreased to a large extent which can be implemented with only 6 transistors. The proposed full adder has a significant improvement in silicon area and power delay product when compared to the previous 8T full adder circuits. Further the proposed adder requires less area to perform a required logic function. Further, the proposed full adder has less power dissipation which makes it suitable for many of the low power applications and because of less area requirement the proposed design can be used in many of the portable applications also . KEYWORDS: Full Adder, XOR, Less Area, Speed, Low Power, Delay, Less Transistor Count, Low Power VLSI INTRODUCTION Full adder is one of the basic building blocks of many of the digital VLSI circuits. Several refinements has been made regarding its structure since its invention. The main aim of those modifications is to reduce the number of transistors to be used to perform the required logic, reduce the power consumption and increase the speed of operation. One of the major advantages in reducing the number of transistors is to put more devices on a single silicon chip there by reducing the total area. In the recent days the use of portable electronic devices like cellular devices, laptops has been increased exponentially. The main requirement of these portable devices is reduced power consumption, small area and high speed of operation. To achieve these requirements research efforts in the field of low power VLSI (very large scale integration) have increased many folds. As the number of transistors on a single silicon chip increases, the package density also increases. With the rise in chip density, power consumption of VLSI systems is also increasing and this further, adds to reliability and packaging problems. Packaging and cooling cost of VLSI systems also goes up with high power dissipation. So, the low power consumption along with minimum delay and area requirements is one of important design consideration for IC designers in designing portable electronic devices and many sopisticated hardware circuits. A basic full adder has three inputs and two outputs which are sum and carry. The logic circuit of this full adder can be implemented with the help of XOR gate, AND gates and OR gates. The logic for sum requires XOR gate while the logic for carry requires requires AND and OR gates. The basic equations for sum and carry of a full adder are Sum = A ӨBӨC (1) Carry = AB + BC + CA (2) The basic logic diagram for full adder using its boolean equations with basic gates can be represented as shown below 88 B. Dilli Kumar, K. Charan Kumar & T. Naveen Kumar Figure 1: Logic Circuit for Full Adder The XOR gate is the basic building block of the full adder circuit. The performance of the full adder can be improved by enhancing the performance of the XOR gate. Several refinements has been made in its structure in terms of transistors to increase the performance of full adder. The early designs of XOR gates were based on eight transistors or six transistors that are conventionally used in most designs. The main intention of reducing this transistor count is to reduce the size of XOR gate so that large number of devices can be configured on a single silicon chip thereby reducing the area and delay. In the proposed work the XOR gate is implemented with only two transistors which reduces the area to a large extent and power consumption. The truth table for full adder is Table 1: Truth Table for Full Adder The full adder design in static CMOS (Complementary Metal Oxide Semiconductor) using complementary pull up pMOS network and pull down nMOS network is the most conventional one, and it also has the advantage of very low power consumption. However, it has as many as 28transistors and thus requires considerable chip area for its implementation. The full adder design based on CMOS transmission gates and CMOS inverters uses 20 transistors. The circuit can operate with full output voltage swing. The designs were further reduced to only 16 transistors while maintaining the full output voltage swing operation. To further minimize the number of transistors, pass transistor logic can be used in lieu of transmission gate. Pass transistor logic based XOR and XNOR circuits were used and as a result the full adder design consists of only 14transistors. In this design, an inverter is employed to generate the function A ӨB. The full adder can be implemented in terms of two half adders. It can be represented in the form of modules as Design of High Speed and Low Power Six Transistor Full Adder Using Two Transistor XOR Gate 89 Figure 2: Structure of Full Adder In the present paper the full is implemented with only 6 transistors which reduces the area required to a great extent so the large number of full adder devices can be placed on a single silicon chip which in turn helps to reduce the size of hardware circuitry required in most complex systems. EXISTING 3 TRANSISTOR XOR GATE In the existing system the XOR gate can be implemented with the help of three transistors. In the existing system the 3 transistor XOR gate can be implemented with two pMos transistors and one nMos transistor. The Boolean equation for XOR gate is Y = A Ө B (3) The logic circuit for a three transistor XOR gate is Figure 3: Design of 3 Transistor XOR Gate The design is based on a modified version of a CMOS inverter and a PMOS pass transistor. When A=B=0, the transistors M2 and M3 are in OFF state while the transistor M1 is in ON state which results in logic low output. When A=0 and B=1, the transistor M2 is in ON state while the transistors M1 and M3 are in OFF state which results in logic high output. When A=1 and B=0, the transistor M1 and M3 are in ON state while the transistor M2 is in OFF state which results in logic high output. When A=B=1, the transistor M1 is in ON state while the transistors M2 and M3 are in OFF state which gives logic low output. From the overall operation it can be understood clearly that this 3T XOR gate exhibits the same operation of normal 2 input XOR gate. When the input B is at logic high, the inverter on the left functions like a normal CMOS inverter. Therefore the output Y is the complement of input A. When the input B is at logic low, the CMOS inverter output is at high impedance. However, the pass transistor M3is enabled and the output Y gets the same logic value as input A. The operation of the whole circuit is thus like a 2 input XOR gate. However, when A=1 and B=0, voltage degradation due to threshold drop 90 B. Dilli Kumar, K. Charan Kumar & T. Naveen Kumar occurs across transistor M3 and consequently the output Y is degraded with respect to the input. The voltage degradation due to threshold drop can be considerably minimized by increasing the W/L ratio of transistor M3. A problem of current feedback through transistorM1 also occurs when A=1 and B=0. The output of the pass transistor is fed back through transistor M1 which is operating in the active region since its gate has a logic high input. This difficulty can be overcome by decreasing the W/L ratio of transistor M1. EXISTING 8 TRANSISTOR FULL ADDER In the existing full adder design, the basic logic for sum and carry can be implemented with the help of 8 transistors making the 3 transistor XOR gate as its main building block. The circuit diagram for 8 transistor full adder is Figure 4: Design of 8 Transistor Full Adder The logic can be implemented by using the following basic equations Sum= A ӨBӨC (4) Carry = AB+BC+CA (5) The modified equation for carry is Carry = (A ӨB) C+AB (6) The sum logic is implemented by using equation 4 while the carry logic is implemented by using equation 6. From the figure it can be realized that two stage delays are required to obtain sum output and at most two stage delays are required to obtain carry output as well. The design was done using 0.15µm and 0.35µm technologies to establish the technology independence of the proposed design. The voltage drop due to the threshold drop in transistors M3 and M6 was minimized by suitably increasing the aspect ratios of the two transistors. It shows the better performance than the earlier designed full adder and acquires less silicon area. The small silicon area of the existing full adder makes it potentially useful for building compact VLSI circuits on a small area of chip.

Load more