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Network on a chip
Network on Chip for FPGA Development of a Test System for Network on Chip
Embedded Networks on Chip for Field-Programmable Gate Arrays by Mohamed Saied Abdelfattah a Thesis Submitted in Conformity With
An Early Performance Evaluation of Many Integrated Core Architecture Based SGI Rackable Computing System
A Comparison of Four Series of Cisco Network Processors
MYTHIC MULTIPLIES in a FLASH Analog In-Memory Computing Eliminates DRAM Read/Write Cycles
Using Inspiration from Synaptic Plasticity Rules to Optimize Traffic Flow in Distributed Engineered Networks Arxiv:1611.06937V1
State-Of-The-Art in Heterogeneous Computing
ESA DSP Day 2016 Workshop Proceedings
Hardware Design of Message Passing Architecture on Heterogeneous System
Scheduling Tasks on Heterogeneous Chip Multiprocessors with Reconfigurable Hardware
Smartcell: an Energy Efficient Reconfigurable Architecture for Stream Processing
Towards a Scalable Software Defined Network-On-Chip for Next Generation Cloud
Low-Power Design Using Noc Technology
Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI
ASC Processor Development & Open Problems
A Study of Network on Chip
Toward a Science of Network-On-Chip Design Full Text Available At
Microprocessor Troller (APIC) and a Dual- Tested HW Limits of a Mesh Network Improved Mesh with 3X Performance/Watt Processor Interface
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System on a Chip
Power and Performance Optimization for Network-On-Chip Based Many-Core Processors
Computer Design
Efficient Memory Access and Synchronization in Noc-Based
DATAFLOW COMPUTERS: THEIR HISTORY and to Improve the Hybrid Systems
Multi-Core Processors – an Overview
Programming the Adapteva Epiphany 64-Core Network-On-Chip Coprocessor
Modeling and Verification of Network-On-Chip Using Constrained-Devs
Managing Power Consumption in Networks on Chips
The Limits of Semiconductor Technology and Oncoming Challenges in Computer Microarchitectures and Architectures
Lattice QCD on Upcoming Arm Architectures
Applying the Benefits of Network on a Chip Architecture to FPGA System Design
Cosh: Clear OS Data Sharing in an Incoherent World
A GALS Infrastructure for a Massively Parallel Multiprocessor
Bus-Based On-Chip Networks: Current and Next Generations
Design of an Accurate Noc for Multiprocessor Soc
System on Chip Design and Modelling Dr. David J Greaves
Revisiting the Case of ARM Socs in High-Performance Computing Clusters
Parameters of a On-Chip Network for Multi-Processor System-On-Chip Environments
Efficient Router Design for Network on Chip
Optical Network-On-Chip Architectures and Designs
NOC): Design Challenges
Survey on High Performance Reconfigurable Soft - Core Processor for SIMD Applications
Architecture of Multi-Core Computer with Data Driven Computation Model
A Multi-FPGA High Performance Computing Platform for Network-Centric Applications Tirumale Ramesh, Senior Member, IEEE and John Meier the Boeing Company
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D4.1 Report on State of the Art of Novel Compute Elements and Gap Analysis in MPI and GASPI
China's Bid to Lead Artificial Intelligence Chip Development Within the Decade
Review of Multicore Processing System
Emerging Technologies in On-Chip and Off-Chip Interconnection Network
Power and Performance Optimization for Network-On-Chip Based Many-Core Processors
A Survey of Software-Defined Networks-On-Chip
Quality-Of-Service (Qos) for Asynchronous On-Chip Networks
Teraflops Research Chip Overview
A Survey of Cluster Based Multi-Processor System Design with IP-Cores K
Network on a Chip: an Architecture for Billion Transistor Era
MAPPING MULTIMODE SYSTEM COMMUNICATION to a NETWORK-ON-A-CHIP (Noc) a Thesis by PRAVEEN SUNDER BHOJWANI Submitted to the Office