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A Survey of Cluster Based Multi-Processor System Design with IP-Cores K 7512 K. Immanuvel Arokia James/ Elixir Network Engg. 44 (2012) 7512-7518 Available online at www.elixirpublishers.com (Elixir International Journal) Network Engineering Elixir Network Engg. 44 (2012) 7512-7518 A survey of cluster based multi-processor system design with IP-cores K. Immanuvel Arokia James VEL Tech Dr. RR and Dr. SR Technical University, Chennai. ARTICLE INFO ABSTRACT Article history: This project aims to design a cluster-based multiprocessor system-on-chip (MPSoC) Received: 23 October 2011; combines of hybrid interconnection composed of both bus based and network on chip Received in revised form: (NOC) architecture. Two or more microprocessors working together to perform one or more 16 March 2012; related tasks using a shared memory is commonly referred to as a multiprocessor system. Accepted: 27 March 2012; NoC is used to form a network to pass the message packets more efficiently between the source and destination and to provide additional communication resources so that multiple Keywords paths can be operated simultaneously. High performance is achieved by efficient MPSoC, implementation of hardware and software. It is done by fine tuning MPSoC architecture in Cluster, the early stage of the design process. This project uses the FPGA device to prototype the IP Cores, cluster-based MPSoC. This paper proposes a hierarchical architecture consisting of SMP NoC. clustered nodes, each of which is structured by more than one baseline cores through centrally-shared memory and, some parallel applications with different characteristic of parallelism, functionality and communication pattern are designed and presented in this work. In this work a pure VHDL design, integrated with some intellectual property (IP) blocks. This project accounts for the highest throughput ratio. © 2012 Elixir All rights reserved. Introduction sequences of instructions in multiple contexts (multiple- Any system that incorporates two or more microprocessors instruction, multiple-data or MIMD). working together to perform one or more related tasks is Processor Coupling commonly referred to as a multiprocessor system. In a Tightly-coupled multiprocessor systems contain multiple multiprocessing system, all CPUs may be equal, or some may be CPUs that are connected at the bus level. These CPUs may have reserved for special purposes. A combination of hardware and access to a central shared memory (SMP or UMA), or may operating-system software design considerations determines the participate in a memory hierarchy with both local and shared symmetry in a given system. For example, hardware or software memory (NUMA). The IBM p690 Regatta is an example of a considerations may require that only one CPU respond to all high end SMP system. Intel Xeon processors dominated the hardware interrupts, whereas all other work in the system may multiprocessor market for business PCs and were the only x86 be distributed equally among CPUs; or execution of kernel- option until the release of AMD's Opteron range of processors in mode code may be restricted to only one processor (either a 2004. Both ranges of processors had their own onboard cache specific processor, or only one processor at a time), whereas but provided access to shared memory; the Xeon processors via user-mode code may be executed in any combination of a common pipe and the Opteron processors via independent processors. Multiprocessing systems are often easier to design if pathways to the system RAM. such restrictions are imposed, but they tend to be less efficient Chip multiprocessors, also known as multi-core computing, than systems in which all CPUs are utilized. involves more than one processor placed on a single chip and Systems that treat all CPUs equally are called symmetric can be thought of the most extreme form of tightly-coupled multiprocessing (SMP) systems. Because of the flexibility of multiprocessing. Mainframe systems with multiple processors SMP and because of its cost being relatively low, this are often tightly-coupled. architecture has become the standard for mainstream Loosely-coupled multiprocessor systems (often referred to multiprocessing. Multitasking operating systems can run as clusters) are based on multiple standalone single or dual processes on any CPU in a SMP system because each processor processor commodity computers interconnected via a high speed has the same view of the machine. In systems where all CPUs communication system (Gigabit Ethernet is common). A Linux are not equal, system resources may be divided in a number of Beowulf cluster is an example of a loosely-coupled system. ways, including asymmetric multiprocessing (ASMP), non- Tightly-coupled systems perform better and are physically uniform memory access (NUMA) multiprocessing, and clustered smaller than loosely-coupled systems, but have historically multiprocessing In multiprocessing, the processors can be used required greater initial investments and may depreciate rapidly; to execute a single sequence of instructions in multiple contexts nodes in a loosely-coupled system are usually inexpensive (single-instruction, multiple-data or SIMD, often used in vector commodity computers and can be recycled as independent processing), multiple sequences of instructions in a single machines upon retirement from the cluster. Power consumption context (multiple-instruction, single-data or MISD, used for is also a consideration. Tightly-coupled systems tend to be much redundancy in fail-safe systems and sometimes applied to more energy efficient than clusters. This is because considerable describe pipelined processors or hyper-threading), or multiple Tele: E-mail addresses: [email protected] © 2012 Elixir All rights reserved 7513 K. Immanuvel Arokia James/ Elixir Network Engg. 44 (2012) 7512-7518 economies can be realized by designing components to work Literature Survey together from the beginning in tightly-coupled systems, whereas The future of multiprocessor systems-on-chips by wayne loosely-coupled systems use components that were not wolf dec 2004 necessarily intended specifically for use in such systems. This paper surveys the state-of-the-art and pending Existing System challenges in MPSoC design. Standards in communications, The multiprocessor System-on-Chip (MPSoC) is a system- multimedia, networking and other areas encourage the on-a-chip (SoC) which uses multiple processors (see multi- development of high-performance platforms that can support a core), usually targeted for embedded applications. It is used by range of implementations of the standard. A multiprocessor platforms that contain multiple, usually heterogeneous, system-on-chip includes embedded processors, digital logic, and processing elements with specific functionalities reflecting the mixed-signal circuits combined into a heterogeneous need of the expected application domain, a memory hierarchy multiprocessor. This mix of technologies creates a major (often using scratchpad RAM and DMA) and I/O components. challenge for MPSoC design teams. We will look at some All these components are linked to each other by an on-chip existing MPSoC designs and then describe some hardware and interconnect. These architectures meet the performance needs of software challenges for MPSoC designers. multimedia applications, telecommunication architectures, HIBI-based Multiprocessor SoC on FPGA by Erno network security and other application domains while limiting Salminen, Ari Kulmala, and Timo D. Hämäläinen, 2005 the power consumption through the use of specialized FPGAs offer excellent platform for System-on- Chips processing elements and architecture. consisting of Intellectual Property (IP) blocks. The problem is The existing microprocessor system on chip architecture that IP blocks and their interconnections is often FPGA vendor was based on either on bus based architecture or a network dependent. The HIBI Network-on-Chip (NoC) scheme solves based architecture. Initially MPSoC architectures were building the problem by providing flexible interconnection network and using system on a chip (SoC). It refers to integrating all IP block integration with Open Core Protocol (OCP) interface. components of a computer or other electronic system into a Therefore, IP components can be of any type: processors, single integrated circuit (chip). It may contain digital, analog, hardware accelerators, communication interfaces, or memories. mixed-signal, and often radio-frequency functions – all on a As a proof of concept, a multiprocessor system with eight soft single chip substrate. These blocks are connected by either a processor cores and HIBI is prototyped on FPGA. The whole proprietary or industry-standard bus such as the AMBA bus system uses 36402 logic elements, 2.9 Mbits of RAM, and from ARM. DMA controllers route data directly between operates on 78 MHz frequency on Altera Stratix 1S40, which is external interfaces and memory, by-passing the processor core comparable to other FPGA multiprocessors. The most important and thereby increasing the data throughput of the SoC. bus- benefit is significant reduction of the design effort compared to based architectures ran out of performance due to the increase in system specific interconnection networks. HIBI also presents the number of cores used and, in addition, consumed far more first OCP compliant IP-block integration in FPGA. energy than desirable to achieve the required on-chip communications and bandwidth. This led to the development of a new architectures based on Network-on- Chip technique. The idea
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