ASC Processor Development & Open Problems

Growth of Intel Processors Year of L1 64-bit RISC CPU Cache Introduction Transistors Processor L2 w/ multithreading etc. 1971 2,250 4004 Cache big level 1 cache, 1972 2,500 8008 CPU bigger level 2 cache 1974 5,000 8080 1978 29,000 8086 1982 120,000 286 CPU with Cache 1985 275,000 Intel386™ processor 1989 1,180,000 Intel486™ processor 1993 3,100,000 Intel® Pentium® processor 1997 7,500,000 Intel® Pentium® II processor What can we do with a billion (109) transistors? 1999 24,000,000 Intel® Pentium® III processor 2000 42,000,000 Intel® Pentium® 4 processor Or more in a few years? 2002 220,000,000 Intel® Itanium® processor 2003 410,000,000 Intel® Itanium® 2 processor Robert A. Walker Robert A. Walker DSP DSP L1 Memory L1 Memory Cache Cache L2 DSP L2 DSP Cache A/D Cache A/D CPU CPU CPU CPU RF RF CPU with Cache System on a Chip (SoC) CPU with Cache System on a Chip (SoC) tens of powerful CPUs: CPU CPU RISC CPU (ARM, etc.), RISC CPU (ARM, etc.), cache, memory custom CPU, etc. Memory DSP, MPEG, A/D, D/A, shared DRAM memory RF, analog (paged, multi-port, etc.) CPU CPU network-on-a-chip Multiprocessor SoC (MPSoC) Robert A. Walker Robert A. Walker many (e.g., 100s, 1000s) DSP Memory Mem Mem processing units PE PE small (e.g., 1-bit, 8-bit) customized for a DSP Control Processing Elements A/D Mem Mem specific application PE PE Unit (PEs) (CU) CPU Control Unit (CU) “sea of DSPs” RF Mem Mem PE PE broadcasts instructions System on a Chip (SoC) SIMD Processor Array SoC DSP DSP CPU CPU DSP DSP CPU CPU DSP DSP Memory DSP DSP Memory DSP DSP CPU CPU DSP DSP CPU CPU DSP Array SoC Multiprocessor SoC (MPSoC) DSP Array SoC Multiprocessor SoC (MPSoC) Robert A. Walker Robert A. Walker Mem Mem Mem Mem Control Mem Mem Mem Mem Control PE PE PE PE Unit PE PE PE PE Unit Control (CU) Control (CU) Mem Mem Mem Mem Mem Mem Mem Mem PE PE Unit PE PE PE PE Unit PE PE (CU) Control (CU) Control Mem Mem Mem Mem Unit Mem Mem Mem Mem Unit PE PE PE PE (CU) PE PE PE PE (CU) SIMD Processor Array SoC MSIMD Processor Array SoC SIMD Processor Array SoC MSIMD Processor Array SoC DSP DSP SIMD or MSIMD Mem Mem APE APE Assoc. MSIMD = multiple SIMD Processor Array SoC CU DSP DSP (PASoC) Mem Mem multiple CUs support APE APE “control parallelism” plus support for Assoc. DSP DSP associative computing Mem Mem CU some PEs do IF, APE APE others do ELSE DSP Array SoC Associative MSIMD PASoC Robert A. Walker Robert A. Walker Development of an ASC Processor Mem Mem Control SIMD or MSIMD PE PE Unit Processor Array SoC (CU) ! 2001-02 — first 4-PE prototype w/ associative search, plus support for Mem Mem PE PE responder resolution, max/min search, not implemented associative computing Control Unit ! 2003 — scalable ASC Processor w/50 PEs, implemented on as part of a SoC Mem Mem PE PE (CU) APEX 20K1000E MSIMD Processor Array SoC ! 2004 — scalable ASC Processor w/ 1-D and 2-D network, demonstrated on VLDC string-matching example & image processing example (edge detection using convolution) Mem Mem Assoc. Mem Mem ! 2005 — scalable ASC Processor w/ pipelined PEs and APE APE APE APE Control CU reconfigurable network, to be demonstrated Mem Mem Unit APE APE Mem Mem (CU) ! 2005 — scalable ASC Processor w/ augmented reconfigurable DSP APE APE MPEG network and row/column broadcast, demonstrated on exact Mem Mem and approximate match LCS example Memory CPU APE APE CU ! 2006 — scalable MASC Processor System on a Chip (SoC) Associative MSIMD PASoC ! 2007? — Multithreaded ASC Processor Robert A. Walker Robert A. Walker Some Currently Open Problems… ! Implement & demonstrate “virtual PEs” on associative String Match and/or LCS algorithm ! Continue LCS algorithm research " Investigate further the presence of “gaps” " Find “best” CS instead of “longest” CS ! Implement & demonstrate one or more associative algorithms on ASC and/or MASC Processor " Convex Hull, video/media processing ! Augment first MASC Processor to support nested conditionals and loops and to support network operations Robert A. Walker.

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