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Efficient Router Design for Network on Chip

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Efficient Router Design for Network on Chip DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA EFFICIENT ROUTER DESIGN FOR NETWORK ON CHIP SWAPNA S 2013 EFFICIENT ROUTER DESIGN FOR NETWORK ON CHIP A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology In VLSI DESIGN AND EMBEDDED SYSTEM By SWAPNA S Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2011 – 2013 i EFFICIENT ROUTER DESIGN FOR NETWORK ON CHIP A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology In VLSI DESIGN AND EMBEDDED SYSTEM by SWAPNA S 211EC2122 Under the Guidance of Prof. Ayas Kanta Swain Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2011 – 2013 ii Dedicated to my parents iii DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING NATIONAL INSTITUTE OF TECHNOLOGY, ROURKELA ORISSA, INDIA-769008 CERTIFICATE This is to certify that the Thesis Report entitled “EFFICIENT ROUTER DESIGN FOR NETWORK ON CHIP”, submitted by SWAPNA S bearing roll no. 211EC2122 in partial fulfilment of the requirements for the award of Master of Technology in Electronics and Communication Engineering with specialization in “VLSI Design and Embedded Systems” during session 2011 - 2013 at National Institute of Technology, Rourkela is an authentic work carried out by her under my supervision and guidance. To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other university/institute for the award of any Degree or Diploma. Place: Rourkela Prof. AYAS KANTA SWAIN Date: Dept. of E.C.E National Institute of Technology Rourkela – 769008 iv ACKNOWLEDGEMENTS With deep regards and profound respect, I avail this opportunity to express my deep sense of gratitude and indebtedness to Prof. Ayas Kanta Swain, Department of Electronics and Communication Engineering, NIT Rourkela for his valuable guidance and support. I am deeply indebted for the valuable discussions at each phase of the project. I consider it my good fortune to have got an opportunity to work with such a wonderful person. Sincere thanks to Prof. K. K. Mahapatra, Prof. S. Meher, Prof. S. K. Behera, Prof. S. K. Das, Prof. Samit Ari, Prof. A. K. Sahoo and Prof.Poonam Singh for teaching me and for their constant feedbacks and encouragements. I would like to thank all faculty members and staff of the Department of Electronics and Communication Engineering, NIT Rourkela for their generous help. I would like to thank all my friends, especially my classmates without whom the project would not have reached its completion. Last but not least I also convey my deepest gratitude to my parents and family for whose faith, patience and teaching had always inspired me to walk upright in my life. Finally, I humbly bow my head with utmost gratitude before the God Almighty who always showed me a path to go and without whom I could not have done any of these. v ABSTRACT A Network-on-chip (NoC) is a new paradigm in complex system-on-chip (SoC) designs that provide efficient on chip communication networks. It allows scalable communication and allows decoupling of communication and computation. The data is routed through the networks in terms of packets. The routing of data is mainly done by routers. So the architecture of router must be an efficient one with a lower latency and higher throughput. In this project we designed, implemented and analyzed three different router architectures for a network on chip communication. The routers have five ports, four ports connected to other ports in four different directions and the fifth port connected to the processing element through a network interface. The first architecture is a basic router with demultiplexer and scheduler. The second architecture consists of crossbar switch and arbiter. The third architecture uses the CDMA technology that is popular in wireless communication. The three architectures were analyzed for their performance in terms of delay, throughput and latency and we concluded that CDMA router performs better than the other two. vi CONTENTS Abstract vi List of Figures x List of Tables xi Acronyms xii Chapter 1 Introduction and Overview 1 1.1 Introduction 2 1.2 Network on Chip (NoC) 5 1.3 NoC Architecture 7 1.4 Links 8 1.5 Network Interface 8 1.6 Router 8 1.7 Network Topology 9 1.7.1 Mesh 11 1.7.2 Torus 11 1.7.3 Tree 12 1.7.4 Butterfly 12 1.7.5 Polygon 12 1.7.6 Star 12 1.8 Metrics for Comparing Topologies 13 1.9 Thesis Goals 13 1.10 Objctives 14 1.11 Thesis Outline 14 vii Chapter 2 Design of a FIFO Based Router 15 2.1 FIFO Based Router Architecture 16 2.2 Register and Multiplexer 17 2.3 FIFO Unit 18 2.4 Scheduler 19 2.5 Round Robin Scheduling Algorithm 20 2.6 Simulation Results 20 2.7 Synthesis Results 21 2.8 Timing Summary 22 Chapter 3 Design of a Crossbar Based Router 23 3.1 Crossbar Based Router Architecture 24 3.2 FIFO Buffer 24 3.3 Crossbar 25 3.4 Arbiter 26 3.5 Simulation Results 27 3.6 Synthesis Results 29 3.7 Timing Summary 29 Chapter 4 Design of a CDMA Based Router 30 4.1 CDMA Based Router Architecture 31 4.2 CDMA Technique 31 4.3 CDMA Router Architecture 34 4.4 FIFO Buffer 34 4.5 Walsh Code Generator 35 4.6 Scheduler 37 viii 4.7 Modulator 39 4.8 Code Adder 39 4.9 Demodulator 40 4.10 Simulation Results 41 4.11 Synthesis Results 42 4.12 Timing Summary 43 Chapter 5 Comparison of Designed Routers 44 5.1 Performance Analysis of the Three Architectures 45 5.1.1 Latency 45 5.1.2 Throughput 45 Chapter 6 Conclusions and Future Work 47 6.1 Conclusions 48 6.2 Future Work 48 REFERENCES 49 PUBLICATIONS 52 ix LIST OF FIGURES Figure No. Page No. 1.1. Evolution of transistor integration on a chip 2 1.2. Communication structures in NoC 4 1.3. General Architecture of NoC 7 1.4. Flow of data packets from source node to destination node Links 7 1.5. A typical routing node 9 1.6. Network Topologies 10 2.1. The router ports for architecture I 16 2.2. The router architecture I 16 2.3. Combined register and demultiplexer 17 2.4. FIFO Unit 18 2.5. Scheduler 19 2.6. Simulation waveform of router architecture – I 20 3.1. Router architecture II 24 3.2. Internal structure of crossbar 25 3.3. Internal structure of arbiter 26 3.4. (a) Simulation waveform of router architecture – II of inputs 28 3.4. (b) Simulation waveform of router architecture – II of outputs 28 4.1. CDMA technique and principle 32 4.2. CDMA Router architecture 35 4.3. Internal structure of scheduler and conceptual diagram 37 4.4. Illustration of a virtual output queue 38 4.5. Simulation waveform of a CDMA router 41 4.6. Chipscope pro analyzer waveform 41 5.1 Comparison of three designed routers 46 x LIST OF TABLES Table No. Page No. 2.1. PERCENTAGE OF RESOURCE UTILIZATION OF FPGA-XILINX (DEVICE SELECTED – 3S500EFG320-4) 21 2.2. TIMING SUMMARY OF PROPOSED ARCHITECTURE I ON FPGA-XILINX (DEVICE SELECTED – 3S500EFG320-4) 22 3.1. PERCENTAGE OF RESOURCE UTILIZATION OF FPGA-XILINX (DEVICE SELECTED – 3S500EFG320-4) 29 3.2. PERCENTAGE OF RESOURCE UTILIZATION OF FPGA-XILINX (DEVICE SELECTED – 3S500EFG320-4) 29 4.1. TRUTH TABLE FOR 8 BIT WALSH CODE 36 4.2. PERCENTAGE OF RESOURCE UTILIZATION OF FPGA-XILINX (DEVICE SELECTED – 3S500EFG320-4) 42 4.3. TIMING SUMMARY OF PROPOSED ARCHITECTURE III ON FPGA-XILINX (DEVICE SELECTED – 3S500EFG320-4) 43 5.1. COMPARISON OF AREA AND POWER 46 xi ACRONYMS NoC Network-on-Chip SoC System-on-Chip CDMA Code Division Multiple Access IC Integrated Circuit CMOS Complementary Metal Oxide Semiconductor ITRS International Technology Roadmap for Semiconductors MAC Medium Access Control PCI Peripheral Component Interconnect IP Intellectual Property FPGA Field Programmable Gate Array VLSI Very Large Scale Integration ASIC Application Specific Integrated Circuit NI Network Interface OSI Operation Systems Interconnect FIFO First In First Out RAM Random Access Memory RR Round Robin FCFS First Come First Serve TX Transmitter MOD Modulator xii CHAPTER 1 INTRODUCTION AND OVERVIEW 1.1 INTRODUCTION A billion transistors, one million gates, thousands of circuits, hundreds of designs on a single IC chip; such intricate designs pose innumerable challenges to IC designers. The most successful IC designers overcome all such challenges to provide functionally correct and reliable operation of the IC’s. As the integration increases the cost effectiveness is also a major area of concern in IC designs. Reduced cost is one of the big attractions of integrated electronics, the cost advantage continues to increase with the evolution of technology toward the production of larger and larger circuit functions on a single semiconductor substrate; proposed by Gordon E Moore in his paper Cramming more components onto integrated circuits, 1965, the paper in which he proposed the well-known Moore’s law[1]. By 2025 the physical dimension of CMOS transistors are expected to cross the 10 nm threshold, according to a 2012 report of International Technology Roadmap for Semiconductors[2]. The graph below shows the transistor integration on a single chip over the past two decades. Now two billion transistors are integrated onto a single chip. Figure 1.1. Evolution of transistor integration on a chip 2 It is to keep pace with such intricate levels of integration that the design engineers have come up with a new design methodology called System-on-Chip (SoC) The SoC is a technology where maximum technology is crammed into the smallest possible space.
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