DOCSLIB.ORG
Explore
Sign Up
Log In
Upload
Search
Home
» Tags
» Indirect branch
Indirect branch
2. Instruction Set Architecture
Exploiting Branch Target Injection Jann Horn, Google Project Zero
Simty: Generalized SIMT Execution on RISC-V Caroline Collange
Ep 2182433 A1
Digital Design & Computer Arch. Lecture 17: Branch Prediction II
Leveraging Indirect Branch Locality in Dynamic Binary Translators
Intel Itanium 2 Processor Reference Manual
Understanding and Predicting Indirect Branch Behavior
Design of Digital Circuits Lecture 19: Branch Prediction II, VLIW, Fine-Grained Multithreading
Instruction Set Define Computer
Lecture 6 Instruction Level Parallelism (4) EEC 171 Parallel Architectures John Owens UC Davis Credits • © John Owens / UC Davis 2007–8
AMD Architecture Guidelines for Indirect Branch Control
Predicated Code
SOFTWARE TECHNIQUES for MANAGING SPECULATION on AMD PROCESSORS 2 to Mitigate the Above Described Variants, There Are a Variety of Possible Techniques Software Can Use
Optimizing Indirect Branch Prediction Accuracy in Virtual Machine Interpreters
Intel® Itanium® Architecture Software Developer's Manual, Volume 3
Compiler Support for Value-Based Indirect Branch Prediction*
Predication and Exceptions
Top View
The Microarchitecture of Intel, AMD and VIA Cpus: an Optimization Guide for Assembly Programmers and Compiler Makers
Itanium™ Software Conventions and Runtime Architecture Guide
Speculative Execution Side Channel Mitigations
ADSP-21160 SHARC DSP Instruction Set Reference, Program Flow Control
SPARC T4™ Supplement to the Oracle SPARC Architecture 2011
Speculative Execution Side Channel Mitigations
A High-Performance RISC-V to X86-64 Binary Translator
Master 512 Technical Guide
Armv8-A Instruction Set Architecture
SPARC64 V Processor Whitepaper for UNIX Server
Introduction to Microprocessors DCAP210
Security Analysis of Processor Instruction Set Architecture for Enforcing Control-Flow Integrity
The Effect of Instruction Padding on SFI Overhead
AMD64 Technology Indirect Branch Control Extension
Analyzing Effects of Trace Cache Configurations on the Prediction Of
Analysis of Transient-Execution Attacks on the Out-Of-Order CHERI- RISC-V Microprocessor Toooba
Spectre Returns! Speculation Attacks Using the Return Stack Buffer
Control-Flow Enforcement Technology Preview
Intel® Itanium® Assembler User's Guide
Instruction Flow Techniques ECE/CS 752 Fall 2017
Leandro Lupori High-Performance RISC-V Emulation Emulação De
Restoring the Performance of Indirect Branches in the Era of Spectre
Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware
Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems
Control-Flow Integrity for Real-Time Embedded Systems Nicholas Brown Worcester Polytechnic Institute
Spectre(V1/V2/V4) V.S. Meltdown(V3)
Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems Jason D