Instruction set define computer

Continue A set of abstract symbols, describing the operations of a computer program for the processor, should not be confused with the architecture of industry standards. General Concepts Instruction set Operand Instructions NOP Branch Indirect Branch vte In Computer Sciences, The Architecture Set of Instructions (ISA) is an abstract computer model. It is also called architecture or computer architecture. Implementing an ISA, such as a CPU, is called implementation. In general, the ISA identifies supported data types, registers, hardware support for basic memory management, core functions (such as memory consistency, processing modes, virtual memory) and the ISA implementation family I/O model. IsA determines the behavior of the machine code running on the implementations of this ISA in a way that does not depend on the characteristics of this implementation, providing binary compatibility between implementations. This allows multiple ISA implementations that differ in performance, physical size and cash costs (among other things), but which are capable of running the same machine code, so that lower performance, lower cost machines can be replaced by higher cost, higher machine performance without replacing the software. It also allows the evolution of microarchitectures to implement this ISA, so that new, higher performance ISA implementations can run software that works on previous generations of implementations. If the operating system supports the standard and compatible binary application interface (ABI) for a specific ISA, the machine code for this ISA and operating system will work on future implementations of this ISA and new versions of this operating system. However, if the ISA supports the launch of multiple operating systems, this does not guarantee that the machine code for one operating system will work on another operating system if the first operating system supports the code of a running machine built for another operating system. ISA can be expanded by adding instructions or other features or adding support for larger addresses and data values; implementing an extended ISA will still be able to run machine code for ISA versions without these extensions. The machine code that uses these extensions will only work on implementations that always khlay those extensions. The binary compatibility they provide makes ISAs one of the most fundamental abstractions in computing. The review of the instruction set architecture differs from the microarchitecture, which is a set of processor design methods used in a particular processor to implement a set of instructions. Processors with different may have a common set of instructions. For example, Intel Pentium and Advanced Advanced Athlon devices implement almost identical versions of the set of instructions, but have radically different internal designs. The concept of architecture, unlike the design of a particular machine, was developed by Fred Brooks at IBM during the System/360 design phase. Prior to NPL System/360 the company's computer designers were free to meet cost goals not only by selecting technologies, but also through the fashion of functional and architectural refinements. THE spread compatibility goal, by contrast, postulated a single architecture for a series of five processors covering a wide range of costs and performance. None of the five design teams could expect to be able to make adjustments to architectural specifications as a way of making it easier to achieve cost and productivity goals. Some virtual machines :p, such as Smalltalk, a Java virtual machine, and Microsoft common language, implement this by translating code for common code paths into native machine code. In addition, these virtual machines perform less commonly used code interpreting paths (see: Just in time for compilation). Transmeta implemented a set of x86 instructions on VLIW processors in this way. The ISAs ISA classification can be classified in different ways. General classification by architectural complexity. The Complex Set of Computer Instructions (CISC) has many specialized instructions, some of which can be rarely used in practical programs. A reduced set of computer instructions (RISC) simplifies the processor by effectively implementing only the instructions that are often used in programs, while less common operations are implemented as routines, resulting in additional processor time compensated by rare use. Other types include very long instruction architecture (VLIW), as well as a closely related long instructional word (LIW) and explicitly parallel instructional computational architecture (EPIC). These architectures seek to exploit scheduling parallelism with fewer hardware than RISC and CISC, making the compiler responsible for the instruction and planning problem. Architectures with even less complexity have been studied, such as a minimum set of computer instructions (MISC) and one computer set of instructions (OISC). In theory, these are important types, but they have not been commercialized. The language of the instructions machine is built from discrete statements or instructions. In the processing architecture of this instruction, you can specify: specific registers (for arithmetic, address, or function management) of specific memory sites (or bias to them) of specific address modes (used to interpret operands) More complex operations are built by combining these simple instructions, which are consistently, or otherwise directed instructions on the flow of control. Types of Instructions Examples of Operations common to many sets of instructions include: Data processing and memory operations Set the register to a fixed permanent value. Copying data from memory to register, or vice versa (machine instruction is often referred to as moving; however, the term is misleading). Used to store the contents of the register, the result of the calculation, or to obtain stored data to do the calculation on it later. Often referred to as load and storage operations. Read and write data from hardware devices. Add, subtract, multiply, or divide the values of the two registers by placing the result in the register, perhaps by installing one or more conditions codes in the status registry. increment, decrement in some ISAs, keeping operand fetch in trivial cases. We perform bit operations, such as taking the connection and disconnecting the corresponding bits in a pair of registers, taking the denial of each bit in the register. Compare the two values in registers (for example, to see if one is smaller or if they are equal). Instructions for floating point for arithmetic on floating point numbers. Manage branch flow operations to another location in the program and follow instructions there. Conditional branching to another place, if a certain condition holds. Indirectly a branch to another place. Call another block of code while saving the location of the following instructions as a point for a return. Download/store data in and out of the coprocessor or by exchanging with processor registers. We perform coprocessor operations. Complex instructions processors can include complex instructions in a set of instructions. One tricky instruction does what can take a lot of instructions on other computers. (quote is necessary) These instructions are characterized by instructions that take several steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of the simple instructions implemented by the processor. Some examples of complex instructions include: transferring multiple registers in or out of memory (especially a stack) immediately moving large blocks of memory (such as a string copy or DMA transmission) to a complex integrator and floating point arithmetic (e.g. square root, or transcendental functions such as logarithm, sinus, cosine, etc.) SIMD instructions, a single instruction, performing the operation at many homogeneous values in parallel, perhaps in the dedicated SIMD registers, performing atomic instructions for testing and kit, or other instructions for learning the readable modification that perform ALU operations with an error of memory, rather than with instructions on the register. CISC than in RISC instructions sets, but RISC instructions sets can also include them. RiSC set of instructions, as a rule, not ALU operations with memory opandas or instructions for moving large memory blocks, but most RISC instructions include SIMD or vector instructions that perform the same arithmetic operation on multiple data fragments at the same time. SIMD instructions have the ability to manipulate large vectors and matrixes in minimal time. SIMD instructions make it easy to use algorithms that normally work in sound, image, and video processing. Various SIMD sales have been brought to the market under trade names such as MMX, 3DNow!, and AltiVec. One instruction instruction one instruction can have several fields that define a logical operation, and can also include source and destination addresses and fixed values. This is the INSTRUCTION MIPS Add immediately, which allows the selection of sources and appointment registers and the inclusion of a small permanent. In traditional architectures, the instruction includes an opcode that identifies an operation to perform, such as adding memory content to register and zero or more opera agents that can specify registers, memory locations, or literal data. Operators may have address modes that determine their meaning, or may be in fixed fields. In a very long word instruction (VLIW) architecture that includes many microcode architectures, several simultaneous and operands are listed in the same instruction. Some exotic set of instructions do not have an opcode field, such as the architectures launched by transport (TTA), only operand (s). Forth's virtual machine and other 0-operands do not have any areas to indicate operand, such as some stack machines, including NOSC. Conditional instructions often have a predicate field - several bits that encode a specific condition to trigger an operation that will be performed rather than performed. For example, a conditional branch instruction will transfer control if the condition is correct, so that the execution goes to another part of the program rather than transfer control if the condition is false, so that the execution continues sequentially. Some sets of instructions also have conditional moves, so the move will be performed, and the data stored in the target location if the condition is correct and not fulfilled, and the target location is not changed if the condition is false. Similarly, IBM z/Architecture has a conditional store instruction. Several sets of instructions include a predicate field in each instruction; it's called the predicate of the branch. The number of sets of operands can be categorized by the maximum number of operas explicitly specified in the instructions. (In subsequent examples, a, b and c are (direct or calculated) addresses related to reg1 and so on.) C - AB 0-operand (zero-address machines), so-called stack machines: All arithmetic arithmetic occurs with the top one or two positions in the stack: click a, push b, add, pop c. C and A'B needs four instructions. For stack machines, the terms 0-operands and zero address apply to arithmetic instructions, but not to all instructions, as instructions on 1- opera and pop music are used to access memory. 1-operand (one machine address), the so-called battery machines, include early computers and many small microcontrollers: most instructions specify one right operand (i.e., constant, register, or place of memory), with an implicit battery like left operand (and destination if there is one): download, add b, store C. C and A'B needs three instructions. 2-opera - many CISC and RISC machines fall into this category: CISC - move A to C; then add B to C. C and A'B need two instructions. This effectively stores the result without explicit store instructions. CISC - Often machines are limited to one memory opend in instruction: load a,reg1; Add b,reg1; Shop reg1,c; This requires a load/shop pair for any memory movement, whether the result is an increase stored elsewhere, like C and A'B, or in the same memory location: A q A'B. C and A'B needs three instructions. RISC - Requirement of explicit memory loads, instructions will be: download a,reg1; Load b,reg2; Add reg1,reg2; Store reg2,c. C and ASB needs four instructions. 3-operands that allow you to reuse data better: CISC - Or, on machines limited to two memory operators on instruction, move a,reg1; Add reg1,b,c; C and ABB needs two instructions. RISC - Arithmetic instructions only use registers, so explicit load/shop instructions are required: download a,reg1; Load b,reg2; Add reg1'reg2-'gt;reg3; Shop reg3,c; C and ABB requires four instructions. Unlike 2-operand or 1-operand, this leaves all three values a, b and c in registers available for further reuse. More CISC machines allow different targeting modes that allow more than 3 operands (registers or access to memory), such as VAX POLY polynomial instruction assessment. Due to the large number of bits required to encode three registers of 3-opera instruction, RISC architectures that have 16-bit instructions are invariably 2- opera designs such as atmel AVR, TI MSP430, and some versions of ARM Thumb. RISC architectures that have 32-bit instructions are typically 3-opera projects such as ARM Architecture, AVR32, MIPS, Power ISA and SPARC. Each instruction explicitly indicates a certain number of operas (registers, memory locations, or direct values). Some instructions give one or both operands implicitly, for example, by on top of the stack or in an implicit register. If some of the operas are given implicitly, fewer operas need to be specified in the How to. When the direction of the operand clearly indicates the destination, an additional operand must be delivered. Consequently, the number of operas encoded in the instructions may differ from the mathematically required number of arguments for logical or arithmetic surgery.) Operands are either encoded in the opcode view instructions, or are given as values or addresses after opcode. Register register pressure measures the availability of free registers at any given time during the program. Register pressure is high when a large number of available registers are used; thus, the higher the register pressure, the more often the contents of the register should be poured into the memory. Increasing the number of registers in architecture reduces register pressure, but increases cost. While built-in sets of instructions, such as Thumb, suffer from extremely high register pressure because they have small register sets, RISC general purpose ISAs, such as MIPS and Alpha, enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to a variety of address modes and optimizations (such as sub-registration address, memory operands in ALU instructions, absolute address, PC address and spill registration) that ISAs CISC offers. The length of the instruction the size or length of the instruction varies widely, from just four bits in some microcontrollers to many hundreds of bits in some VLIW systems. Processors used in personal computers, mainframes and supercomputers have instructions of 8 to 64 bits. The longest possible instruction on x86 is 15 bytes (120 bits). In the set of instructions, different instructions can have different lengths. In some architectures, especially most abbreviated computers of the instruction set (RISC), the instructions are fixed length, usually corresponding to the size of the word of this architecture. In other architectures, the instructions have a variable length, usually integral multiples on the side or half-word. Some, such as the thumb extension ARM, have mixed variable encoding, i.e. two fixed, usually 32-bit and 16-bit coding, where instructions cannot be mixed freely but must be switched between the branch (or the exception boundary in ARMv8). The RISC set of instructions usually has a fixed instruction length (often 4 bytes and 32 bits), while a typical set of CISC instructions can have instructions of varying lengths (from 1 to 15 bytes for x86). Fixed-length instructions are less difficult to handle than variable length instructions for several reasons (for example, you don't need to check whether the instruction crosses the cache line or virtual boundary of the memory page, and so there are several optimize for speed. The density of the code In early computers, the memory was So minimizing the size of the program to make sure that it will fit into limited memory is often central. Thus, the cumulative size of all the instructions required to complete a particular task, the density of the code, was an important characteristic of any set of instructions. High-density computers often have complex instructions for entering procedures, parametrical returns, cycles, etc. (so retroactively called Set Computers, CISC). However, more typical or frequent CISC instructions simply combine a basic ALU operation, such as add, with access to one or more opernds in memory (using address modes such as direct, indirect, index, etc.). Some architectures may allow two or three operands (including the result) directly into memory or may be able to perform functions such as automatic pointer zoom, etc. For the first time in a period of fast-growing memory systems, computers with a reduced set of instructions, RISC, were widely introduced. They sacrifice code density to simplify the implementation scheme, and try to improve performance by higher clock frequencies and more registers. One RISC instruction typically only performs one operation, such as adding registers or loading from a memory location to a register. The RISC set of instructions usually has a fixed-length instruction, while the typical CISC set of instructions has instructions of varying lengths. However, because RISC computers typically require more and more instructions to do the task, they are inherently making less optimal use of the bus bandwidth and memory cache. Some built-in RICs, such as Thumb and AVR32, tend to have very high density due to a method called code compression. This method packs two 16-bit instructions into one 32-bit word, which is then unpacked at the decoding stage and performed as two instructions. The Minimum Set of Computer Instructions (MISC) is a form of stack machine where there are several separate instructions (16-64), so multiple instructions can be fit into a one-word machine. These types of nuclei often take a little silicon to implement, so they can be easily implemented in FPGA or in multi-core form. The density of the MISC code is similar to that of the RISC code; The increased density of the instruction is offset by the requirement for more primitive instructions to complete the task. (quote is necessary) There have been studies on compression as a mechanism to improve code density. The mathematics of Kolmogorov's complexity describes the problems and limits of this. View components of the program are rarely specified using their internal, numerical form (machine code); they can be indicated by programmers using the language of the au writing assembly, or, more often than not, can be obtained from compiler languages. The design of the set of instructions is a complex issue. For the microprocessor there were two stages in history. First, CISC (Complex Instructions Set Computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many of the instructions in the set could be eliminated. The result is a RISC (Reduced Instruction Set Computer), an architecture that uses a smaller set of instructions. A simpler set of instructions can offer the potential for higher speeds, smaller processor sizes, and lower power consumption. However, a more complex set can optimize overall operations, improve memory and cache efficiency, or simplify programming. Some instructions set designers to reserve one or more opcodes for some kind of system call or software interruption. For example, MOS Technology 6502 uses 00H, Cylog No80 uses eight C7,D7,DF,E7,EF,F7,FFH codes, while Motorola 68000 uses codes in the A000 range. AFFFH. Fast virtual machines are much easier to implement if a set of instructions meets the requirements of Popek and Goldberg virtualization. The NOP slide used in software known to the immune system is much easier to implement if the unprogramried state of memory is interpreted as NOP. In multi-processor systems, synchronization algorithms that aren't blocking are much easier to implement if a set of instructions includes support for something like bring-and-add, load-link/shop-conditional (LL/SC) or atomic comparison and swap. Implementation of a set of instructions Any given set of instructions can be implemented in a variety of ways. All ways to implement a specific set of instructions provide the same programming model, and all implementations of this set of instructions can be executed the same way. Different ways of implementing a set of instructions give different trade-offs between the cost, When designing the microarchitecture of the processor, engineers use hard-wired electronic circuit blocks (often developed separately) such as adders, multiplexers, counters, registers, ALUs, etc. There are two main ways to create a control unit to implement this description (although many projects use middle ways or trade-offs): Some computer projects have a tough full set of decoding and sequencing instructions (just like the rest of the microarchitecture). Other projects use microcode procedures or tables (or both) to do so, usually as on a ROMs chip or PLAs both (although separate RAMs and ROMs have been used historically). The Western Digital MCP-1600 is an older example, using a dedicated separate ROM for the microcode. Microcode. The designs use a combination of wired structure and microcode for control unit. Some processor designs use a wriggling control store - they compile a set of instructions for wriggling RAM or flash inside the processor (such as the Rekursiv and Imsys Cjip processor), or FPGA (reconfigurable calculations). The ISA can also be emulated in the software by a translator. Naturally, because of the overhead interpretation costs, this is slower than directly running programs on emulation equipment if the hardware runs the emulator an order of magnitude faster. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready. Implementation details often have a strong impact on the specific instructions chosen for the set of instructions. For example, many implementations of the instructions pipeline allow you to use only one memory load or memory reserve per instruction, resulting in a load store architecture (RISC). In another example, some early ways to implement the instructions pipeline resulted in a slot delay. The demands of high-speed digital signal processing pushed in the opposite direction, forcing instructions to be carried out in a certain way. For example, for digital filters to run quickly enough, the MAC instruction in a typical digital signal processor (DSP) should use a kind of Harvard architecture that can get instruction and two words of data at the same time, and this requires a multiplier multiplicing of a single loop. See also Comparison Architectures Set Of Instructions Computer Architecture Processor Design Emulator Simulator List instructions set instructions set simulator OVPsim complete simulator systems, providing the ability to create/model/emulate any set of instructions using C and standard APIs Registration of Transmission Language (RTL) Micro-Operation Links - Pew, Emerson W.; Johnson, Lyle R.; Palmer, John H. (1991). 360 and the beginning of 370 IBM systems. MIT Press. ISBN 0- 262-16123-0. Crystal Chen; Greg Novick; Kirk Shimano (December 16, 2006). RISC Architecture: RISC vs. CISC. cs.stanford.edu. received on February 21, 2015. Fort Resources: NoSC Postal List Archive. strangegizmo.com archive from the original 2014-05-20. Received 2014-07-25. a b c Evolution of RISC technology at IBM by John Coca - IBM Journal of R'D, Volume 44, Numbers 1/2, p.48 (2000) - Page, Daniel (2009). 11. Compilers. A practical introduction to computer architecture. Springer. page 464. Bibcode:2009pica.book .... P. ISBN 978-1-84882-255-9. Venkat, Ashish; Tulsen, Dean M. (2014). Using ISA Diversity: Design of the Multiprocessor microprocessor Heterogeneous-ISA Chip. 41st Annual International computer architecture. Intel® 64 and IA-32 Architecture Software Developer Guide. Intel. Received on July 12, 2012. Weaver, Weaver, M.; Mackie, Sally A. (2009). Code density applies to new architectures. IEEE International Conference on Computer Development. CiteSeerX 10.1.1.398.1967. doi:10.1109/ICCD.2009.5413117. Hanssle, Jack (February 26, 2001). Proactive debugging. embedded.com . - Great microprocessors past and present (V 13.4.0). cpushack.net. Received 2014-07-25. Further reading Bowen, Jonathan. (July-August 1985). Standard microprocessor programming cards. Microprocessors and microsystems. 9 (6): 274–290. doi:10.1016/0141-9331(85)90116-4. External Links Design Microprocessor Wikibook has a page on the theme: Instructions To Set Media Architecture related to the instruction set of architectures on The Commons Programming Textfiles: Bowen Instruction Summary map Mark Smotherman's Historic Computer Samples Page extracted from define reduced instruction set computer. define complex instruction set computer architecture. define instruction set in computer science. define and explain reduced instruction set computer. define the complex instruction set computer. define computer term instruction set

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