Master 512 Technical Guide
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Wakefield 2006 RISC OS Computer Show
I would like to welcome you all to this, our eleventh annual show in Wakefield. There have been many ups and downs over the last eleven years, since the first show at Cedar Court, organised in thirteen weeks, which ended up taking over the entire hotel. Ever since then, we have been at our current venue of Thornes Park. Over the years we have had many interesting attractions and features, such as the guest appearance by Johnny Ball one year. Of course, the show has seen many new hardware and software launches and previews over the years, some more successful then others: Kinetic, Peanut, Phoebe, StrongARM, Vantage, RiScript and so on. In fact, this year it is ten full years since we saw the very first StrongARM at the first Wakefield Show, as well as being the 25th Anniversary of the BBC Micro! Even now, we still have people developing for this famous microcomputer, which helped to start the home computer revolution. Be sure to visit both the JGH BBC Software and Domesday System stands during your visit. The Domesday Project is another superb example of how advanced we were with the BBC Master and other Acorn products of the 1980s. Now we are looking to the future with the new A9home, which is expected to be on retail sale or available for ordering at the show. Over the years we have had visitors to the show from all over the world, from countries such as New Zealand, Australia, South Africa, Belgium, Finland, Sweden and the USA; not bad for an amateur show! Another long-standing attraction of the show is of course the charity stall, which allows redundant equipment to be recycled, and through your kind support the stall has raised many thousands of pounds, primarily for the Wakefield Hospice, over the years. -
Archimedes PC Emulator
Archimedes PC Emulator PC emulators are not new, but so far they have had limited success in their job of enabling your chosen micro to run PC-compatible software. Simon Jones unveils Acorns PC Emulator package for the Archimedes range of micros to see how well it performs in action. At this years PCW Show, Acorn proudly displayed its PC Emulator package for the Archimedes range of computers, which is claimed to allow packages written for the IBM PC to run on an Archimedes. Acorn was demonstrating the Emulator running dBase III+ and Lotus 1-2-3 at the show and, as I only managed a quick glance at the Emulator then, I was pleased to get the opportunity to examine the product at close quarters. Having seen other attempts at PC compatibility, such as pc-ditto (reviewed in PCW, October) I was sceptical to say the least. The Archimedes carries on the Acorn tradition, having a lot in common with the BBC Micro and the BBC Master series. Indeed, the Archimedes will run most of the well-behaved software written for the BBC computers. However, the Archimedes and the BBC micros differ radically in the CPU they use and the amount of RAM available. Based on Acorns RISC processor, the Archimedes 440 is blindingly fast and, with 4Mbytes of memory, it is not short functions to those in MS-DOS. This is cellaneous keys between the main of space — a problem which caused the more than a little confusing if you are group and the numerics. The back- downfall of the BBC Micros. -
2. Instruction Set Architecture
!1 2. ISA Gebotys ECE 222 2. Instruction Set Architecture “Ideally, your initial instruction set should be an exemplar, …” " Instruction set architecture (ISA) defines the interface between the hardware and software# " instruction set is the language of the computer# " RISCV instructions are 32-bits, instruction[31:0]# " RISC-V assembly1 language notation # " uses 64-bit registers, 64-bits refer to double word, 32-bits refers to word (8-bits is byte).# " there are 32 registers, namely x0-x31, where x0 is always zero # " to perform arithmetic operations (add, sub, shift, logical) data must always be in registers # " the number of variables in programs is typically larger than 32, hence ‘less frequently used’ [or those used later] variables are ‘spilled’ into memory [spilling registers]# " registers are faster and more energy e$cient than memory# " for embedded applications where code size is important, a 16-bit instruction set exists, RISC-V compressed (e.g. others exist also ARM Thumb and Thumb2)# " byte addressing is used, little endian (where address of 64-bit word refers to address of ‘little' or rightmost byte, [containing bit 0 of word]) so sequential double word accesses di%er by 8 e.g. byte address 0 holds the first double word and byte address 8 holds next double word. (Byte addressing allows the supports of two byte instructions)# " memory contains 261 memory words - using load/store instructions e.g. 64-bits available (bits 63 downto 0, 3 of those bits are used for byte addressing, leaving 61 bits)# " Program counter register (PC) -
Tube Application Note
16th January 1992 Support Group Application Note Number: 004 Issue: 1 Author: Tube Application Note Applicable Related Hardware : Application BBC B Notes: BBC B+ BBC Master 128 Copyright © Acorn Computers Limited 1992 Every effort has been made to ensure that the information in this leaflet is true and correct at the time of printing. However, the products described in this leaflet are subject to continuous Support Group development and improvements and Acorn Computers Limited reserves the right to change its specifications at any time. Acorn Computers Limited cannot accept liability for any loss Acorn Computers Limited or damage arising from the use of any information or particulars in this leaflet. ACORN, Acorn House ECONET and ARCHIMEDES are trademarks of Acorn Computers Limited. Vision Park Histon Cambridge CB4 4AE Support Group Application Note No. 004, Issue 1 16th June 1992 Overview One of the BBC Microcomputer's strengths lies in its sophisticated Operating System, the MOS. This operating system has a very fast and flexible response to Interrupts, which allows the machine to take a wide range of peripherals and handle them with ease. The TUBE is a fast bus interface through which additional Co-processors (also called second processors) can be added. when a co-processor is connected to the TUBE interface, the BBC Micro continues to look after all of the I/O processing, whilst the additional co-processor now carries out the task of running the Language Application. The Co-Processor The co-processor can be based on any microprocessor chip, and can have any memory size that this chip can address. -
NASM – the Netwide Assembler
NASM – The Netwide Assembler version 2.14rc7 © 1996−2017 The NASM Development Team — All Rights Reserved This document is redistributable under the license given in the file "LICENSE" distributed in the NASM archive. Contents Chapter 1: Introduction . 17 1.1 What Is NASM?. 17 1.1.1 License Conditions . 17 Chapter 2: Running NASM . 19 2.1 NASM Command−Line Syntax . 19 2.1.1 The −o Option: Specifying the Output File Name . 19 2.1.2 The −f Option: Specifying the Output File Format . 20 2.1.3 The −l Option: Generating a Listing File . 20 2.1.4 The −M Option: Generate Makefile Dependencies. 20 2.1.5 The −MG Option: Generate Makefile Dependencies . 20 2.1.6 The −MF Option: Set Makefile Dependency File. 20 2.1.7 The −MD Option: Assemble and Generate Dependencies . 20 2.1.8 The −MT Option: Dependency Target Name . 21 2.1.9 The −MQ Option: Dependency Target Name (Quoted) . 21 2.1.10 The −MP Option: Emit phony targets . 21 2.1.11 The −MW Option: Watcom Make quoting style . 21 2.1.12 The −F Option: Selecting a Debug Information Format . 21 2.1.13 The −g Option: Enabling Debug Information. 21 2.1.14 The −X Option: Selecting an Error Reporting Format . 21 2.1.15 The −Z Option: Send Errors to a File. 22 2.1.16 The −s Option: Send Errors to stdout ..........................22 2.1.17 The −i Option: Include File Search Directories . 22 2.1.18 The −p Option: Pre−Include a File . 22 2.1.19 The −d Option: Pre−Define a Macro . -
Exploiting Branch Target Injection Jann Horn, Google Project Zero
Exploiting Branch Target Injection Jann Horn, Google Project Zero 1 Outline ● Introduction ● Reverse-engineering branch prediction ● Leaking host memory from KVM 2 Disclaimer ● I haven't worked in CPU design ● I don't really understand how CPUs work ● Large parts of this talk are based on guesses ● This isn't necessarily how all CPUs work 3 Variants overview Spectre Meltdown ● CVE-2017-5753 ● CVE-2017-5715 ● CVE-2017-5754 ● Variant 1 ● Variant 2 ● Variant 3 ● Bounds Check ● Branch Target ● Rogue Data Cache Bypass Injection Load ● Primarily affects ● Primarily affects ● Affects kernels (and interpreters/JITs kernels/hypervisors architecturally equivalent software) 4 Performance ● Modern consumer CPU clock rates: ~4GHz ● Memory is slow: ~170 clock cycles latency on my machine ➢ CPU needs to work around high memory access latencies ● Adding parallelism is easier than making processing faster ➢ CPU needs to do things in parallel for performance ● Performance optimizations can lead to security issues! 5 Performance Optimization Resources ● everyone wants programs to run fast ➢ processor vendors want application authors to be able to write fast code ● architectural behavior requires architecture documentation; performance optimization requires microarchitecture documentation ➢ if you want information about microarchitecture, read performance optimization guides ● Intel: https://software.intel.com/en-us/articles/intel-sdm#optimization ("optimization reference manual") ● AMD: https://developer.amd.com/resources/developer-guides-manuals/ ("Software Optimization Guide") 6 (vaguely based on optimization manuals) Out-of-order execution front end out-of-order engine port (scheduler, renaming, ...) port instruction stream add rax, 9 add rax, 8 inc rbx port inc rbx sub rax, rbx mov [rcx], rax port cmp rax, 16 .. -
NASM — the Netwide Assembler Version 2.09.04
NASM — The Netwide Assembler version 2.09.04 -~~..~:#;L .-:#;L,.- .~:#:;.T -~~.~:;. .~:;. E8+U *T +U' *T# .97 *L E8+' *;T' *;, D97 `*L .97 '*L "T;E+:, D9 *L *L H7 I# T7 I# "*:. H7 I# I# U: :8 *#+ , :8 T, 79 U: :8 :8 ,#B. .IE, "T;E* .IE, J *+;#:T*" ,#B. .IE, .IE, © 1996−2010 The NASM Development Team — All Rights Reserved This document is redistributable under the license given in the file "LICENSE" distributed in the NASM archive. Contents Chapter 1: Introduction . .15 1.1 What Is NASM? . .15 1.1.1 Why Yet Another Assembler?. .15 1.1.2 License Conditions . .15 1.2 Contact Information . .16 1.3 Installation. .16 1.3.1 Installing NASM under MS−DOS or Windows . .16 1.3.2 Installing NASM under Unix . .17 Chapter 2: Running NASM . .18 2.1 NASM Command−Line Syntax . .18 2.1.1 The −o Option: Specifying the Output File Name . .18 2.1.2 The −f Option: Specifying the Output File Format . .19 2.1.3 The −l Option: Generating a Listing File . .19 2.1.4 The −M Option: Generate Makefile Dependencies . .19 2.1.5 The −MG Option: Generate Makefile Dependencies . .19 2.1.6 The −MF Option: Set Makefile Dependency File . .19 2.1.7 The −MD Option: Assemble and Generate Dependencies. .19 2.1.8 The −MT Option: Dependency Target Name. .20 2.1.9 The −MQ Option: Dependency Target Name (Quoted) . .20 2.1.10 The −MP Option: Emit phony targets. .20 2.1.11 The −F Option: Selecting a Debug Information Format . -
Simty: Generalized SIMT Execution on RISC-V Caroline Collange
Simty: generalized SIMT execution on RISC-V Caroline Collange To cite this version: Caroline Collange. Simty: generalized SIMT execution on RISC-V. CARRV 2017: First Work- shop on Computer Architecture Research with RISC-V, Oct 2017, Boston, United States. pp.6, 10.1145/nnnnnnn.nnnnnnn. hal-01622208 HAL Id: hal-01622208 https://hal.inria.fr/hal-01622208 Submitted on 7 Oct 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Simty: generalized SIMT execution on RISC-V Caroline Collange Inria [email protected] ABSTRACT and programming languages to target GPU-like SIMT cores. Be- We present Simty, a massively multi-threaded RISC-V processor side simplifying software layers, the unification of CPU and GPU core that acts as a proof of concept for dynamic inter-thread vector- instruction sets eases prototyping and debugging of parallel pro- ization at the micro-architecture level. Simty runs groups of scalar grams. We have implemented Simty in synthesizable VHDL and threads executing SPMD code in lockstep, and assembles SIMD synthesized it for an FPGA target. instructions dynamically across threads. Unlike existing SIMD or We present our approach to generalizing the SIMT model in SIMT processors like GPUs or vector processors, Simty vector- Section 2, then describe Simty’s microarchitecture is Section 3, and izes scalar general-purpose binaries. -
First Osborne Group (FOG) Records
http://oac.cdlib.org/findaid/ark:/13030/c8611668 No online items First Osborne Group (FOG) records Finding aid prepared by Jack Doran and Sara Chabino Lott Processing of this collection was made possible through generous funding from the National Archives’ National Historical Publications & Records Commission: Access to Historical Records grant. Computer History Museum 1401 N. Shoreline Blvd. Mountain View, CA, 94043 (650) 810-1010 [email protected] August, 2019 First Osborne Group (FOG) X4071.2007 1 records Title: First Osborne Group (FOG) records Identifier/Call Number: X4071.2007 Contributing Institution: Computer History Museum Language of Material: English Physical Description: 26.57 Linear feet, 3 record cartons, 5 manuscript boxes, 2 periodical boxes, 18 software boxes Date (bulk): Bulk, 1981-1993 Date (inclusive): 1979-1997 Abstract: The First Osborne Group (FOG) records contain software and documentation created primarily between 1981 and 1993. This material was created or authored by FOG members for other members using hardware compatible with CP/M and later MS and PC-DOS software. The majority of the collection consists of software written by FOG members to be shared through the library. Also collected are textual materials held by the library, some internal correspondence, and an incomplete collection of the FOG newsletters. creator: First Osborne Group. Processing Information Collection surveyed by Sydney Gulbronson Olson, 2017. Collection processed by Jack Doran, 2019. Access Restrictions The collection is open for research. Publication Rights The Computer History Museum (CHM) can only claim physical ownership of the collection. Users are responsible for satisfying any claims of the copyright holder. Requests for copying and permission to publish, quote, or reproduce any portion of the Computer History Museum’s collection must be obtained jointly from both the copyright holder (if applicable) and the Computer History Museum as owner of the material. -
APP229 Acorn Education News Issue 6 June 1989 6Th Edition
Announcing a new BBC ISSUE computer - the Acorn A3000 6 JUNE 1989 The A3000, Acorn's new Archimedes 6502 emulator allows access to many computer for primary and secondary edu- BBC B and Master 128 software packages cation, has been enthusiastically received (where copyright permits). On top of this, by education, software producers and the an optional PC Emulator makes it possible computer press. Since 1982, when the to run MS-DOS packages on the machine. BBC Model B was launched, Acorn has offered outstanding power, performance The A3000 retails at just £649 + VAT and ease of use to users in schools and the (educational prices are available through Inside: home. The A3000 once again leads the Acorn dealers) so that many more schools, way with its advanced RISC technology. including primary schools, will be able to Computer-designed cards bring in benefit from 32-bit technology, with the cash The new machine is like the Master 128 in powerful sound and graphics and an easy- Snaps and snippets that it incorporates its full PC-style key- to-use mouse and pointer interface. The Let the BBC Acorn User Show board and processor into a single unit. But A3000 is being used by peripheral make your day in addition the A3000 has an integral 3.5 and software developers and is available to inch floppy disc drive on the right hand LEA's for demonstration and evaluation. Two-day networking conference side of the case. The 32-bit RISC chip set The machine can be first purchased at the fixed for September has a full 1 Mbyte of fast access RAM, in BBC Acorn User Show at London's Master is the tops for special needs line with the demand for a memory ca- Alexandra Palace from 21-23 July. -
Acorn Engineering News Issue 2
Acorn Engineering News Issue 2 CONTENTS PAGE Introduction 1 Archimedes Field Change Orders 2 Disc Compatibility and Transferring 2 Software to the Archimedes Archimedes Keyboards 3 Archimedes ROM upgrades 3 Archimedes Serial Port 4 FileStore Service 4 Econet 5 Customer Support 6 Common Problems Section 7 External Second Processor Unit - Tube ULA 7 Master 128 8 Master Compact 8 Archimedes 8 Test Equipment 9 Service Reports / Obtaining Spares 9 Acorn Warranty - reminder 10 Repair of Hardware - external agencies 10 Connecting a 5.25 inch Disc Drive 14 to a Master Compact Service Capability of Dealers / ASCs 15 Unofficial variations - warranty void 15 View family 15 Upgrades 16 Dealer / ASC Servicing Questionnaire 17 Appendices Archimedes User Registration form Compact Drive cable diagram FileStore E01 Circuit Diagram ACORN ENGINEERING NEWS REF. 9990031 DECEMBER 1987 ALL ENQUIRIES TO: Acorn Computers Limited Telephone (0223) 214411 Cambridge Technopark Telex 81152 ACNNMR G 645 Newmarket Road Fax (0223) 214382 Cambridge CB5 8PB, England Viewdata (0223) 243642 Customer Services Department Acorn Computers Limited Cambridge Technopark 645 Newmarket Road Cambridge CB5 8PB Telephone 0223 214411 Telex 81152 ACNNMR G Fax No 0223 214382 Direct dealer / ASC lines Support 0223 215452 Engineering / Returns 0223 215454 Dear Colleague Welcome to an edition of Engineering News. This is the last version that you will receive on paper, as we will be putting future Engineering Information on SID - the Support Information Database. This should allow us to be considerably more flexible with Engineering Information, as well as the ability to include test programs and the like in Telesoftware. As well as just Engineering information, I have included some more general support information on other areas too - so you may wish to show this document around your organisation. -
Ep 2182433 A1
(19) & (11) EP 2 182 433 A1 (12) EUROPEAN PATENT APPLICATION published in accordance with Art. 153(4) EPC (43) Date of publication: (51) Int Cl.: 05.05.2010 Bulletin 2010/18 G06F 9/38 (2006.01) (21) Application number: 07768016.3 (86) International application number: PCT/JP2007/063241 (22) Date of filing: 02.07.2007 (87) International publication number: WO 2009/004709 (08.01.2009 Gazette 2009/02) (84) Designated Contracting States: • AOKI, Takashi AT BE BG CH CY CZ DE DK EE ES FI FR GB GR Kawasaki-shi HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE Kanagawa 211-8588 (JP) SI SK TR Designated Extension States: (74) Representative: Ward, James Norman AL BA HR MK RS Haseltine Lake LLP Lincoln House, 5th Floor (71) Applicant: Fujitsu Limited 300 High Holborn Kawasaki-shi, Kanagawa 211-8588 (JP) London WC1V 7JH (GB) (72) Inventors: • TOYOSHIMA, Takashi Kawasaki-shi Kanagawa 211-8588 (JP) (54) INDIRECT BRANCHING PROGRAM, AND INDIRECT BRANCHING METHOD (57) A processor 100 reads an interpreter program the indirect branch instruction in a link register 120c (the 200a to start an interpreter. The interpreter makes branch processor 100 internally stacks the branch destination prediction by executing, in place of an indirect branch addresses also in a return address stack 130) in inverse instruction that is necessary for execution of a source order and reading the addresses from the return address program 200b, storing branch destination addresses in stack 130 in one at a time manner. EP 2 182 433 A1 Printed by Jouve, 75001 PARIS (FR) 1 EP 2 182 433 A1 2 Description vised and brought into practical use.