EE3032 Introduction to VLSI Design

Jin-Fu Li Department of Electrical Engineering National Central University Jhongli, Taiwan

A

C

B

C=AxB

abcd z

Outline

Chapter 1: Introduction to CMOS Circuits

Chapter 2: MOS Transistor Theory

Chapter 3: Fabrication of CMOS Integrated Circuits

Chapter 4: Electrical Characteristics of CMOS Circuits

Chapter 5: Elements of Physical Design

Chapter 6: Combinational Circuit Design

Chapter 7: Sequential Circuit Design

Chapter 8: Introduction to 3D Integration using TSV

Appendix

Homeworks Chapter 1 Introduction to CMOS Circuit Design

Jin-Fu Li Advanced Reliable Syym(E)L.stems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan

Outline † Introduction † MOS Transistor Switches † CMOS Logic † Circuit and System Representation

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

1 Binary Counter

a Present Next state A state b

abAB B 0001 0110 1011 1100 A = a’b + ab’ CK B = a’b’ + ab’ CLR

Source: Prof. V. D. Agrawal

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1-bit Multiplier

A

C

B

C=AxB

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2 Switch: MOSFET † MOSFETs are basic electronic devices used to direct and control logic signals in IC design „ MOSFET: Metal-Oxide-Semiconductor Field- Effect Transistor „ N-type MOS (NMOS) and P-type MOS (PMOS) „ Voltage-controlled switches † A MOSFET has four terminals: gate, source, drain, and substrate (body) † Complementary MOS (CMOS) „ Using two types of MOSFETs to create logic networks „ NMOS & PMOS

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Silicon Lattice and Dopant Atoms † Pure silicon consists of a 3D lattice of atoms „ Silicon is a Group IV element and it forms covalent bonds with four adjacent atoms „ It is a poor con duc tor † N-type (P-type) semiconductor „ By introducing small amounts of Group V-As (Group III-B) into the silicon lattice

Si Si Si Si Si Si Si Si Si - + + - Si Si Si Si As Si Si B Si

Si Si Si Si Si Si Si Si Si

Lattice of pure Lattice of N-type Lattice of P-type Silicon Semiconductor Semiconductor Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

3 P-N Junctions † A junction between p-type and n-type semiconductor forms a diode. † Current flows only in one direction

p-type n-type

anode cathode

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NMOS Transistor † Four terminals: gate, source, drain, body † Gate–oxide–body stack looks like a capacitor „ Gate and body are conductors

„ SiO2 (oxide) is a very good insulator „ Called metal–oxide–semiconductor (MOS) capacitor „ Even though gate is no longer made of metal

SourceGate Drain Polysilicon

SiO2

n+ n+

p bulk Si

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4 NMOS Operations † Body is commonly tied to ground (0 V) † When the gate is at a low voltage: „ P-type body is at low voltag e „ Source-body and drain-body diodes are OFF „ No current flows, transistor is OFF

SourceGate Drain Polysilicon

SiO2

0 n+ n+ S D p bulk Si

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NMOS Operations (Cont.) † When the gate is at a high voltage: „ Positive charge on gate of MOS capacitor „ Negative charge attracted to body „ Inverts a channel under gate to n-type „ Now current can flow through n-type silicon from source through channel to drain, transistor is ON

SourceGate Drain Polysilicon

SiO2

1 n+ n+ S D p bulk Si

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5 PMOS Operations † Similar, but doping and voltages reversed

„ Body tied to high voltage (VDD) „ Gate low: transistor ON „ Gate high: transistor OFF „ Bubble indicates inverted behavior

SourceGate Drain Polysilicon

SiO2

p+ p+

n bulk Si

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Threshold Voltage † Every MOS transistor has a characterizing

parameter called the threshold voltage VT

† The specific value of VT is established during the manufacturing process † Threshold voltage of an NMOS and a PMOS

NMOS PMOS V V Drain A Source A

VDD + VDD VDD VGSp Gate V =1 VDD-|VTp| V =1 V Mn A V - Mp A A + Mn On A Gate Mp Off VGSn -

Source VTn VA=0 VA=0 0 Mn Off Drain 0 Mp On

Gate-source voltage Logic translation Gate-source voltage Logic translation

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6 MOS Transistor is Like a Tap…

Source: Prof. Banerjee, ECE, UCSB

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MOS Switches † NMOS symbol and characteristics

Vth 5v 5v 5v-V 00v 00v th

† PMOS symbol and characteristics 0v Vth 5v 5v 0v Vth

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7 CMOS Switch † A complementary CMOS switch „ Transmission gate

-s -s

Symbols a C b a b a b

s s s

0v 55v 55v Characteristics 0v 0v 5v

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CMOS Logic-Inverter † The NOT or INVERT function is often considered the simplest Boolean operation „ F(x)=NOT(x)=x’ Vdd

Vin Vout Vin Vout

Vdd Vdd Vdd

Indeterminate 0110 Vdd/2 logic level

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8 Combinational Logic † Serial structure

S1=0 S1=0 S1=1 S1=1 a S2=0 S2=1 S2=0 S2=1 S1 01 S1 0 a!=b a!=b S2 S2 1 a!=b a=b

b

S1=0 S1=0 S1=1 S1=1 a S2=0 S2=1 S2=0 S2=1 S1 0 1 S1 0 a=b a!=b S2 1 a!=b a!=b S2

b

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Combinational Logic † Parallel structure

S1=0 S1=0 S1=1 S1=1 aS1S2=0 S2=1 S2=0 S2=1 01 0 a!=b a=b S1 S2 S2 1 a=b a=b

b S1=0 S1=0 S1=1 S1=1 S1 a S2=0 S2=1 S2=0 S2=1 01 0 a=b a=b S1 S2 S2 1 a=b a!=b

b

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9 NAND Gate

Output A A 0 1

0 1 1 B B 1 10

A Output B

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NOR Gate

A

B A 0 1 Output 0 1 0 B 1 00

A Output B

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10 Compound Gate † F = ((AB) + (CD))

A B

A C D B F F C D A C

B D

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Structured Logic Design † CMOS logic gates are intrinsically inverting „ The output always produces a NOT operation acting on the input variables † For example, the inverter shown below illustrates this property

1 VDD

a=1 f0f=0

0

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11 Structured Logic Design † The inverting nature of CMOS logic circuits allows us to construct logic circuits for AOI and OAI expressions using a structured approach † AOI logic function „ Implements the operations in the order AND then OR then NOT „ E.g., g (a, b, c, d ) = a.b + c.d † OAI logic function „ Implements the operations in the order OR then AND then NOT „ E.g., g (a, b, c, d ) = (a + b) ⋅ (c + d )

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Structured Logic Design † Behaviors of nMOS and pMOS groups „ Parallel-connected nMOS † OR-NOT operations „ Parallel-connected pMOS † AND-NOT operations „ Series-connected nMOS † AND-NOT operations „ Series-connected pMOS † OR-NOT operations † Consequently, wired groups of nMOS and pMOS are logical duals of another

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12 Dual Property † If an NMOS group yields a function of the form g = a ⋅ (b + c )

then an identically wired PMOS array gives the dual function G = a + (b ⋅ c)

where the AND and OR operations have been interchanged † This is an interesting property of NMOS-PMOS logic that can be exploited in some CMOS designs

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An Example of Structured Design † X = a + b ⋅ (c + d )

VDD c b d

a Group 1 Group 2 Group 3 X b a c d

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13 An Example of XOR Gate † Boolean equation of the two input XOR gate „ a ⊕ b = a ⋅ b + a ⋅ b, this is not in AOI form „ But, a ⊕ b = a ⋅ b + a ⋅ b , this is in AOI form „ Therefore, a ⊕ b = (a ⊕ b) = a ⋅ b + a ⋅ b

VDD VDD a b a b • • • • b a b a • • a ⊕ b • • a ⊕ b a a a a

b b bb

XOR Gate XNOR Gate

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Multiplexer

A 11 B 10 Y A C 01 1 Y D 00 B 0

S S1 S0 -S A

A B Y S Y B C

-S D

S1 -S1 S0 -S0

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14 Static CMOS Summary † In static circuits at every point in time (except when switching), the output is connected to either Vdd or Gnd through a low resistance path „ Fan-in of n (or n it)inputs) requires 2n (n N-type and n P- type) devices † Non-ratioed logic: gates operate independent of PMOS or NMOS sizes † No path ever exists between Vdd and Gnd: low static power † Fully-restored logic (NMOS passes “0” only and PMOS passes “1” only † Gates must be inverting

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Circuit and System Representations † Behavioral representation „ Functional, high level „ For documentation, simulation, verification † Structural representation „ System level – CPU, RAM, I/O „ Functional level – ALU, Multiplier, Adder „ Gate level – AND, OR, XOR „ Circuit level – Transistors, R, L, C „ For design & simulation † Physical representation „ For fabrication

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15 Behavior Representation † A one-bit full adder (Verilog)

module fadder(sum,cout,a,b,ci); output sum, cout; input a, b, ci; a b reg sum, cout;

ci fadder cout always @(a or b or ci) begin sum = a^b^ci; sum cout = (a&b)|(b&ci)|(ci&a); end endmodule

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Structure Representation † A four-bit full adder (Verilog) module adder4(s,c4,a,b,ci); a b output[3:0] sum; output c4; a[0] b[0] a[1] b[1] a[2] b[2] a[3] b[3] input[3:0] a, b; co[0] co[1] co[2] input ci; ci a0 a1 a2 a3 reg[3:0] s; s[0] s[1] s[2] s3] reg c4; wire[2:0] co; fadder a0(s[0],co[0],a[0],b[0],ci); s adder4 fadder a1(s[1], co[1], a[1], b[1], co[0]); fadder a2(s[2],co[2],a[2],b[2],co[1]); fadder a3(s[3],c4,a[3],b[3],co[2]); endmodule

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16 Physical Representation † Layout of a 4-bit NAND gate

Vdd Vdd

in1 in2 in3 in4

Out in1

Out in2

in3

in4

Gnd

in1 in2 in3 in4

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Design Flow for a VLSI Chip

Specification

Function

Behavioral Design

Function

Structural Design Function Timing Power Physical Design

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17 Chapter 2 MOS Transistor Theory

Jin-Fu Li Advance d Re lia ble Sys tems (ARES) La b. Department of Electrical Engineering National Central University Jhongli, Taiwan

Outline

† Introduction † I-V Characteristics of MOS Transistors † Nonideal I-V Effects † Pass Transistor † Summary

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1 MOS Transistor † MOS transistors conduct electrical current by using an applied voltage to move charge from the source side to the drain side of the device † An MOS transistor is a mmjajorit y-carrier device † In an n-type MOS transistor, the majority carriers are electrons † In a p-type MOS transistor, the majority carriers are holes † Threshold voltage „ It is defined as the voltage at which an MOS device begins to conduct (“turn on”) † MOS transistor symbols

NMOS PMOS

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MOS Transistor

† So far, we have treated transistors as ideal switches † An ON transistor passes a finite amount of current „ Depends on terminal voltages „ DiDerive current-voltage (I-V) relati on ships † Transistor gate, source, drain all have capacitance „ I = C (ΔV/Δt) -> Δt = (C/I) ΔV „ Capacitance and current determine speed † The structure of a MOS transistor is symmetric „ Terminals of source and drain of a MOS can be exchanged

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2 Vg & Channel for P-Type Body

Accumulation mode Polysilicon Gate Silicon Dioxide Insulator Vg<0 P-type Body

Depletion mode Depletion Region 0

Inversion mode Inversion Region

Vg>Vt Depletion Region

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NMOS Transistor in Cutoff Mode

Vgs=0 Vgd g s d n+ n+

p-type body

¾ Cutoff region 9 The source and drain have free electrons 9 The body has free holes but no free electrons 9 The junction between the body and the source or drain are reverse-biased, so almost zero current flows

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3 NMOS Transistor in Linear Mode

Vgs>Vt Vgd=Vgs Vgs>Vt Vgs>Vgd>Vt

g g s d s d Ids n+ n+ n+ n+

p-type body p-type body

Vds=0 0

9 If Vgd=Vgs, then Vds=Vgs-Vgd=0 and there is no electrical field tending to push current from drain to source

9 If Vgs>Vgd>Vt, then 0

potential Vds is applied to the drain , current Ids flows through the channel from drain to source 9 The current increases with both the drain and gate voltage

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NMOS Transistor in Saturation Mode

Vgs>Vt Vgd

p-type body

Vds>Vgs-Vt ¾ Saturation region

9 The Vds becomes sufficiently large that Vgd

9 The current Ids is controlled by the gate voltage and ceases to be influenced by the drain

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4 NMOS Transistor

†In summary, the NMOS transistor has three modes of operations

„ If Vgs

„ If Vgs>Vt and Vds is small, the transistor acts as a linear resistor in which the current flow is

proportional to Vds

„ If Vgs>Vt and Vds is large, the transistor acts as a current source in which the current flow becomes

independent of Vds †The PMOS transistor operates in just the opposite fashion

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I-V Characteristics of MOS

† In linear and saturation regions, the gate attracts carriers to form a channel † The carriers drift from source to drain at a rate proportional to the electric field between these regions † MOS structure looks like parallel plate capacitor while operating in inversion „ Gate–oxide–channel Vg

N+ N+

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5 Channel Charge

Vg

Vs Vd

Cg V n+ c n+

¾ Qchannel=Cg(Vgc-Vt) , where Cg is the capacitance of the

gate to the channel and Vgc-Vt is the amount of voltage attracting charge to the channel beyond the minimal required to invert from p to n

¾ Vc=(Vs+Vd)/2=Vs+Vds/2

¾ Therefore, Vgc=(Vgs+Vgd)/2=Vgs-Vds/2

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Gate Capacitance (Cg) † Transistor dimensions

tOX

W Gate

N+ N+

L

† The gate capacitance is „ WL C g = ε ox t ox

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6 Carrier Velocity

†Charge is carried by e- †Carrier velocity v proportional to lateral E- field between source and drain †v = μE, where μ is called mobility

†E = Vds/L †Time for carrier to cross channel: „ t = L / v

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NMOS Linear I-V †Now we know

„ How much charge Qchannel is in the channel „ How much time t each carrier takes to cross † Q I = channel ds t W ⎛⎞V =−−μCVV⎜⎟ds V ox L ⎝⎠gst2 ds ⎛⎞V = β ⎜⎟VV−−ds V ⎝⎠gs t2 ds

W „ Where βμ = C ox L

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7 NMOS Saturation I-V

†If Vgd

„ When Vds>Vdsat = Vgs–Vt †Now drain voltage no longer increases current † ⎛⎞V I =−−β ⎜⎟VVdsat V ds⎝⎠ gs t2 dsat β 2 =−()VVgs t 2

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Summary of NMOS I-V Characteristics

⎧ ⎪ 0 VV< cutoff ⎪ gs t ⎪ V IVVVVV=−−β ⎛⎞ds t VV ds dsat saturation ⎩⎪ 2

2.5 V = 5 Vds=Vgs-Vt gs 2 Linear Saturation 1.5 V = 4

A) gs m ( ds ds I 1 Vgs = 3 0.5 Vgs = 2 V = 1 0 gs 0 1 2 3 4 5

Vds

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8 Example † Assume that the parameters of a technology are as follows 2.5 V = 5 „ t = 100 Å gs ox 2 „ μ = 350 cm2/V*s 1.5 V = 4 „ Vt = 0.7 V gs (mA) ds ds I 1 † Plot Ids vs. Vds Vgs = 3 „ Vgs = 0, 1, 2, 3, 4, 5 0.5 Vgs = 2 „ Use W/L = 4/2 λ V = 1 0 gs 0 1 2 3 4 5

Vds

−14 WWW⎛⎞3.9•⋅ 8.85 10 ⎛⎞ 2 βμ==CAVox ()350⎜⎟−8 ⎜⎟ = 120 μ / LLL⎝⎠100⋅ 10 ⎝⎠

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Nonideal I-V Effects † Nonideal I-V effects „ Velocity saturation, mobility degradation, channel length modulation, subthreshold conduction, body effect, etc. † The saturation current increases less than quadratically

wihith increasi ng Vgs. This is caused by two eff ects: „ Velocity saturation „ Mobility degradation † Velocity saturation

„ At high lateral field strengths (Vds/L), carrier velocity ceases to increase linearly with field strength

„ RltResult in lower Ids than expecte d at hihhigh Vds † Mobility degradation

„ At high vertical field strengths (Vgs/tox), the carriers scatter more often

„ Also lead to less current than expected at high Vgs

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9 Channel Length Modulation

† Ideally, Ids is independent of Vds for a transistor in saturation, making the transistor a perfect current source 1 W 2 „ I ds = μ C ox (V gs − V t ) 2 L † Actually, the width Ld of the depletion region between the channel and drain is increased with Vdb. To avoid introducing the body voltage into our calculations, assume the source voltage is close to the body voltage

so Vdb~Vds

„ Thus the effective channel length is shorten to Leff=L-Ld „ Therefore, the Ids can be expressed as 1 W 1 W 1 I = μ C (V − V ) 2 = μ C (V − V ) 2 ds 2 L ox gs t 2 L ox gs t L eff 1 − d L L „ Assume that d << 1 , then 11WWL L I =−+=−+μμλCV()(1) V22d CV ()(1) V V ds22LLL ox gs t ox gs t ds Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

Channel Length Modulation † The parameter λ is an empirical channel length modulation factor † As channel length gets shorter, the effect of the channel length modulation becomes relatively more important „ Hence λ is inversely dependent on channel length † This channel length modulation model is a gross oversimplification of nonlinear behavior and is more useful for conceptual understanding than for accurate device modeling † Channel length modulation is very important to analog designers because it reduces the gain of amplifiers. It is generally unimportant for qualitatively understanding the behavior of digital circuits

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10 Body Effect

† Body effect

„ Vt is a function of voltage between source and substrate

090.9

0.85

0.8

0.75

0.7

(V) 0.65 T V 0.6

0.55

0.5

0.45 Degree 0.4 -2.5 -2 -1.5 -1 -0.5 0 V (V) Low High BS

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Mobility Variation † Mobility μ „ It describes the ease with which carriers drift in the substrate material „ It is defi ned by †μ =(average carrier drift velocity, v)/(electrical field, E) † Mobility varies according to the type of charge carrier „ Electrons have a higher mobility than holes † Thus NMOS has higher current-producing capability than the corresponding PMOS † Mobility decreases with increasing doping- concentration and increasing temperature

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11 Drain Punchthrough & Hot Electrons

† Drain punchthrough „ When the drain voltage is high enough, the depletion region around the drain may extend to source. Thus, causi ng current to flow irrespecti ve of the gate voltage † Hot electrons „ When the source-drain electric field is too large, the electron speed will be high enough to break the electron-hole pp,air. Moreover, the electrons will penetrate the gate oxide, causing a gate current

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Subthreshold Conduction

† Subthreshold region „ The cutoff region is also referred to as the subthreshold

region, where Ids increases exponentially with Vds and Vgs

„ Observe in the following figure that at Vgs

Ids V =1.8 1 mA Saturation ds Subthreshold region 100 uA region 10 uA 1 uA 100 nA 10 nA Subthreshold 1 nA slope 100 pA Vt 10 pA 00.3 0.6 0.9 1.2 1.5 1.8

Vgs

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12 Junction Leakage † The p-n junctions between diffusion and the substrate or well form diodes † The p-type and n-type substrates are tied to GND or

Vdd to ensure these diodes remain reverse-biased † However, reverse-biased diodes still conduct a small

amount of currentV D IL v T „ I L = I S (e − 1) , VD: diode voltage; vT: thermal voltage (about 26mv at room temperature) † In modern transistors with low threshold voltages, subthreshold conduction far exceeds junction leakage

N+ N+

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Temperature Dependence † The magnitude of the threshold voltage decreases nearly linearly with temperature † Carrier mobility decreases with temperature † Junction leakage increases with temperature because

Is is strongly temperature dependent

† The following figure shows how the current Idsat decreases with temperature

250 240

Idsat (uA) 230 220

210

020 40 60 80 100 120 Temperature (C)

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13 Geometry Dependence † The layout designer draws transistors with width and

length Wdraw and Ldraw. The actual gate dimensions may differ by some factors XW and XL „ E.g., the manufacturer may create masks with narrower polysilicon or may overetch the polysilicon to provide shorter

channels (negative XL) † Moreover, the source and drain tend to diffuse laterally

under the gate by LD, producing a shorter effective channel length that the carriers must traverse between

source and drain. Similarly, diffusion of the bulk by WD decreases the effective channel width † Therefore, the actually effective channel length and width can be expressed as

„ Leff=Ldraw+XL-2LD

„ Weff=Wdraw+XW-2WD

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MOS Small Signal Model

(Vsb=0) Cgd Gate Drain

g Cgs+Cgb gmVgs ds Cdb

Source

Linear region Saturation region

W 1 2 1 W 2 I ds = μ C ox [(V gs − V t )V ds − V ds ] I = μ C (V − V ) L 2 ds 2 L ox gs t

dI ds W g ds = = μ C ox [(V gs − Vt ) − V ds ] g ds = 0 dV ds L dI W W g = ds | (V = const .) = μ C V g = μ C (V − V ) m ds ox ds m L ox gs t dV gs L

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14 Pass Transistor † NMOS pass transistor

„ Cload is initially discharged, i.e., Vout=Vss

„ If Vin=Vdd and VS=Vdd, the Vout=Vdd-Vtn

„ If Vin=Vss and VS=Vdd, the Vout=Vss

Vout Vin

Cload S † PMOS pass transistor

„ If Vin=Vdd and V-S=Vss, the Vout=Vdd

„ If Vin=Vss and V-S=Vss, the Vout=Vtp

Vout Vin

Cload -S

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Pass Transistor Circuits

V V V V DD DD DD DD V V DD DD V = V -V V -V s DD tn V -V DD tn DD tn VDD-Vtn

V DD V -V Vs = |Vtp| DD tn V DD VDD-2Vtn VSS

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15 Transmission Gate † By combining behavior of the NMOS and PMOS, we can construct a transmission gate „ The transmission gate can transmit both logic one and logic zero without degradation -S

Vout Vin

Cload S † The transmission gate is a fundamental and ubiquitous comppgonent in MOS logic „ A multiplexer element „ A logic structure, „ A latch element, etc.

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Voltage-Controlled Resistor † Consider the case where the control input changes

rapidly, the Vin is Vdd, and the capacitor on the transmission gate output is discharged (Vss) „ The transmiss ion gate acts as a resistor

mA

Id -S Idn+Idp V Vout dd VDD Vss

Cload Idp S

Idn

12345

Vout

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16 Summary † Threshold drops „ Pass transistors suffer a threshold drop when passing the

wrong value: NMOS transistors only pull up to VDD-Vtn, while PMOS transistors only pull down to |Vtp| „ The magnitude of the threshold drop is increased by the body effect „ Fully complementary transmission gates should be used where both 0’s and 1’s must be passed well

† VDD „ Velocity saturation and mobility degradation result in less current than expected at high voltage

„ This means that there is no point in trying to use a high VDD to achieve high fast transistors, so VDD has been decreasing with process generation to reduce power consumption „ Moreover, the very short channels and thin gate oxide would

be damaged by high VDD

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Summary † Leakage current „ Real gates draw some leakage current „ The most important source at this time is subthreshold leakage between source and drain of a transistor that should be cut off „ The subthreshold current of a OFF transistor decreases by an

order of magnitude for every 60-100mV that Vgs is below Vt. Threshold voltages have been decreasing, so subthreshold leakage has been increasing dramatically

„ Some processes offer multiple choices of Vt; low-Vt devices are used for high performance, while high-Vt devices are used for low leakage elsewhere „ Leakage current causes CMOS gates to consume power when idle. It also limits the amount of time that data is retained in dynamic logic, latches, and memory cells „ In modern processes, dynamic logic and latches require some sort of feedback to prevent data loss from leakage „ Leakage increases at high temperature

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17 Chapter 3 Fabrication of CMOS Integrated Circuits

Jin-Fu Li Department of ElilElectrical EEiingineering National Central University Jungli, Taiwan

Outline † Background † The CMOS Process Flow † Design Rules † Latchup † Antenna Rules & Layer Density Rules † CMOS Process Enhancements † Summary † 3D Integration Technology Using TSV

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1 Introduction † An integrated circuit is created by stacking layers of various materials in a pre-specified sequence † Both the electrical properties of the material and the geometrical patterns of the layer are important in establishing the characteristics of devices and networks † Most layers are created first, and then patterne d using lithographi c sequence † Doped silicon layers are the exception to this rule

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Material Growth and Deposition

† Silicon Dioxide (SiO2) „ It is an excellent electrical insulator „ It can be grown on a silicon wafer or deposited on top of the waf er „ Thermal oxide

† Si+O2ÆSiO2 (dry oxidation), using heat as a catalyst „ Growth rate is lower

† Si+2H2OÆSiO2+2H2 (wet oxidation) „ Growth rate is faster † The surface of the silicon is recessed from its original location „ CVD oxide

† SiH4(gas)+2O2(gas)ÆSiO2(solid)+2H2O(gas) † Chemical vapor deposition (CVD)

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2 Material Growth and Deposition

† Silicon Nitride (Si3N4) „ A.k.a. nitride

„ 3SiH4(gas)+4NH3(gas)ÆSi3N4(solid)+12H2(gas) „ Nitrides act as strong barriers to most atoms, this makes them ideal for use as an overglass layer † Polycrystal Silicon „ Called polysilicon or just poly for short „ It is used as the gate material in MOSFETs

„ SiH4ÆSi+ 2H2 „ It adheres well to silicon dioxide

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Material Growth and Deposition † Metals „ Aluminum (Al) is the most common metal used for interconnect wiring in ICs † It is pro ne to electromi grati on † J=I/A; A=wt is the cross-section area † Layout engineers cannot alter the thickness t of the layer † Electromigration is thus controlled by specifying the minimum width w to keep J below a max. value „ Copper ( Cu) has recently been introduced as a replacement to aluminum † Its resistivity is about one-half the value of Al † Standard patterning techniques cannot be used on copper layers; specialized techniques had to be developed

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3 Material Growth and Deposition † Doped Silicon Layers „ Silicon wafer is the starting point of the CMOS fabrication process „ A doppyped silicon layer is a patterned n- or p-type section of the wafer surface „ This is accomplished by a technique called ion implantation † Basic section of an ion implanter

Ion source Magnetic Mass Accelerator Separator

Ion beam

wafer

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Material Growth and Deposition † The process of deposition causes that the top surface has hillocks „ If we continue to add layers (e.g., metal layers), the surface will ggggyet increasing rough and may lead to breaks in fine line features and other problems „ Surface planarization is required † Chemical-Mechanical Polishing (CMP) „ It uses a combination of chemical etching and mechanical sanding to produce planar surfaces on silicon wafers † Surface planarization

poly

substrate substrate

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4 Lithography † One of the most critical problems in CMOS fabrication is the technique used to create a pattern „ Photolithography † The photolithographic process starts with the desired pattern definition for the layer † A mask is a piece of glass that has the pattern defined using a metal such as chihromium

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Transfer a Mask to Silicon Surface

† The process for transferring the mask pattern to the surface of a silicon region „ Coat photoresist „ Exposure step „ Etching † Coat photoresist „ Liquid photoresist is sprayed onto a spinning wafer † Exposure „ Photoresist is sensitive to light, such as ultraviolet (UV)

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5 Transfer a Mask to Silicon Surface

„ The figure shown as below depicts the main idea UV

Hardened mask resist layer

photoresist wafer wafer

„ The hardened resist layer is used to protect underlying regions from the etching process † EhiEtching „ The chemicals are chosen to attack and remove the material layer not shielded by the hardened photoresist

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Dopping

„ The figure shows the etching process

Hardened Patterned resist layer oxide layer

Oxide layer Substrate Substrate

† Creation of doped silicon Arsenic ions

Lateral dopping

N+ N+ Substrate Substrate

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6 Dopping † The conductive characteristics of intrinsic silicon can be changed by introducing impurity atoms into the silicon crystal lattice † Impurity elements that use (provide) electrons are called as acceptor (donor) † Silicon that contains a majority of donors (acceptor) is known as n-type (p-type) † When n-type and p-type materials are merged together, the region where the silicon changes from n-type to p-type is called junction

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MOS Transistor † Basic structure of a NMOS transistor

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7 Fabrication Steps for an NMOS

+ + Patterning Implant or n n Diffusion SiO2 Layer Implant of p-substrate p-substrate Impurities Thin Oxide

+ + SiO2 by Gate Contact n n deposition Oxidation Cuts p-substrate p-substrate Polysilicon Al contacts

Patterning n+ n+ Patterning Polysilicon Al layer p-substrate p-substrate

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Basic CMOS Technology

† Four dominant CMOS technologies „ N-well process „ P-well process „ Twin-tub process „ Silicon on insulator (SOI) † N-well (P-well) process „ Starts with a lightly doped p-type (n-type) substrate (wafer), create the n-type (p-type) well for the p-chlhannel (n-chl)hannel) ddievices, and bbilduild the n-channel (p-channel) transistor in the native p-substrate (n-substrate)

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8 N-Well CMOS Process

Cross Section of Physical Structure Mask (top view)

n-well mask

n-well p-substrate n-well

active mask

nitride oxide

n-well p-substrate Active

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N-Well CMOS Process

Implant (Boron) Resist channel stop mask p-channel stop

n-well p-substrate Channel stop

n-well p-substrate

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9 N-Well CMOS Process

polysilicon mask

n-well p-substrate polysilicon

n+ mask

n+ n+ n-well p-substrate n+ mask

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N-Well CMOS Process

Light implant heavier implant

oxide poly poly - - - - n n n n n+ n+ Shadow drain implant LDD (lightly doped drain) structure

p+ mask

n+ n+ p+ p+ n-well p-substrate p+ mask

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10 N-Well CMOS Process

contact mask

n+ n+ p+ p+ n-well p-substrate contact mask

metal mask

n+ n+ p+ p+ n-well p-substrate metal mask

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CMOS Inverter in N-Well Process

in

out Vdd Vss

in

out

Vdd Vss

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11 CMOS Inverter in N-Well Process

+ + p p n+ n+

n-well

p-substrate

field oxide contact cut polysilicon metal gate oxide

p+ p+ n+ n+

n-well p-substrate

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A Sample of Multi-Layer Metal

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12 Design Rules

† Design rules (layout rules) „ Provide a necessary communication link between circuit designers and process engineers during manuftifacturing phase „ The goal of design rules is to achieve the optimum yield of a circuit with the smallest area cost † Design rules specify to the designer certain geometric constraints on the layout artwork so that the patterns on the processed wafer will preserve the topology and geometry of the designs

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Design Rules

† The design rules primarily address two issues „ The geometrical reproduction of features that can be reproduced by the mask-making and lithographi cal process „ The interactions between different layers † Lambda-based rules „ Based on a single parameter, lambda, which characterizes the linear feature – the resolution of the complete wafer implementation process

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13 Examples of Design Rules

Same Potential Different Potential 9 0 WllWell or 6 10 3 2 Active Polysilicon

3 2 3 Metal1 Contact or Via 2 Hole 3 2

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Transistor Layout r o 1 ansist Tr

3 2

5

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14 Design Rules for Vias & Contacts

2 4 Via 1 1 5 Metal to Metal to 1 Poly Contact Active Contact 32

2 2

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Design Rule Checker

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15 Latchup

† Latchup is defined as the generation of a low- impedance path in CMOS chips between power supply rail and the ground rail due to interaction of parasitic pnp and npn bipolar transistors † These BJTs form a silicon-controlled rectifier (SCR) with positive feedback and virtually short circuit the power rail to ground, thus causing excess ive curren t flows and even permanent device damage

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Latchup of a CMOS Inverter

Vdd

p+ n+ n+ p+ p+ n+ PNP NPN N-well Rwell

R substrate P-substrate

2.0mA Rwell

Iramp

Trigger point Vne Rsubstrate Iramp

-1 01234Holding Voltage Vne

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16 Latchup Triggering † Latchup can be triggered by transient current or voltages that may occur internally to a chip during power-up or externally due to voltages or currents bbdeyond normal operating ranges † Two possible triggering mechanisms „ Lateral triggering & vertical triggering † Ex: the static trigger point of lateral triggering is

Vpnp−on Intrigger ≈ αnpn Rwell

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Latchup Prevention

† Reducing the value of resistors and reducing the gain of the parasitic transistors are the basis for eliminating latchup † Latchup can be prevented in two basic methods „ Latchup resistant CMOS process „ Layout techniques † I/O latchuppp prevention „ Reducing the gain of parasitic transistors is achieved through the use of guard rings

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17 Guard Rings † Guard rings are that p+ diffusions in the p- substrate and n+ diffusions in the n-well to collect injected minority carriers

Vdd

emitter p+ p-plus n-plus

n+ n-plus base N-well collector (substrate)

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I/O Latchup Prevention † A p+ guard ring is shown below for an n+ source/drain

Vss

n+ p+ p+ + + + hole current P+ collects hole current thereby N-well shielding n+ source/drain

† A n+ guard ring is shown below for a p+ source/drain

V n+ collects electron current dd thereby b shie lding p+ source/drain n+ n+ p+ electron current - - - N-well

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18 Antenna Rules

† When a metal wire contacted to a transistor gate is plasma-etched, it can charge up to a voltage sufficient to break down thin gate oxide † The metal can be contacted to diffusion to provide a path for the charge to bleed away † Antenna rules specify the maximum area of metal that can be connected to a gate without a source or drain to act as a discharge element † The design rule normally defines the maximum ratio of metltal area to gate area such thtthat charge on the metal will not damage the gate „ The ratios can vary from 100:1 to 5000:1 depending on the thickness of the gate oxide (and hence breakdown voltage) of the transistor in question

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Antenna Rule Violation and Fix Wire attracts charge during plasma processing and builds up voltage V=Q/C

L2 Length L2 exceeds allowed limit Any source/drain can act as a discharge element

Gate may be connected to source/drain at any metal layer in an auto routing situation

metal 4 metal 3 L1 metal 2 metal 1

Added link solves problem-L1 satisfies design rule

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19 Antenna Diode Addition † An alternative method is to attach source/drain diodes to problem nets as shown below „ These diodes can be simple junctions of n-diffusion to p- substrate rather than transistor source/drain regions

L2

Antenna diode may be added

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Layer Density Rules † For advanced processes, a minimum and maximum density of a particular layer within a specific area should be specified „ Layer density rules † Layer density rules are required as a result of the CMP process and the desire to achieve uniform etch rates † For example, a metal layer might have to have 30% minimum and 70% maximum fill within a 1mm by 1mm area † For digital circuits, layer dedensitynsity levels are normally reached with normal routing † Analog & RF circuits are almost sparse „ Gate and metal layers may have to be added manually or by a fill program after design has been completed

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20 CMOS Process Enhancements † Multiple threshold voltages

„ Low-Vt → more on current, but greater subthreshold leakage

„ High-Vt → less current, but smaller subthreshold leakage

„ User low-Vt devices on critical ppgaths and higher-Vt devices elsewhere to limit leakage power „ Multiple masks and implantation steps are used to set the various thresholds † Silicon on insulator (SOI) process „ The transistors are fabricated on an insulator „ Two major insulators are used, SiOs and sapphire „ Two major addtvantages: eliitilimination of the capac itance btbetween the source/drain regions and body, leading to higher-speed devices; lower subthreshold leakage

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CMOS Process Enhancements

† High-k gate dielectrics „ MOS needs high gate capacitance to attract charge to

channel→very thin SiO2 gate dieletrics † Scaling trends indicate the gate leakage will be unacceptably large in such thin gates „ Gates could use thicker dielectrics and hence leak less if a material with a higher dielectric constant were available

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21 Summary

† Some of more common CMOS technologies have been covered † A representative set of n-well process has been introduced † Concepts of design rules have been presented † The important condition known as latchup has been introduced with necessary design rules to avoid this condition in CMOS chips † Antenna rules & layer density rules should be considered in modern manufacturing process

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3D Integration Technology

† 3D integration approaches „ 3D packaging technology „ 3D integration using through silicon via (TSV) † 3D packagi ng technol ogy

Source: Proceedings of IEEE, Jan. 2009

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22 3D Integration Technology

† 3D integration using TSV „ Via-last technology „ Via-first technology † Via-First (1) Before CMOS

(2) After CMOS & BEOL

Source: Yole, 2007. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45

3D Integration Technology

† Via-Last

(1) After BEOL & before bonding

(2) After bonding

Source: Yole, 2007.

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23 3D Integration Technology

Source: ASP-DAC 2009.

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Fabrication Flow

Source: ASP-DAC 2009.

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24 Design Example

Source: ASP-DAC 2009.

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Benefits of 3D Integration

† Benefits of 3D integration over 2D integration „ High functionality „ HhHigh performance „ Small form factor „ Low power

Source: Proceedings of IEEE, Jan. 2009 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50

25 Road Map of 3D Integration with TSVs

Source: Proceedings of IEEE, Jan. 2009 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51

26 Chapter 4 Electrical Characteristics of CMOS

Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Outline

† Resistance & Capacitance Estimation † DC Response † Logic Level and Noise Margins † Transient Response † Delay Estimation † Transistor Sizing † Power Analysis † Scaling Theory

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1 Resistance Estimation † Resistance „ R = (ρ / t)(L /W ) , where ( ρ , t , L , W ) is (resistivity, thickness, conductor length, conductor width) † Sheet resistance

„ Rs =Ω/ □

„ Thus R = Rs (L /W )

W W 1 rectangular block t

R = Rs (L /W ) W L t

L L 4 rectangular block

R = Rs (2L / 2W ) = Rs (L /W )

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Drain-Source MOS Resistance † A simplified linear model of MOS is useful at the logic level design

„ RC model of an NMOS G

G Rn S D

S D Cs CD

„ The drain-source resistance at any point on the current curve as shown below

Ids

c b a

Vds

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2 Drain-Source Resistance

† The resistance at point a „ The current is approximated by

† Ids ≈ βn (Vgs −Vt )Vds „ Thus the resistance is

† Rn ≈ 1/ βn (Vgs −Vt ) † The resistance at point b „ The full non-saturated current must be used so that 1 2 † Ids = βn[2(Vgs −Vt )Vds −Vds ] 2 „ Thus the resistance is † Rn = 2 / βn[2(Vgs −Vt ) −Vds ]

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Drain-Source Resistance † The resistance at point c „ The current is 1 † I ≈ β (V − V ) 2 ds 2 n gs t „ Thus the resistance is 2 † Rn = 2Vds / βn (Vgs −Vt )

„ Rn is a function of both Vgs and Vds † These equations show that it is not possible to

define a constant value for Rn β † However, Rn is inversely proportion to n in all cases, i.e.,

„ Rn ∝1/ βn β = k(W / L) „ n , W/L is called aspect ratio

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3 Capacitance Estimation † The switching speed of MOS circuits are heavily affected by the parasitic capacitances associated with the MOS device and itinterconnec tion capacitances † The total load capacitance on the output of a CMOS gate is the sum of „ Gate capacitance „ Diffusion capacitance „ RtiRouting capacitance † Understanding the source of parasitic loads and their variations is essential in the design process

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MOS-Capacitor Characteristics

† The capacitance of an MOS is varied with the applied voltages † Cappyacitance can be calculated by ε ε „ C = 0 x A d „ ε x is dielectric constant

„ ε 0 is permittivity of free space † Depend on the gate voltage, the state of the MOS surface may be in „ Accumulation „ Depletion „ Inversion

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4 MOS Capacitor Characteristics

† When Vg<0, an accumulation layer is formed „ The negative charge on the gate attracts holes toward the silicon surface „ The MOS s truc ture be haves like a parall el -pltlate capacitor

gate gate Vg<0

C tox ε ε o 0 SiO 2 C 0 = A tox

P-substrate

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MOS Capacitor Characteristics † When a small positive voltage is applied to the gate, a depletion layer is formed „ The positive gate voltage repels holes, leaving a negativel y charged regi on depl et ed of carr iers

gate gate Vg~0

ε 0ε Si C dep = A t d Co ox Depletion layer d C dep C C C = 0 dep P-substrate gb C0 + Cdep

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5 MOS Capacitor Characteristics † When the gate voltage is further increased, an n-type channel (inversion layer) is created „ If the MOS is operated at high frequency, the surface c harge is not able to ttkrack fftast movi ng gate voltages gate gate Vg>0 Low frequency

C gb = C 0 t Co ox Channel Depletion layer Cdep Hig h frequency C C P-substrate 0 dep Cgb = = Cmin C0 + Cdep

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MOS Capacitor Characteristics † Consequently, the dynamic gate capacitance as a function of gate voltage, as shown below

Accumulation Depletion Inversion 1.0 Low freq.

C/Co

High freq.

Vgs 0 Vt † The minimum capacitance depends on the depth of the depletion region, which depends on the substrate doping density

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6 MOS Device Capacitances † The parasitic capacitances of an MOS transistor are shown as below

„ Cgs, Cgd: gate-to-channel capacitances, which are lumped a t the source and the drai n regi ons of the channel, respectively

„ Csb, Cdb: source and drain-diffusion capacitances to bulk „ Cgb: gate-to-bulk capacitance Cgd Cdb gate

Cgs Cgb Cgd source channel drain depletion layer Cgs Csb Cgb Csb Cdb substrate

Cg=Cgb+Cgs+Cgd

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Variation of Gate Capacitance † The behavior of the gate capacitance in the three regions of operation is summarized as below

„ Off region (Vgs

„ Non-saturated region (Vgs-Vt>Vds): Cgs and Cgd become significant. These capacitances are dependent on gate voltage. Their value can be estimated as ε ε 1 0 SiO2 Cgdd = Cgs = A 2 tox

„ Saturated region (Vgs-Vt

7 Approximation of the Cg

† The Cg can be further approximated with ε ε o SiO2 „ C g = C ox A, where Cox = tox † The gate capacitance is determined by the gate area, since the thickness of oxide is associated with process of fabrication † For example, assume that the thickness of silicon oxide of the given process is 150 × 10 − 8 μ m . Calculate the capacitance of the MOS shown 2λ blbelow λ = 0.5μm

4λ 5λ 3.9 × 8.854 × 10 −14 C = × 2 = 25 .5 × 2 × 10 − 4 pF ≈ 0.005 pF g 150 × 10 −8 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

Diffusion Capacitance

† Diffusion capacitance Cd is proportional to the diffusion-to-substrate junction area

Substrate b Source Drain a Diffusion Diffusion Area Area b a

Cjp

Xc (a finite depth)

Cja

Cd =Cja ×(ab)+Cjp ×(2a+2b)

Cja=junction capacitance per micron square

Cjp=periphery capacitance per micron

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8 Junction Capacitance † Semiconductor physics reveals that a PN junction automatically exhibits capacitance due to the opposite polarity charges involved. This is called junction or depletion capacitance and is found at every drain or source region of a MOS † The junction capacitance is varies with the junction voltage, it can be estimate as

V j − m C j = C j 0 (1 − ) Vb

„ C j =junction voltage (negative for reverse bias) C „ j0 =zero bias junction capacitance ( V j = 0 ) „ Vb =built-in junction voltage ~ 0.6V Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

Single Wire Capacitance

† Routing capacitance between metal and substrate can be approximated using a parallel-plate model Fringing fields WL

T H

substrate Insulator (()Oxide) † In addition, a conductor can exhibit capacitance to an adjacent conductor on the same layer

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9 Multiple Conductor Capacitances

† Modern CMOS processes have multiple routing layers „ The capacitance interactions between layers can become quite complex † Multilevel-layer capacitance can be modeled as below

Layer 3 C Multi-layer 23 C22 condtductor Layer 2 C21 Layer 1

C2=C21+C23+C22

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A Process Cross Section † Interlayer capacitances of a two-level-metal process

A B C D E F G

m2 m2 m2 m2 m2 C C m1 m2 m1 C m1 C poly C poly C CC Thin-oxide/diffusion

Substrate

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10 Inductor † For bond wire inductance μ 4h d „ L = ln( ) h 2π d

w † For on-chip metal wires „ μ 8h w L = ln( + ) h 2π w 4h † The inductance produces Ldi/dt noise especially for ground bouncing noise. Note that when CMOS circuit are clocked, the current flow changes greatly di V = L dt

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Distributed RC Effects † The propagation delay of a signal along a wire mainly depends on the distributed resistance and capacitance of the wire † A long wire can be represented in terms of several RC sessions, as shown below Ij-1 Ij R R R R R Vj-1 Vj Vj+1

C C C C C

„ The response at node Vj with respect to time is then given by dV (V −V ) (V −V ) † CdV = Idt ⇒ C j = (I − I ) = j−1 j − j j+1 dt j−1 j R R

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11 Distributed RC Effects † As the number of sections in the network becomes large (and the sections become small), the above expression reduces to the differenti a l form 2 dV d V 2 „ rc = ⇒ t x = kx dt dx 2 „ r : resistance per unit length „ c : capacitance per unit length † Alternatively, a discrete analysis of the cir cuit show n in the pre vio us page yi elds an approximate signal delay of RCn(n +1) „ tn = 0.7 × , where n=number of sections 2 2 rcl t = 0.7 „ 1 2

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Wire Segmentation with Buffers † To optimize speed of a long wire, one effective method is to segment the wire into several sections and insert buffers within these sections † Consider a poly bus of length 2mm that has been divided into two 1mm sections. −15 2 „ Assume that tx = 4×10 x −15 2 −15 2 „ With buffer t p = 4×10 ×1000 + tbuf + 4×10 ×1000 = 4ns + tbfbuf + 4ns = 8ns + tbfbuf

−15 2 „ Without buffer t p = 4×10 × 2000 =16ns „ By keeping the buffer delay small, significant gain can be obtained with buffer insertion

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12 Crosstalk † A capacitor does not like to change its voltage instantaneously. † A wire has high capacitance to its neighbor. „ When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. „ Called capacitive coupling or crosstalk. † Crosstalk effects „ Noise on nonswitching wires „ Increased de lay on switc hing wires

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Crosstalk Delay † Assume layers above and below on average are quiet „ Second terminal of capacitor can be ignored

„ Model as Cgnd = Ctop + Cbot

† Effective Cadj depends on behavior of neighbors „ Miller effect

B ΔV Ceff(A) MCF

Constant VDD Cgnd + Cadj 1 A B Cadj Switching with A 0 Cgnd 0 Cgnd Cgnd

Switching opposite A 2VDD Cgnd + 2 Cadj 2

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13 Crosstalk Noise † Crosstalk causes noise on nonswitching wires † If victim is floating: „ model as capacitive voltage divider

Cadj Δ=VVvictim Δ aggressor CCgnd− v+ adj

Aggressor

ΔVaggressor Cadj Victim

Cgnd-v ΔVvictim

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Driven Victim † Usually victim is driven by a gate that fights noise „ Noise depends on relative resistances „ Victim driver is in linear region, agg. in saturation

„ If sizes are same, Raggressor = 2-4 x Rvictim

Cadj 1 R Δ=VVvictim Δ aggressor aggressor Aggressor CCkgnd− v++ adj 1 Cgnd-a ΔVaggressor Cadj R victim Victim RCC+ C ΔV τ aggressor aggressor( gnd− a adj ) gnd-v victim k == τ victim RCvictim() gnd− v+ C adj

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14 Simulation Waveforms

† Simulated coupling for Cadj = Cvictim

Aggressor 1.8

1.5

1.2

Victim (undriven): 50% 0.9

0.6 Victim (half size driver): 16%

Victim (equal size driver): 8% 0.3 Victim (double size driver): 4%

0 0 200 400 600 800 1000 1200 1400 1800 2000 t(ps)

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DC Response

† DC Response: Vout vs. Vin for a gate † Ex: Inverter

„ When Vin = 0 ÆVout=VDD VDD „ When Vin = VDD ÆVout=0

„ In between, Vout depends on Idsp transistor size and current Vin Vout

„ By KCL, must settle such that Idsn

Idsn = |Idsp| „ We could solve equations „ But graphical solution gives more insight

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30

15 Transistor Operation † Current depends on region of transistor behavior

† For what Vin and Vout are NMOS and P MOS in „ Cutoff? „ Linear? „ Saturation?

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

NMOS Operation

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn –Vtn Vdsn > Vgsn –Vtn

VDD

Idsp Vgsn = Vin Vin Vout I Vdsn = Vout dsn

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

16 NMOS Operation

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Viin < Vttn Viin > Vttn Viin > Vttn

Vdsn < Vgsn –Vtn Vdsn > Vgsn –Vtn

Vout < Vin -Vtn Vout > Vin -Vtn

VDD

Vgsn = Vin Idsp Vin Vout Vdsn = Vout Idsn

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

PMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp –Vtp Vdsp < Vgsp –Vtp

VDD

Idsp Vgsp = Vin - VDD V < 0 tp Vin Vout V = V -V dsp out DD Idsn

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

17 PMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp

Vdsp > Vgsp –Vtp Vdsp < Vgsp –Vtp

Vout > Vin -Vtp Vout < Vin -Vtp

VDD

V = V - V gsp in DD Vtp < 0 Idsp Vin Vout Vdsp = Vout -VDD Idsn

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

I-V Characteristics

† Make pMOS is wider than nMOS such that βn = βp

Vgsn5

Vgsn4 Idsn

Vgsn3 -Vdsp V -VDD gsn2 Vgsp1 Vgsn1 Vgsp2 0 VDD V Vgsp3 dsn

Vgsp4 -Idsp

Vgsp5

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36

18 Current & Vout, Vin

Vin1 Vin5

Vin2 Vin4 Idsn, |Idsp|

Vin3 Vin3

Vin4 Vin2 Vin5 Vin1

VDD Vout

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37

Load Line Analysis

† For a given Vin:

„ Plot Idsn, Idsp vs. Vout

„ Vout must be where |currents| are equal in

Vin1 Vin5

Vin2 Vin4 V Idsn, |Idsp| DD I V dsp V Vin3 Vin3 in out Idsn Vin4 Vin2 Vin5 Vin1

VDD Vout

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38

19 DC Transfer Curve

† Transcribe points onto Vin vs. Vout plot

Vin1 Vin5

Vin2 Vin4

Vin3 Vin3

Vin4 Vin2 Vin5 Vin1

VDD Vout

VDD AB

Vout C

D E 0 Vtn VDD/2 VDD+Vtp VDD Vin Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39

Operation Regions † Revisit transistor operating regions

Region nMOS pMOS VDD ACutoffLinear AB

B Saturation Linear Vout C C Saturation Saturation D Linear Saturation D E ELinearCutoff 0 Vtn VDD/2 VDD+Vtp VDD Vin

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40

20 Beta Ratio

† If βp / βn ≠ 1, switching point will move from VDD/2 † Called skewed gate † Other gates: collapse into equivalent inverter

VDD

β p = 10 βn

Vout 2 1 0.5 β p = 0.1 βn

0

VDD Vin

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41

Noise Margin † How much noise can a gate input see before it does not recognize the input?

Output Characteristics Input Characteristics VDD Logical High Logical High Output Range VOH Input Range NMH V IH Indeterminate Region VIL NM L Logical Low Logical Low VOL Input Range Output Range GND

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42

21 Transient Analysis

† DC analysis tells us Vout if Vin is constant

† Transient analysis tells us Vout(t) if Vin(t) changes

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43

Switching Characteristics † Switching characteristics for CMOS inverter

Vin(t) Vout(t)

Vds=Vgs-Vt

CL

VDD Ids

Vin(t)

t V tdf tdr DD 90% Vout(t) VDD Vout(t) 50% 10% t tf tr Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44

22 Switching Characteristics

† Rise time (tr) „ The time for a waveform to rise from 10% to 90% of its steady-state value

† Fall time (tf) „ The time for a waveform to fall from 90% to 10% steady-state value

† Delay time (td) „ The time difference between input transition (50%) and the 50% output level. (This is the time taken for a logic transition to pass from input to output

„ High-to-low delay (tdf)

„ Low-to-high delay (tdr)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45

Fall Time of the Inverter † Equivalent circuit for fall-time analysis

PMOS PMOS

Input rising Vout(t) Vout(t)

I NMOS Rcn NMOS dsn CL CL

Saturated Vout>=VDD-Vtn Nonsaturated 0

„ tf1=perio d dur ing w hic h the capacit or volt age, Vout, drops from 0.9VDD to (VDD-Vtn)

„ tf2=period during which the capacitor voltage, Vout, drops from (VDD-Vtn) to 0.1VDD

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46

23 Timing Calculation

† tf1 can be calculated with the current-voltage equation as shown below, while in saturation dV β „ C out + n (V −V )2 = 0 L dt 2 DD tn „ tf2 also can be obtained by the same way „ Finally, the fall time can be estimated with CL t f ≈ k × βnVDD † Similarly, the rise time can be estimated with CL „ tr ≈ k × β pVDD † Thus the propagation delay is

CL 1 1 „ t p ≈ k × ( + ) VDD βn β p

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47

Design Challenges

† βn =β p , rise time=fall time

„ This implies Wp=2-3Wn

† Reduce CL „ Careful layout can help to reduce the diffusion and interconnect capacitance

† Increaseβn and β p „ Increase the transistor sizes also increases the diffusion capacitance as well as the gate capacitance. The latter will increase the fan-out factor of the driving gate and adversely affect its speed

† Increase VDD „ Designers don’t have too much control over this

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48

24 Gate Delays † Consider a 3-input NAND gate as shown below

P3 P2 P1 out

IN-3 N3

IN-2 N2 IN-1 N1 „ When pull-down path is conducting 1 † β neff = (1/ β n1) + (1/ βn2 ) + (1/ β n3 ) β † For β = β = β ⇒ β = n n1 n2 n3 neff 3 „ When the pull-down path is conducting † Only one p-transistor has to turn on to raise the output.

Thus β peff = β p

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49

Gate Delays † Graphical illustration of the effect of series transistors

L

L 3L

L

w w

„ In ge nera l, the fall time tf is mtf (tf/m) for m n- transistors in series (parallel). Similarly the rise

time tr for k p-transistors in series (parallel) is ktr (tr/k)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50

25 Switch-Level RC Model

† RC modeling „ Transistors are regarded as a resistance discharging or charging a capacitance † Simple RC modeling R „ Lumped RCs p

„ tdf = ∑Rpulldown ×∑Cpulldown− path

† Elmore RC modeling C R „ Distributed RCs n

„ td = ∑ RiCi i

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51

Example

† Consider a 4-input NAND as shown below „ Simple RC model

tdf = ∑ Rpulldown ×∑C pulldown− path

=(RN1 +RN2 +RN3 +RN4)×(Cout +Cab +Cbc +Ccd) t = R ×C dr p4 out P P P P 4 3 2 1 out

A N4 „ Elmore RC model Cout Cab

td = ∑ RiCi B N3 i C t =(R ×C )+[(R +R )×C ] bc df N1 cd N1 N2 bc C N2 Ccd +[(RN1 +RN2 +RN3)×Cab] D N1

+[(RN1 + RN 2 + RN 3 + RN 4 )×Cout ]

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 52

26 Cascaded CMOS Inverter

† As discussed above, if we want to have approximately the same rise and fall times for an inverter, for current CMOS process, we must mkmake

„ Wp =2-3Wn „ Increase layout area and dynamic power dissipation † In some cascaded structures it is possible to use minimum or equal-size devices without compromising the switching response † In the following, we illustrate two examples to explain why it is possible

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 53

Cascaded CMOS Inverter

† Example 1:

tinv-pair tinv − pair = t fall + t rise R Icharge 4/1 = R 3C eq + 2 3C eq R R 2 2/1 3C 3C eq eq = 3RC + 3RC Idischarge eq eq

Wp=2Wn = 6 RC eq † Example 2:

tinv-pair

tinv − pair = t fall + trise 2/1 Icharge 2R R = R 2C eq + 2 R 2C eq

2/1 2Ceq 2Ceq Idischarge = 6RC eq

Wp=Wn

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 54

27 Stage Ratio † To drive large capacitances such as long buses, I/O buffers, etc. „ Using a chain of inverters where each successive inverter is made larger than the previous one until the last inverter in the chain can drive the large load in the time required „ The ratio by which each stage is increased in size is called stage ratio † Consider the circuit shown below „ It consists of n-cascaded inverters with stage-

ratio a driving a capacitance CL 1 a a2 a3

CL n(4) stages Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 55

Stage Ratio

† The delay through each stage is atd, where td is the average delay of a minimum-sized inverter driving another minimum-sized inverter

† Hence the del ay through n stages is na td † If the ratio of the load capacitance to the

capacitance of a minimum inverter, CL/Cg, is R, then an=R „ Hence ln(R)=nln(a)

„ Thus the total delay is ln(R)(a/ln(a))td „ The optimal stage ratio may be determined from

k + aopt C drain aopt „ aopt = e where k is C gate

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 56

28 Power Dissipation † Instantaneous power „ The value of power consumed at any given instant „ P(t) = v(t)i(t) † PkPeak power „ The highest power value at any given instant; peak power determines the component’s thermal and electrical limits and system packaging requirements

„ Ppeak = Vi peak † Average power „ The total distribution of power over a time period; average power impacts the battery lifetime and heat dissipation „ 1 t +T V t +T Pave = P (t)dt = i(t)dt T ∫t T ∫t Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 57

Power Analysis for CMOS Circuits † Two components of power consumption in a CMOS circuit „ Static power dissipation † Caused by t he leak age current and oth er static current „ Dynamic power dissipation † Caused by the total output capacitance † Caused by the short-circuit current † The total power consumption of a CMOS circuit is

„ Pt = Ps + Psw + Psc

„ Ps: static power (leakage power); Psw: switching power; Psc: short-circuit power

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 58

29 Static Power

† Static dissipation is major contributed by „ Reverse bias leakage between diffusion regions and the substrate „ Subthreshold conduction

Vin

Gnd VDD PN junction reverse bias Vout leakage current p+ n+ n+ p+ p+ n+ i = i (eqV / KT −1) n-well 0 s n P = I ×V p-substrate s ∑ leakage supply 1 n=number of devices

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 59

Dynamic Power Dissipation † Switching power „ Caused by charging and discharging the output capacitive load † CidConsider an inverter operated at a swiihitching frequency f=1/T 1 T Psw = io (t)vo (t)dt T ∫0 VDD dvo i ip = io = CL p dt V out dvo Vin in = −io = −CL io dt in C L 1 VDD 0 Psw = [ CLvodvo − CLvodvo ] T ∫∫0 VDD C V 2 P = L DD = fC V 2 sw T L DD

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 60

30 Power & Energy † Energy consumption of an inverter (from 0 → V DD ) „ The energy drawn from the power supply is 2 † E = QV = C LVDD „ The energy stored in the load capacitance is V † DD 1 2 E cap = Cvo dv o = C LV DD ∫0 2

„ The output from VDD →0

† The Ecap is consumed by the pull-down NMOS † Low-energy design is more important than low- power design „ Minimize the product of power and delay

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 61

Short-Circuit Power Dissipation

† Even if there were no load capacitance on the output of the inverter and the parasitics are negligible, the gate still dissipate switching energy † If the input changes slowl y, bbhoth the NMOS and PMOS transistors are ON, an excess power is dissipated due to the short-circuit current † We are assuming that the rise time of the input is equal to the fall time † The short-circuit power is estimated as

„ Psc = ImeanVDD

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 62

31 Short-Circuit Power Dissipation

† Imean can be estimated as follows

Vin T VDD

tr t VDD-|Vtp| f

Vin i V sc Vout tn

CL

Imax

Imean

t1 t2 t3

1 t 2 t3 I mean = 2 × [ i ( t )dt + i ( t ) dt ] T ∫∫t1 t 2

4 t 2 I mean = [ i ( t ) dt ] T ∫t1

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 63

Short-Circuit Power Dissipation

† The NMOS transistor is operating in saturation, hence the above equation becomes

t 4 2 β 2 I mean = [ (V in ( t ) − V T ) dt ] T ∫t1 2

V DD V in ( t ) = t t r

V T t 1 = t r V DD t t = r 2 2 β P = (V − 2V ) 3 τ f (t = t = τ ) sc 12 DD T r f

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 64

32 Power Analysis for Complex Gates † The dynamic power for a complex gate cannot

be estimated by the simple expression CLVDDf † Dynamic power dissipation in a complex gate „ Internal cell power

„ Capacitive load power VDD

† Capacitive load power BC 2 „ PL = α C LV DD f A C1 † Internal cell power n out „ A C Pint = ∑ α i C iV iV DD f i =1 B C2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 65

Glitch Power Dissipation

† In a static logic gate, the output or internal nodes can switch before the correct logic value is being stable. This phenomenon results in spurious transitions called glitches

ABC 100 111 A D B D Z C Z

Unit delay Spurious transition

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 66

33 Rules for Avoiding Glitch Power

† Balance delay paths; particularly on highly loaded nodes

† Insert, if possible, buffers to equalize the fast path † Avoid if possible the cascaded design † Redesign the logic when the power due to the glitches is an important component

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 67

Principles for Power Reduction

† Switching power dissipation 2 „ PL = α C LV DD f n „ Pint = ∑ α i C iV iV DD f i =1 † Prime choice: reduce voltage „ Recent years have seen an acceleration in supply voltage reduction „ Design at very low voltage still open question (0.6V…0.9V by 2010) † Reduce switching activity † Reduce physical capacitance

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 68

34 Layout Guidelines for LP Designs † Identify, in your circuit, the high switching nodes † Keep the wires of high activity nodes short † Use low-capacitance layers (e.g., metal2, metal 3, etc.) for high capacitive nodes and busses † Avoid, if possible, the use of dynamic logic design style † For any logic design, reduce the switching activity, by logic reordering and balanced delays through gate tree to avoid glitch problem † In non-critica l paths, use min imum size didevices whenever it is possible without degrading the overall performance requirements † If pass-transistor logic style is used, careful design should be considered

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 69

Sizing Routing Conductors † Why do metal lines have to be sized? „ Electromigration „ Power supply noise and integrity (i.e., satisfactory power and signal voltage leve ls are presen te d to each gate) „ RC delay † Electromigration is affected by „ Current density „ Temperature „ Crystal structure † For example, the limiting value for 1 um-thick

aluminum is J Al = 1 → 2mA / μm

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 70

35 Power & Ground Bounce † An example of ground bounce

Voltage

Vin L Vout V Pad Time DD Current

Time V Vout I in I

VSS Pad

VL

L VL=L(di/dt) Time

Ground bounce

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 71

Approaches for Coping with L(di/dt)

† Multiple power and ground pins „ Restrict the number of I/O drivers connected to a single supply pins (reduce the di/dt per supply pin) † Careful selection of the position of the power and ground pins on the package „ Avoid locating the power and ground pins at the corners of the package (reduce the L) † Increase the rise and fall times „ Reduce the di/dt † Adding decoupling capacitances on the board „ Separate the bonding-wire inductance from the inductance of the board interconnect

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 72

36 Contact Replication † Current tends to concentrate around the perimeter in a contact hole „ This effect, called current crowding, puts a practical upper lim it on the s ize o f the con tac t „ When a contact or a via between different layers is necessary, make sure to maximize the contact perimeter (not area)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 73

Charge Sharing † Charge Q=CV † A bus example is illustrated to explain the charge sharing phenomenon

„ A bus can be modeled as a capacitor Cb „ An element attached to the bus can be modeled as

a capacitor Cs Bus

Vb Cb Vs Cs (Qb = CbVb ) (Qs = CsVs )

Q Q = C V + C V T T b b s s VR = = (CbVb + CsVs ) /(Cb + Cs ) CT CT = Cb + Cs

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 74

37 Design Margining † The operating condition of a chip is influenced by three major factors „ Operating temperature „ SlSupply voltage „ Process variation † One must aim to design a circuit that will reliably operate over all extremes of these three variables † Design corners „ Simulating circuits at all corners is needed † SS † TT † FF

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 75

Package Issues † Packaging requirements „ Electrical: low parasitics „ Mechanical: reliable and robust „ Thlhermal: efficient heat removal „ Economical: cheap † Bonding techniques Wire Bonding

Substrate

Die

Pad

Lead Frame

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 76

38 Yield Estimation

No. of good chips per wafer Y = ×100% Total number of chips per wafer

WfWafer cost Die cost = Dies per wafer× Die yield π×(wafer diameter/2)2 π× wafer diameter Dies per wafer = − die area 2×die area

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 77

Die Cost

Single die

Wafer

Going up to 12” (30cm)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 78

39 Scaling Theory † Consider a transistor that has a channel width W and a channel length L † We wish to find out how the main electrical chtitiharacteristics change wh en bbthoth didiimensions are reduced by a scaling factor S>1 such that the new transistor has sizes ~ W ~ L W = L = „ S S † Gate area of the scaled transistor ~ A „ A = 2 S † The aspect ratio of the scaled transistor ~ W W = ~ „ L L

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 79

Scaling Theory

† The oxide capacitance is given by ε ox „ Cox = tox „ If the new transistor has a thinner oxide that is ~ tox decrease d as t ox = , then the scal ed devi ce has S ~ Cox = SCox † The transconductance is increased in the scaled device to ~ „ β = Sβ † The resistance is reduced in the scaled device to ~ 1 R „ R = = Sβ (VDD − VT ) S

„ Assume that the supply voltage is not altered

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 80

40 Scaling Theory † On the other hand, if we can scale the voltages in the scaled device to the new values of ~ V ~ V „ V = DD V = T DD S T S „ The resistance of the scaled device would be ~ unchanged with R = R † The effects of scaling the voltage, consider a scaled MOS with reduced voltages of ~ VDS ~ VGS „ VDS = VGS = S S † The current offgy the scaled device is given by ~ Sβ V V V I „ I = [( GS − T ) DS ] = D D 2 S S S S † The power dissipation of the scaled device is ~ ~ ~ V I P „ P = V I = DS D = DS D S 2 S 2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 81

Summary

† We have presented models that allow us to estimate circuit timing performance, and pppower dissipation † Guidelines for low-power design have also been presented † The concepts of design margining were also introduced † The scaling theory has also introduced

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 82

41 Chapter 5 Elements of Physical Design

Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan

Outline † Basic Concepts † Layout of Basic Structures † Cell Concepts † MOS Sizing † Physical Design of Logic Gates † Design Hierarchies

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

1 Basic Concepts † Physical design „ The actual process of creating circuits on silicon „ During this phase, schematic diagrams are carefully translated into sets of geometric patterns that are used to defi ne the on-chip physi ca l struct ures † Every layer in the CMOS fabrication sequence is defined by a distinct pattern † The process of physical design is performed using a computer tool called a layout editor „ A graphics program that allowsallows the designer to specify the shape, dimensions, and placement † Complexity issues are attacked by first designing simple gates and storing their descriptive files in a library subdirectory or folder

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

Basic Concepts

„ The gates constitute cells in the library † Library cells are used as building blocks by creatinggp copies of the basic cells to construct a larger more complex circuit „ This process is called instantiate of the cell „ A copy of a cell is called an instance † Much of the designer’s work is directed toward the gggoal of obtaining a fast circuit in the minimum amount of area „ Small changes in the shapes or area of a polygon will affect the resulting electrical characteristics of the circuit

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

2 CAD Toolsets

† Physical design is based on the use of CAD tools „ Simplify the procedure and aid in the verification process † Physical design toolsets „ Layout editor „ Extraction routine „ Layout versus schematic (LVS) „ Design rule chhkecker (DRC) „ Place and route routine „ Electrical rule checker (ERC)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

Layout of Basic Structures † The masking sequence of the P-substrate technology was established as „ Start with P-type substrate „ nWell „ Active „ Poly „ pSelect „ nSelect „ Active Contact „ Poly contact „ Metal1 „ Via „ Metal2 „ …

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

3 Layout of Basic Structures † It is worth remembering that the features on every level have design rule specifications for the minimum width w of a line, and a minimum edge-to-edge spacing s between adjacent polygons „ For example,

w

S

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

Layouts of PMOS & NMOS

† NMOS Poly L L Poly

n+ n+ W n+ n+ P † PMOS

L Poly L Poly

p+ p+ W p+ p+ N-well

P N-well

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

4 The Layout of a CMOS Inverter † A transistor-level CMOS inverter & the corresponding layout

Vdd

Vdd

Vin Vout Vout Vin

Vss

Vss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

Layouts of a 2-Input NAND Gate

Vdd Vdd

z a z b

a b

Vss Vss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

5 Layouts of a 2-Input NOR Gate

Vdd Vdd

a z b z

V ss Vss b a

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11

Cell Concepts † The basic building blocks in physical design are called cells † Logic gates as basic cells

XNOT XNAND2 XNOR2

Vdd Vdd Vdd Vdd Vdd Vdd in1 in1 in out out out in2 in2

Vss Vss Vss Vss Vss Vss

„ Note that power supply ports for Vdd and Vss are chosen to be at the same locations for every cell „ The width of each cell depends on the transistor sizes and wiring used at the physical level Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

6 Cell Creation Using Primitive Cells

† Create a new cell providing the function „ f=a’b

Vdd

a f b

Vss

2XNOT+XNAND2

Vdd

a f b

Vss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

Layout of Cells

† Vdd & Vss power supply lines

Vdd

nWell PMOSs

D m1-m1 P P-substrate m1-m1 NMOSs

Vss

„ Dm1-m1: edge-to-edge distance between Vdd and Vss

„ Pm1-m1: distance between the middle of the Vdd and Vss lines

„ Pm1-m1=Dm1-m1+Wdd, where Wdd is the width of the power supply lines

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

7 Layout of Cells

† Layout styles of transistors

Vdd

WP

WP

Wn

Wn

Vss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

Effect of Layout Shapes

† Larger spacing between Vdd and Vss

Vdd

ABC D

Vss

† Smaller spacing between Vdd and Vss

Vdd

ABC D

Vss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16

8 Routing Channels † Interconnection routing considerations are very

important considerations for the Vss-Vdd spacing „ In complex digital systems, the wiring is often more comppggylicated than designing the transistor arrays „ The general idea for routing Metal3 Wiring Vdd cell1 cell2 cell3 cell4 cell5 Vss

Routing Metal1 Channel Wiring V dd Metal2 cell6 cell7 cell8 cell9 Wiring Vss Routing Metal1 Channel Wiring

Vdd cell10 cell11 cell12 cell13 Vss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

High-Density Techniques

† Alternate Vdd and Vss power lines and share them with cells above and below „ For example,

Vdd Logic cells Vss Inverted logic cells Vdd Logic cells Vss Inverted logic cells Vdd „ Since no space is automatically reserved for routing, this scheme allows for high-density of placement of cells „ The main drawback is that the connection between rows must be accomplished by using Metal2 or higher

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

9 High-Density Techniques

† MOS transistor placement

PMOS transistors

Vdd

PMOS transistors nWell

P-substrate NMOS transistors

Vss

P-substrate NMOS transistors

nWell PMOS transistors

Vdd

PMOS transistors

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

Port Placement

† An example of the port placement in a cell

Vdd

Metal1 input Metal1 output

Vss

To routing channel

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

10 MOS Sizing in Physical Design

† A minimum-size MOS transistor is the smallest transistor that can be created using the design rule set † Scaling of the unit transistor L L L 4W W 2W

X2X 4X

LL

W X2X 2W

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

Physical Designs of Complex Gates

C D Vdd

B

A z Z C AB Vss D ABC D

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

11 Physical Design of XNOR Gate (1)

A Z’ B Z

Vdd

A Z’ Z’ z B

AB

Z’ Vss

A B

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

Physical Design of XNOR Gate (2)

A B Z

Vss Vdd

z

B

A

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

12 Automation of Physical Design

ABC D E

Vdd

E A D C B E

Vss

D E C AB D E C AB

Vdd

P

N

Vss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

Standard-Cell Physical Design

WVdd

Wp

Dnp

Wn

abcd z WVss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

13 Standard-Cell Physical Design

Vdd Vdd

Vss Vss

abc z abc z

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

Gate-Array Physical Design

Vdd

Vss

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14 Gate-Array Physical Design

Vdd

Gate array cells

Routing channels

Vss

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Sea-of-Gate Physical Design

well contacts

Vdd supply

P-transistors

poly gates

N-transistors

Vss supply substrate contacts

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15 Sea-of-Gate Physical Design

abc

abc z z

abc

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

CMOS Layout Guidelines

† Run VDD and VSS in metal at the top and bottom of the cell † Run a vertical ppyoly line for each g ate inp ut † Order the poly gate signals to allow the maximal connection between transistors via abutting source-drain connection

† Place n-gate segments close to VSS and p-gate segments close to VDD † Connection to complete the logic gate should be made in poly, metal, or, where appropriate, in diffusion

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

16 Guidelines for Improving Density

† Better use of routing layers – routes can occurs over cells † More “merged” source-drain connections † More usage of “white” space in sparse gates † Use of optimum device sizes – the use of smaller devices leads to smaller layouts

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

Layout Optimization † Vary the size of the transistor according to the position in the structure

Vdd clk

F

A<0> A<1> F A<2> A<3>

Vss

clk A<3> A<2> A<1> A<0> † In submicron technologies, where the source/drain capacitances are less, such that this improvement is limited

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

17 Layout Optimization

2

A

A B C Z B C D D

1

Vdd

Right Z Wrong

Vss ABC D ABC D

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Layouts of Transmission Gates

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18 Routing to Transmission Gates

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2-Input Multiplexer

c

a z -c a z b b

c

c-c

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19 Design Hierarchies

Layout level

cell1 cell2 celln Cell library

Subsystems Module 1 Module m

Module 1 Module 4 Chips Module 3 Module 5 Module 2 Module 6

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Summary

† Basic physical design concepts have been introduced † Cell concepts have also presented † Layout optimization guidelines have been summarized † Design hierarchy has been briefly introduced

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40

20 Chapter 6 Combinational CMOS Circuit and Logic Design

Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan

Outline † Advanced CMOS Logic Design † I/O Structures

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

1 Pseudo-NMOS Logic † A pseudo-NMOS inverter

VDD β p F

A β n VL Time „ The low output voltage can be calculated as β β (V − V )V = P (V − | V |) 2 n DD tn L 2 DD tp

for Vtn = −Vtp = Vt

β P V L = (V DD − VT ) 2 β n β /β „ Thus VL depends strongly on the ratio p n „ The logic is also called ratioed logic

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

Pseudo-NMOS Logic † An N-input pseudo-NMOS gate

Vout

NMOS inputs network

† Features of pseudo-NMOS logic „ Advantages † Low area costÆonly N+1 transistors are needed for an N- input gate

† Low input gate-load capacitanceÆCgn „ Disadvantage † Non-zero static power dissipation

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

2 Pseudo-NMOS XOR Gate

† An example of XOR gate realized with pseudo- NMOS logic „ The XOR is defined by

Y = X1 ⊕ X 2 = X1 X 2 + X1X 2 = X1X 2 + X1 X 2 = X1X 2 + X1 + X 2

Y

X1 X2

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Choosing Transistor Sizes † Goals „ Noise margin „ Power consumption „ Speed † Noise margin

„ It is affected by the low output voltage (VL) β /β „ VL is determined by p n † Speed „ The larger the W/L of the load transistor, the faster the gate will be, particularly when driving many other gates „ Unfortunately, this increases the power dissipation and the area of the driver network

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

3 Choosing Transistor Sizes † Power dissipation „ A pseudo-NMOS logic gate having a “1” output has no static (DC) power dissipation. „ However, a pseudo-NMOS gate having a “ 0” output has a static power dissipation † The static power dissipation is equal to the current of the PMOS load transistor multiplied by the power supply voltage. Thus, the power is given by μ C W P = p ox ( ) (V − V ) 2V dc 2 L P gs tp dd „ The large PMOS results in large power dissipation † Power-reduction methods „ Select an appropriate PMOS „ Increase the bias voltage of PMOS

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

Choosing Transistor Sizes † A simple procedure for choosing transistor sizes of pseudo-NMOS logic gates „ The relative size (W/L) of the PMOS load transistor is chosen as a comprom ise between sp eed and size versus power dissipation „ Once the size of the load transistor has been chosen, then a simple procedure can be used to choose the W/Ls of the NMOS transistors in the NMOS network

† Let (W/L)eq be equal to one-half of the W/L of the PMOS load transistor

† For each transistor Qi, determine the maximum number of drive transistors it will be in series, for

all possible inputs. Denote this number ni.

† Take (W/L)i=ni(W/L)eq

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

4 An Example † Choose appropriate sizes for the pseudo- NMOS logic gate shown below

„ (W/L)8 is 5 um/0.8 um

„ (W/L)eq is (5/0. 8)/2=3. 125 „ Gate lengths of drive transistors are taken at their minimum 0.8um Q 5/0.8 „ Thus we can obtain 8 Y Transistor Size X1 Q1 X2 Q2 X4 Q4 Q1 2.5um/0.8um

Q2 50um/08um5.0um/0.8um X5 Q5 Q3 5.0um/0.8um

Q4 10um/0.8um X Q3 X Q6 Q5 10um/0.8um 3 6

Q6 10um/0.8um X Q7 Q7 10um/0.8um 7

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

Dynamic Logic † To eliminate the static power dissipation of pseudo-NMOS logic „ An alternative technique is to use dynamic precharging called dynamic logic as shown below

PR

Vout

NMOS inputs network

„ Normally, during the time the output is being precharged, the NMOS network should not be conducting † This is usually not possible

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

5 Dynamic Logic † Another dynamic logic technique

Vout

NMOS Evaluate inputs network Precharge CLK

CLK

† Two-phase operation: precharge & evaluate † This can fully eliminate static power dissipation

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Examples of Dynamic Logic

† Two examples

clk clk A Y=ABC C Z=(A+B).C B

AB C

clk clk

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6 Problems of Dynamic Logic

† Two major problems of dynamic logic „ Charge sharing „ Simple single-phase dynamic logic can not be cascaded † Charge sharing

clk=1 A 1 C A CVDDA= () C++ C12 C V B C C C C 1 2 1 C 1 VVADD= CC++12 C C C 0 2 charge sharing model E.g., if CC12= = 0.5 C clk=1 then output voltage is

VDD/2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

Problems of Dynamic Logic

† Simple single-phase dynamic logic can not be cascaded

clock N1 N2

N1 inputs N Logic N Logic

Td1 Erroneous State clock N2

Td2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

7 CMOS Domino Logic † Domino logic can be cascaded † The basic structure of domino logic

Vout

NMOS inputs network

CLK

† Some limitations of this structure „ Each gate must be buffered „ Only noninverting structures are possible

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

A Domino Cascade † An example of cascaded domino logics

Stage 1Stage 2Stage 3

Vout NMOS NMOS NMOS network network network

CLK

precharge evaluate

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8 Charge-Keeper Circuits † The domino cascade must have an evaluation interval that is long enough to allow every stage time to discharge „ This means that charge sharing and charge leakage processes that reduce the internal voltage may be limiting factors † Two types of modified domino logics can cope with this problem „ Static version „ Latched version

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

Charge-Keeper Circuits † Modified domino logics

Weak PMOS Weak PMOS

Z Z

Inputs N-logic Inputs N-logic Block Block

Clk Clk

Static version Latched version

„ The aspect ratio of the charge-keeper MOS must be small so that it does not interfere with discharge event Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

9 Complex Domino Gate † In a complex domino gate, intermediate nodes have been provided with their own precharge transistor

F

N-logic

N-logic N-logic

N-logic

CLK

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

Multiple-Output Domino Logic

† Multiple-output domino logic (MODL) allows two or more outputs from a single logic gate † The basic structure of MODL

F1 A

F2 B

CLK

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

10 A Multiple-Output Domino Logic Gate

F1 A⊕ B ⊕C ⊕ D D D’ A⊕ B ⊕C F2 C CCC’

F3 A⊕ B BB’B’ B

A A’

CLK

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

NP Domino Logic † A further refinement of the domino logic is shown below „ The domino buffer is removed, while cascaded logic blocks are alternately composed of P- and N-transistors

CLK -CLK CLK

N-logic P-logic N-logic

Other P blocks Other N blocks

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

11 NP Domino Logic

† NP domino logic with multiple fanouts

Other N blocks Other P blocks

CLK -CLK CLK

N-logic P-logic N-logic

Other P blocks Other N blocks

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

Advanced CMOS Logic Design

† Pass-Transistor Logic

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

12 Pass-Transistor Logic

† Model for pass transistor logic

Control signals

Pi

Pass signals Product term (F) Vi

† The product term

„ F=P1V1+P2V2+…+PnVn

„ The pass variables can take the values {0,1,Xi,- Xi,Z}, where Xi and –Xi are the true and complement of the ith input variable and Z is the high-impedance Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

Pass-Transistor Logics

† Different types of pass-transistor logics for two-input XNOR gate implementation

A -A A -B -B -A OUT A OUT OUT B B B

A

Complementary Single-polarity Cross-coupled

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

13 Full-Swing Pass-Transistor Logic

† Modifying NMOS pass-transistor logic so full-level swings are realized

B Y

A

† Adding the additional PMOS has another advantages „ It adds hysteresis to the inverter, which makes it less likely to have glitches

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

Differential Logic Design

† Features of the differential logic design „ Logic inversions are trivially obtained by simply interchanging wires without incurring a time delay „ The load net work s will oft en consi st of two cross- coupled PMOS only. This minimizes both area and the number of series PMOS transistors † Disadvantage „ Two wires must be used to represent every signal, the interconnect area can be significantly greater. In applications in which only a few close gates are being driven, this disadvantage is often not as significant as the advantages † Thus differential logic circuits are often a preferable consideration Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

14 A Fully Differential Logic Circuit † One simple and popular approach for realizing differential logic circuit is shown below „ The inputs to the drive network come in pairs, a single- ended signal and its inverse „ The NMOS network can be divided into two separate networks, one between the inverting output and ground, and a complementary network between the noninverting output and ground

- + Vout Vout

V1 + V1 - Fully Differential NMOS Network Vn+

Vn-

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Examples

† Differential CMOS realizations of AND and OR functions

AB AB A+B A+B

A A A B A B B B

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15 Examples

† Differential CMOS realization of the

function Vout=(A+B’)C+A’E

Vout Vout

C E A E

A B A B C

A

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

Differential Split-Level Logic † Differential split-level (DSL) logic „ A variation of fully differential logic „ A compromise between a cross-coupled load with no d. c. power dissipation and a continuously-on load with d.c. power dissipation

- + Vout Vout

Vref Vref V- V+

V1+ V - 1 Differential NMOS Network Vn+

Vn-

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

16 Differential Split-Level Logic † Features of DSL logic „ The loads have some of the features of both continuous loads and cross-coupled load † Both outputs begin to change immediately † The loads do have d.c. power dissipation, but normally much less than pseudo-NMOS gates and dynamic power dissipation „ The nodes V+, V-, and all internal nodes of the NMOS network have voltage changes between

greater than 0V and Vref-Vtn † This reduced voltage swing increases the speed of the logic gates „ The maximum drain-source voltage across the NMOS transistors is reduced by about one-half † This greatly minimizes the short-channel effects Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

Differential Pass-Transistor Logic † It is not necessary to wait until one side goes to low before the other side goes high „ Pass-transistor networks for most required logic functions exist in which both sides of the cross- coupled loads are driven simultaneously „ This minimizes the time from when the inputs changes to when the low-to-high transition occurs

- + Vout Vout

V1+ V1- Pass-Transistor Network Vn+ Vn-

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

17 Differential Pass-Transistor Logic † Other features of pass-transistor logic „ It removes the ratio requirements on the logic and has guaranteed functionality „ The cross-coupled loads restore signal levels to

full Vdd levels, thereby eliminating the voltage drop † Examples:

AB AB ABA+B A+B

- + - + A- A A+ A- A+ A A A B+ B- - B+ B

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

Dynamic Differential Logic

† A differential Domino logic gate

CLK

- + Vout Vout

V1+ V1- Differential NMOS Network Vn+

Vn-

CLK

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36

18 Dynamic Differential Logic † Features of dynamic Domino logic „ Its d.c. power dissipation is very small, whereas its its sppqgeed still quite good „ Because of the buffers at the output, its output drive capability is also very good „ One of major limitations of Domino logic, the difficulty in realizing inverting functions, is eliminated because of the differential nature of the circuits

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37

Dynamic Differential Logic † When the fan-out is small, the inverters at the output can be eliminated and the inputs to the charge-keeper transistors can be taken from the opposite output CLK

- + Vout Vout

V1+ V1- Differential NMOS Network Vn+

Vn-

CLK

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38

19 Clocked CMOS (C2MOS) † Structure of a C2MOS gate „ Ideally, clocks are non-overlappingÆCLK X CLK=0 „ CLK=1, f is valid „ CLK=0, the output is in a high-impedance state. During

this time interval, the output voltage is held on Cout

… PMOS Network

CLK f CLK +

Cout Vout

… NMOS - Network

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Examples of C2MOS Logic Gates

B B A

A CLK AB CLK CLK A+B

Cout A CLK

Cout B B A

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20 Dw f MLg Gates † The problem of charge leakage „ Cause that the output node cannot hold the

charge on Vout very long † The basi cs of ch arge leak age are sh own V(t) below Vdd V CLK=1 1 i iout p V + X CLK=0 i Cout Vout n - 0 t th

V ( t ) t dV I L I L iout = in − i p = −Cout dV = − dt ⇒ V (t) = V1 − t ∫V ∫0 dt 1 C out C out iout I L ⇒ dV = − dt V (th ) = V1 − th = V X C Cout out C ⇒ t = out (V − V ) Assume iout is a constant IL h 1 X I L Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41

I/O Pads † Types of pads

„ Vdd, Vss pad „ Input pad (ESD) „ OtOutpu t pad (di(driver ) „ I/O pad (ESD+driver) † All pads need guard ring for latch-up protection † Core-limited pad & pad-limited pad Core-limited pad Pad-limited pad

PAD PAD

I/O circuitry I/O circuitry

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21 ESD Protection

† Input pad without electrostatic discharge (ESD) protection

Assume I=10uA, Cg=0.03pF, and t=1us PAD The voltage that appears on the gate is about 330volts

† Input pad with ESD protection

PAD

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43

Tristate & Bidirectional Pads

† Tristate pad

output-enable OE P OE D N P OUT OUT 0 X 0 1 Z PAD 1 0 1 1 0 N 1 1 0 0 1 data D

† Bidirectional pad

PAD

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44

22 Schmitt Trigger Circuit

† Voltage transfer curve of Schmitt circuit

Vout

VDD

Vin VT- VT+ VDD

„ Hysteresis voltage VH=VT+-VT-

„ When the input is rising, it switches when Vin=VT+

„ When the input is falling, it switches when Vin=VT-

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45

Schmitt Trigger Circuit

† Voltage waveform for slow input

Vout V DD Vin

VT+

VT-

Time

† Schmitt trigger turns a signal with a very slow transition into a signal with a sharp transition

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46

23 Schmitt Trigger Circuit

† A CMOS version of the Schmitt trigger circuit

VDD P1 VFP P3

P2

Vin Vout

N2

N3 VFN N1

„ When the input is rising, the VGS of the transistor N2 is given by VGS2 =Vin −VFN V =V „ When in T + , N2 enters in conduction mode which means

VGS2 =VTn

„ Then VFN =VT+ −VTn

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47

Summary

† The following topics have been introduced in this chapter „ CMOS Logic Gate Design „ Advanced CMOS Logic Design „ Clocking Strategies „ I/O Structures

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48

24 Chapter 7 Sequential Circuits

Jin-Fu Li Advanced Reliable Syy()stems (ARES) Lab. Department of Electrical Engineering National Central University Jungli, Taiwan

Outline † Latches & Registers † Sequencing Timing Diagram

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

1 Sequencing † Combinational logic „ Output depends on current inputs † Seqqguential logic „ Output depends on current and previous inputs „ Requires separating previous, current, future „ Called state or tokens „ Ex: FSM, pipeline

clk clk clk clk

in out CL CL CL

Finite State Machine Pipeline

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

Sequencing Elements † Latch: Level sensitive „ A.k.a. transparent latch, D latch † Flip-flop: edge triggered „ A.k.a. master-slave flip-flop, D flip-flop, D

register clk clk

† Timing Diagrams D Q DQ Flop Latch „ Transparent

„ Opaque clk „ Edge-trigger D

Q (latch)

Q (flop)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

2 Latches † Negative-level sensitive latch

D 0 clk Q 1 D

clk Q

† Positive-level sensitive latch

clk 0 Q D D 1

clk Q

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Registers † Positive-edge triggered register (single- phase clock)

clk D 0 QM 0 D Q 1 1 S S QM clk clk Q master slave

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3 Registers † Operations of the positive-edge triggered register

clk=0

clk=1

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

Registers † CMOS circuit implementation of the positive- edge triggered register

D

Q

clk clk

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

4 Single-Phase Latch † Positive active-static latch -clk

D Q 1. Low area cost 2. Driving capability of clk D must override the feedback inverter

-clk

D Q clk clk

-clk

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

Typical Latch Symbolic Layouts

Vdd

clk

D -clk Q D -clk Q

clk

-clk clk

Vss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

5 CVSL (Differential) Style Register † The following figure shows latches based on a CVSL structure „ An N and a P version are shown that are cascaded to form a register

-Q D Q

clk

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11

Double-Edge Triggered Register † The following figure shows latches that may be used to clock data on both edges of the clock Latch 1 Latch 2 clk clk

D -D Q2 -Q2

Q1 -Q1 D-D

clk clk

clk clk Q1 Q2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

6 Double-Edge Triggered Register † Double-edge triggered register can be implemented by combining Latch 1 & Latch 2 as follows Latch 2

D Q2

-Q2 Q

-Q

-Q1

Q1 clk clk Latch 1 enabled Latch 2 enabled Latch 1 Q2=-Q2=low Q1=-Q1=high

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

Asynchronously Register † Asynchronously resettable register

-clk -reset

Q

clk clk -clk clk

D

-clk clk -clk

clk -reset

Q

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

7 Asynchronously Register † Asynchronously resettable and settable register

-clk -reset

Q

clk clk clk -clk

D

-clk clk -clk

-set

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

Dynamic Latches & Registers † Dynamic single clock latches

clk clk

clk D -Q D D -clk -clk -clk

† Dynamic single clock registers

clk -clk clk -clk -Q D Q D Q -clk clk -clk clk

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16

8 Dynamic Latches † Clock active high latch

Dn CLK Xn Qn 0 H10 D X 1 H 0 1 CLK Q 1 L Xn-1 Qn-1

0 L 1 Qn-1

† Clock active high latch with buffer

D X

CLK -Q

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

Dynamic Latches † Clock active low latch

D Dn CLK Xn Qn CLK 0 L10 1 L 0 1 X Q 1 H 0 Qn-1

0 H Xn-1 Qn-1

† Clock active low latch with buffer

D

CLK

X -Q

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

9 Dynamic Latches † Clock active high and low latches without feedback

D X D

CLK Q CLK

X Q

† The problem of leakage current „ Assume that the capacitance of node X is 0.002pF and the leakage current I is 1nA † Therefore, T=CV/I=0.002pFx5V/1nA=100us † That is, the latch needs to be refreshed each 100us. Otherwise, the output Q will become high

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

Sequencing Methods

T † Flip-flops c Flip-Flops † 2-Phase Latches clk clk clk † Pulsed Latches

lop Combinational Logic lop F F 2-Phase Transparent Latches Transparent 2-Phase

φ1

tnonoverlap tnonoverlap

Tc/2 φ2

φ1 φ2 φ1

Combinational Combinational Logic Logic Latch Latch Latch Half- Cycle 1 Half- Cycle 1 Pulsed Latches Pulsed

φp tpw

φp φp

Combinational Logic Latch Latch

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

10 Timing Diagrams

Contamination and A tpd Combinational AY Propagation Delays Logic

Y tcd Logic Prop. Delay tpd LiLogic CCtont. DDlelay tcd clk t clk setup t Latch/Flop Clk-Q Prop Delay hold tpcq t Latch/Flop Clk-Q Cont. Delay DQD

ccq Flop t Latch D-Q Prop Delay pcq tpdq Q tccq Latch D-Q Cont. Delay tpcq Latch/Flop Setup Time tsetup clk t t clk setup hold t Latch/Flop Hold Time t hold tccq pcq D DQ tpdq Latch tcdq Q

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

Max-Delay: Flip-Flops

tTt≤− + t pdc(setup pcq ) sequencing overhead clk clk

Q1 D2 Combinational Logic F1 F2

Tc

t clk setup tpcq

Q1 tpd

D2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

11 Max Delay: 2-Phase Latches

ttpd=+≤− pd12 t pd T c()2 t pdq  φ1 φ2 φ1 sequencing overhead D1Q1 Combinational D2Q2Combinational D3 Q3

L1 Logic 1 L2 Logic 2 L3

φ1

φ2

Tc

D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

Max Delay: Pulsed Latches tT≤−max ttt , + − t pd c () pdq pcqsetup pw sequencing overhead

φp φp

D1Q1 D2 Q2 CbiiCombinationa lLil Logic 2 L1 L

Tc

D1 tpdq

(a) tpw > tsetup Q1 tpd

D2

φp

tpcq Tc tpw

Q1 tpd tsetup

(b) tpw < tsetup D2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

12 Min-Delay: Flip-Flops

ttcd≥−hold t ccq clk

Q1 1 CL F

clk

D2 F2

clk

t Q1 tccq cd

D2 thold

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

Min-Delay: 2-Phase Latches

tttttcd1, cd 2≥−− hold ccq nonoverlap

φ1

Hold time reduced by Q1 1 CL nonov erlap L

φ Paradox: hold applies 2 twice each cycle, vs. D2 only once for flops. L2

tnonoverlap But a flop is made of φ1 two latches! tccq φ2

Q1 tcd

D2 thold

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

13 Min-Delay: Pulsed Latches

ttcd≥−+hold tt ccq pw Hold time increased φ by pulse width p Q1 CL L1

φp

D2 L2

φp tpw

thold

Q1 tccq tcd

D2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

Time Borrowing † In a flop-based system: „ Data launches on one rising edge „ Must setup before next rising edge „ If it arrives late, system fails „ If it arrives early, time is wasted „ Flops have hard edges † In a latch-based system „ Data can pass through latch while transparent „ Long cycle of logic can borrow time into next „ As long as each loop completes in one cycle

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

14 Time Borrowing Example

φ1

φ2

φ1 φ2 φ1

Combinational Combinational Logic (a) Logic Latch Latch Latch

Borrowing time across Borrowing time across half-cycle boundary pipeline stage boundary

φ1 φ2

Combinational (b) Combinational Logic Logic Latch Latch

Loops may borrow time internally but must complete within the cycle

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29

How Much Borrowing?

φ1 φ2

D1Q1 D2 Q2 Combinational Logic 1 2-Phase Latches L1 L2 T ttt≤−c + borrow( setup nonoverlap ) φ 2 1

t φ2 nonoverlap T Pulsed Latches c

tsetup Tc/2 tborrow tttborrow≤−pw setup Nominal Half-Cycle 1 Delay

D2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30

15 Clock Skew † We have assumed zero clock skew † Clocks really have uncertainty in arrival time „ Decreases maximum propagation delay „ Increases minimum contamination delay „ Decreases time borrowing

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

Skew: Flip-Flops

clk clk

Q1 D2 Combinational Logic tTtt≤− + + t F1 F2 pd c( pcq setup skew ) Tc sequencing overhead

clk t tt≥−+ tt pcq cdhold ccq skew tskew t Q1 tpdq setup

D2

clk

Q1 CL F1

clk

D2 2 F

tskew clk thold

Q1 tccq

D2 tcd

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

16 Skew: Latches

2-Phase Latches φ1 φ2 φ1

D1Q1 Combinational D2Q2Combinational D3 Q3

tT≤− 2 t L1 Logic 1 L2 Logic 2 L3 pd c() pdq sequencing overhead

φ1 tttttcd1, cd 2≥−− hold ccq nonoverlap + t skew

φ2

Tc ttttborrow≤−() setup + nonoverlap + skew 2 Pulsed Latches tT≤−max ttt , + − tt + pd c () pdq pcqsetup pw skew sequencing overhead

ttcd≥+−+hold ttt pw ccq skew

ttttborrow≤−pw () setup + skew

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

Two-Phase Clocking † If setup times are violated, reduce clock speed † If hold times are violated, chip fails at any speed † In this class, working chips are most important „ No tools to analyze clock skew † An easyyyg way to guarantee hold times is to use 2-phase latches with big nonoverlap times

† Call these clocks φ1, φ2 (ph1, ph2)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

17 Safe Flip-Flop † In class, use flip-flop with nonoverlapping clocks „ Very slow – nonoverlap adds to setup time „ But no hold times † In industry, use a better timing analyzer „ Add buffers to slow signals if hold time is at risk

Q φ2 φ1 X D Q

φ2 φ1 φ2 φ1

φ2 φ1

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

Clock Distribution † In a large CMOS chip, clock distribution is a serious problem „ For example,

† Vdd=5V

† Creg=2000pF (20K register bits @ 0.1pF)

† Tclk=10ns

† Trise/fall=1ns

† Ipeak=C(dv/dt)=(2000p)x(5/1n)=10A 2 † Pd=C(Vdd) f=2000px25x100=5W

† Methods for reducing the values of Ipeak and Pd „ Reduce C „ Interleaving the rise/fall time

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36

18 Clock Distribution † Clocking is a floorplanning problem because clock delay varies with position on the chip † Ways to improve clock distribution „ Physical design † Make clock delays more even † At least more predictable „ Circuit design † Minimizing delays using several stages of drivers † Two most common types of physical clocking networks „ H-tree clock distribution „ Balanced-tree clock distribution

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37

H-Tree Clock Distribution

clock

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38

19 H-Tree Clock Distribution

Source: Prof. Irwin

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39

Balanced-Tree Clock Distribution

clock

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40

20 Reduce Clocking Power † Techniques used to reduce the high dynamic power dissipation „ Use a low capacitance clock routing line such as metal3. This layyfmer of metal can be, ,fmp, for example, dedicated to clock distribution only „ Using low-swing drivers at the top level of the tree or in intermediate levels Vdd C1 C2 CA clkp -clkp

Vout

clk -clk n n CB C3 C4 Gnd

Clock

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41

Power & Ground Distribution

Source: Prof. Irwin

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42

21 Chapter 8 Introduction to 3D Integggyration Technology using TSV

Jin-Fu Li Department of ElilElectrical EEiingineering National Central University Jungli, Taiwan

Outline † Why 3D Integration † An Exemplary TSV Process Flow † Stac king Stra teg ies † Concept of 3D IC Design † Summary

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

1 IC Technology Evolution

Chip Single-chip package

Printed wiring board(PCB) RF Analog Flash

CPU

Chemical & Bio Sensors Package Other Sensors, Imagers

Nano Device 3D-SIP MEMS RF ADC DAC

Memory Stack

Processor

3D-IC Energy/Power

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU

Why 3D Integration † Integrating more and more transistors in a single chip to support more and more powerful functionality is a trend „ Using 2D int egrati on tech nol ogy to impl em ent suc h complex chips is more and more expensive and difficult † Some alternative technologies attempting to cope with the bottlenecks of 2D integration technology have been p rop osed † 3D integration technology using through silicon via (TSV) has been acknowledged as one of the future chip design technologies

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

2 3D Integration Technology Using TSV

† 3D integration technology using TSV „ Multiple dies are stacked and TSV is used for the inter-die interconnection

Die 1 Die 2 Die 3

TSV † The fabrication flow of a 3D IC „ Die/wafer preparation „ Die/wafer assembly

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

What is TSV † Through Silicon Via (TSV): „ A via that goes through the silicon substrate „ Used for dies stacking

Top Bump

Wiring layer Al wiring TSV

CMOS Diameter 50 um or less

Via made by laser SiO2 insulator Top Bump

† Typical TSV technologies „ Via-first, via-middle, and via-last technologies

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

3 Via-First TSV Technology

† Via-First TSV

(1) Before CMOS

(2) After CMOS & BEOL

Source: Yole, 2007.

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

Via-Last TSV Technology

† Via-Last TSV

(1) After BEOL & before bonding

(2) After bonding

Source: Yole, 2007.

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

4 An Exemplary Via-Last Process Flow (1/6)

† Step 1: A wafer with CMOS circuits … … …

MOSFET MOSFET Ref ：ITRI

Substrate

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

An Exemplary Via-Last Process Flow (2/6) † Step 2: via etching … … Via machining … (by etching or laser dilling)

MOSFET MOSFET

Ref ：ITRI

Substrate

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

5 An Exemplary Via-Last Process Flow (3/6) † Step 3: via filling … … … Via filling

MOSFET MOSFET

Ref ：ITRI Substrate

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11

An Exemplary Via-Last Process Flow (4/6) † Step 4: wafer thinning … … …

50 ~ 100 μm

Wafer thinning Ref ：ITRI

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

6 An Exemplary Via-Last Process Flow (5/6) † Step 5: micro bump forming

Micro Bump … … …

Ref ：ITRI

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

An Exemplary Via-Last Process Flow (6/6) † Step 6: stacking … … …

TSV

Micro (μ) Bump ABF(Ajinomoto Built-in Film) … … …

Ref ：ITRI

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

7 An Exemplary 3D IC using Via-Last TSV

Bonding Bonding Adhesive Adhesive P-Substrate 3rd Chip

TSV N+P+ P+ N+ N+P+ N+P+ N+ N+P+ N+ N Well N Well N Well

P-Substrate 2nd Chip

TSV N+P+ P+ N+ N+P+ N+P+ N+ N+P+ N+ N Well N Well N Well

P-Substrate 1st Chip

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

3-Tier 3D IC Cross-Section

Source: E. G. Friedman, University of Rochester.

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16

8 Die/Wafer Assembly

† Bonding technologies for 3D ICs „ Wafer-to-wafer (W2W), Die-to-Wafer (D2W), and Die-to-Die (D2D) † Comparison of different bonding technologies

D2D D2W W2W Yield High High Low Flexibility High Good Poor Production Throughput Low Good High

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

Stacking Strategies

μ Bump μ Bump μ Bump

TSV Die2

D2D Vias

Metal

Die1 Active Si

Bulk Si

„face-to-face „back-to-back „face-to-back

Lewis, D.L. et al, “A ScanIsland Based Design Enabling Prebond Testability in DieStacked Microprocessors,” in proc. IEEE International Test Conference (ITC), 2007, pp. 1-8

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

9 Fabrication Steps for Face-to-Face Stacking

1 2 3 4 5 Die2 Die2 Die2

Metal Metal Metal Metal Metal

Active Si Active Si Active Si Active Si Active Si

Bulk Si Bulk Si Bulk Si Bulk Si Bulk Si Die1 Die 2 Die 1 Die2 Die1 Die1 Die1

Loh, Gabriel H. et al, “Processor Design in 3D Die-Stacking Technologies,” in IEEE Micro, vol.27, issue 3, pp. 31-48, 2007

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

Fabrication Steps for Face-to-Back Stacking

1 2 3 4 5 Die2 Die2

Handle wafer

Metal Metal Metal Metal Metal Active Si Active Si Active Si Active Si Active Si Bulk Si Bulk Si Bulk Si Bulk Si Bulk Si Die1 Die2 Die1 Die2 Die1 Die2 Die1 Die1

Loh, Gabriel H. et al, “Processor Design in 3D Die-Stacking Technologies,” in IEEE Micro, vol.27, issue 3, pp. 31-48, 2007

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

10 Electrical Characteristics of TSV

† Capacitance of TSV

Top Bump

Wiring layer Al wiring TSV

CMOS Diameter TSV Length

Dielectric Thickness

TSV Dia TSV Diel TSV Length Cap [fF] [[]um] Thk [[]nm] [[]um] 5 50 20 239.5 5 100 20 135.2 10 50 20 496.4 10 100 20 288.3

Source: Proceedings of IEEE, pp. 101, Jan. 2009 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

RC Characteristics of TSV

1 FO4 = 22 ps Die2 (BSIM 70nm) ~ 0.35*RCviastack Die1 a

D2D vi M9

via9 225 ps > 11 FO4

… 1-mm top-level metal M2 RC … viastack 4x minimum size via2

M1 8 ps via1 F2F D2D via ~ 1/3*FO4

MOSFET

Loh, Gabriel H. et al, “Processor Design in 3D Die-Stacking Technologies,” in IEEE Micro, vol.27, issue 3, pp. 31-48, 2007 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

11 Benefits of 3D Integration

† Benefits of 3D integration over 2D integration „ High functionality „ HhHigh performance „ Small form factor „ Low energy

Source: Proceedings of IEEE, Jan. 2009

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

High Functionality

† Heterogeneous integration Chemical & † Combine disparate Bio Sensors Other technologies Sensors, „ DRAM, flash, RF, etc. Imagers Nano † Combine different Device MEMS technology RF ADC nodes DAC „ E.g., 65nm technology and 45nm technology Memory Stack

Processor

Energy/Power

Source: Proceedings of IEEE, Jan. 2009

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

12 High Performance

† 3D integration technology can reduce the length of the long interconnections using TSV † For example,

xx xx B B y 1 2 1 2 z

y 3 4 y 3 4 A A

L =x+2y 2D L3D=x+y+z

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

High Bandwidth

† 3D IC allows much more IO resources than 2D IC † For exampp,le, „ Stacking of processor and memory

Memory Memory

CPU CPU

Many TSVs are allowed for Bandwidth is limited by IOs high bandwidth transportation

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

13 Low Energy

Energy SOB

SIP

RF Analog Flash CPU 3D-IC

Package

RF

Analog

Flash

SRAM

CPU

Package Technology

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

3D IC Design Approaches

rs rf Idq rob L2 bpred D$ IF tlb Multiple I$ Cores alu stq CPU L2 dec L2 L2

„Entire Core „Function Unit Block (FUB)

VDD

X gnd

Y

„Logic gates (FUB splitting) „Transistors (circuit) Level

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

14 2D RAM

Bitlines Wordlines 0 ec ec ec ec k 1 k 2 k 3 k D D D D Bloc Bloc Bloc Bloc WL WL WL WL WL WL

Mux & SA Mux & SA Mux & SA Mux & SA Address input WL Pre-Dec Data output Mux & SA Mux & SA Mux & SA Mux & SA ck 4 ck 4 ck 4 ck 4 Dec Dec Dec Dec WLs o o o o L L L L Bl Bl Bl Bl W W W W 128

RAM Subarray 256 BLs

Y.-F. Tsai et al, “Design Space Exploration for 3-D Cache,” IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp. 444-555, 2008

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29

3D Wordline-Partitioned RAM WL Dec WL WL Dec WL Dec WL Dec WL 2 2 Block 1-2 2 Block 0-2 Block 2-2 Block 3-2 1 c c c c - - -

SA 0-2 SA 1-2 SA 2-2 SA 3-2 WL De WL WL De WL De WL De WL Block 3- Block 1 Address input Block 0 Block 2 WL Pre-Dec SA 0- SA 1- SA 2- Data output SA 3-1 SA 4-2 2SA 5-2 2SA 6-2 2SA 7-2 WL Pre-Dec SA 4- SA 5- SA 6- SA 7-1 2 2 2 WL Dec WL Dec WL Dec WL Dec WL Block 4-2 Block 5-2 Block 6-2 Block 7-2 c c c c -2 -2 -2 -1 Ls e e e e 4 5 6 7 W WL D WL D WL D WL D WL Block Block Block Block 128

128 BLs

Y.-F. Tsai et al, “Design Space Exploration for 3-D Cache,” IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp. 444-555, 2008

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30

15 3D Bitline-Partitioned RAM

Block 0-2 Block 1-2 Block 2-2 Block 3-2 WL Dec WL Dec WL Dec WL Dec WL Mux & SA Mux & SA Mux & SA Mux & SA Block 0-2 Block 1-2 Block 2-2 Block 3-1 WL WL WL WL WL Address input Dec Dec Dec Dec WL Pre-Dec Mux & Mux & Mux & Data output Mux & SA Mux & SA SA Mux & SA SA Mux & SA SA Mux & SA WL Pre-Dec Block 4-2Mux & Block 5-2Mux & Block 6-2Mux & Block 7-2 Mux & SA WL Dec WL SA Dec WL SA Dec WL SA Dec WL Block 4-1 Block 5-1 Block 6-1 Block 7-1 L Dec L Dec L Dec L Dec 4 WLs W W W W 6

256 BLs

Y.-F. Tsai et al, “Design Space Exploration for 3-D Cache,” IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp. 444-555, 2008

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

Design Example: 3D RAM

Source: G. H. Loh, ISCA 2008

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

16 Design Example

Source: ASP-DAC 2009.

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

Road Map of 3D Integration with TSVs

Source: Proceedings of IEEE, Jan. 2009

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

17 Summary

† 3D integration technology using TSV is one of future IC design technologies † It can offer many advantages over the 2D integration technology † However, there are some challenges should be overcome before volume-production of TSV- based 3D IC becomes possible

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

18