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Leakage Power Analysis and Reduction for Nanoscale Circuits

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Leakage Power Analysis and Reduction for Nanoscale Circuits LEAKAGE POWER ANALYSIS AND REDUCTION FOR NANOSCALE CIRCUITS LEAKAGE CURRENT IN THE NANOMETER REGIME HAS BECOME A SIGNIFICANT PORTION OF POWER DISSIPATION IN CMOS CIRCUITS AS THRESHOLD VOLTAGE, CHANNEL LENGTH, AND GATE OXIDE THICKNESS SCALE DOWNWARD. VARIOUS TECHNIQUES ARE AVAILABLE TO REDUCE LEAKAGE POWER IN HIGH- PERFORMANCE SYSTEMS. CMOS devices have scaled down- ponents becomes equally important in ward aggressively in each technology genera- nanoscaled devices.2 Hence, the relative mag- tion to achieve higher integration density and nitudes of the leakage components play a performance. However, leakage current has major role in low-leakage logic design.3 increased drastically with technology scaling In the nanometer regime, leakage currents Amit Agarwal and become a major contributor to the total make up a significant portion of the total IC power. Different leakage mechanisms con- power consumption in high-performance dig- Intel Corp. tribute to the total leakage in a device. As Fig- ital circuits. Because high-performance systems ure 1 shows, the three major types of leakage must work within a predefined power budget, mechanisms are leakage power reduces the available power, Saibal Mukhopadhyay impacting performance. It also contributes to • subthreshold, the power consumption during standby oper- Arijit Raychowdhury • gate, and ation, reducing battery life. Hence, designers • reverse-biased, drain- and source-sub- require techniques that reduce leakage power Kaushik Roy strate junction band-to-band-tunneling while maintaining high performance. More- (BTBT).1 over, as different leakage components become Purdue University more important with technology scaling, each With technology scaling, each of these leak- leakage reduction technique needs reevalua- age components increases drastically, result- tion in scaled technologies where subthresh- Chris H. Kim ing in an increase in the total leakage current. old conduction is not the only leakage The increase in different leakage compo- mechanism. Designers will require new, low- University of Minnesota nents with technology scaling has two major power circuit techniques to reduce total leak- implications in leakage estimation and low- age in high-performance nanoscale circuits. power logic design. First, these increases add up to a dramatic increase in total leakage. Leakage components More importantly, each of the leakage com- In addition to the three major leakage com- 68 Published by the IEEE Computer Society 0272-1732/06/$20.00 © 2006 IEEE Subthreshold Gate leakage −06 leakage 10 Gate − 10 07 Subtreshold Gate Junction BTBT −08 Source Drain 10 − 10 09 n+ n+ − 10 10 − 10 11 Reverse-biased − junction BTBT 10 12 − 10 13 Leff = 25 nm Leff = 50 nm Leff = 90 nm Bulk Figure 2. Contribution of different leakage components in NMOS devices4 at different technology generations. The Figure 1. Major leakage components in a transistor. leakage values are extracted using device simulation in Medici. VDD values are chosen following the ITRS guidelines (0.7 V at 25 nm, 0.9 V at 50 nm, and 1.2 V at 90 nm). ponents, there are others, such as gate-induced drain leakage (GIDL) and punch-through cur- rent.But those components are not very serious × −07 − 10 in normal modes of operations. GIDL will be 10 04 7 Gate of concern in cases where VGD < 0 (VGD, volt- BTBT 6 age across the gate and the drain of the transis- Leff = 25 nm Subthreshold tor), and pass-gate logic is definitely a part of it. − 5 10 06 However, for the range of VDD suggested by the L = 50 nm eff 4 International Technology Roadmap for Semicon- ductors, we observe that maximum negative 3 Current (A) − Current (A) V = −V , and it does not result in any sig- 10 08 GD DD 2 nificant GIDL. As technology scales downward, the supply 1 voltage must also scale down to reduce − 10 10 0 dynamic power and maintain reliability. How- 1.1 nm 1.3 nm 1.2 nm 1.4 nm Doping-1 Doping-2 T ever, this requires the scaling of Vth to main- (a) ox (b) tain a reasonable gate overdrive. Vth scaling and reduction, because of short-channel Figure 3. Variation of different leakage components with technology genera- effects (SCEs) such as drain-induced barrier- tion and oxide thickness (a), and doping profile (b). Doping-1 has a stronger lowering (DIBL),2 result in an exponential halo profile than Doping-2. We extracted leakage values using device simu- increase in subthreshold current. To control lation in Medici. We chose VDD as 0.7 V at 25 nm and 0.9 V at 50 nm. the SCE and to increase the transistor drive strength, oxide thickness must also become thinner in each technology generation. helps to control the short-channel effect. The Aggressive scaling of oxide thickness results in high doping density near the source- and a high direct-tunneling current through the drain-substrate junctions causes a significant- transistor’s gate insulator.2 On the other hand, ly large BTBT current through these junctions scaled devices require higher substrate doping under high reversed bias.2 We conclude that densities and the application of “halo” pro- each of the leakage components increases with files (implants of a high doping region near technology scaling, as Figure 2 shows. the source and drain junctions of the chan- Figure 3 shows the different leakage com- nel) to reduce the width of the depletion ponents of NMOS devices with physical gate region for the source- and drain-substrate lengths of 25 and 50 nm.4 The plot also shows junctions.2 A narrower depletion region width the results at different oxide thicknesses based MARCH–APRIL 2006 69 POWER REDUCTION the different leakage current components have − × 10 08 different temperature dependences. Sub- 1.5 Gate threshold current is governed by the carrier dif- Junction BTBT fusion that increases with an increase of Subthreshold temperature. Since tunneling probability of an Total m) 1.0 electron through a potential barrier does not μ depend directly on temperature, the gate and the junction band-to-band tunneling are less sensitive to temperature variations. However, Current (A/ 0.5 increasing temperature reduces silicon’s band gap, which is the barrier height for tunneling in BTBT. Hence, the junction BTBT should 0 increase with an increase in temperature. 300 320 340 360 380 400 Figure 4 shows the effect of temperature Temperature (K) variation on individual leakage component of the previously mentioned 25-nm NMOS Figure 4. Simulation result for variation of different leakage device based on the device simulation. In Fig- components with temperature for NMOS device of ure 4, we observe that the subthreshold leak- 4 Leff = 25 nm. age increases exponentially with temperature, the junction BTBT increases slowly with tem- perature, and the gate leakage is almost inde- on device simulation. We varied only the oxide pendent of temperature variation. Figure 4 thickness in the simulations for a particular shows that for this particular NMOS device, technology node (doping remained constant). at T = 300 K (a possible temperature in the The gate and subthreshold leakages correlate standby mode) the gate leakage is the domi- strongly with oxide thickness; a high oxide nant leakage component. However, the sub- thickness results in low gate leakage. Although threshold and BTBT leakages become long-channel MOSFET theory maintains that dominant at T = 400 K (a possible tempera- higher oxide thickness helps to increase the ture in active mode). Hence, it can be con- threshold voltage, it worsens the short-chan- cluded that the individual leakage components nel effect.2 If the short-channel effect is not and the total leakage depend strongly on tem- very high (as in the 50 nm device in Figure 3a), perature (or mode of operation). increasing Tox might reduce the subthreshold It is evident that in nanoscaled devices all leakage. However, in a nanoscale device where of the different leakage components become SCE is extremely severe (in the 25 nm device important and their magnitude depends in the present case), an increase in the oxide strongly on the device structure, doping pro- thickness will increase the subthreshold leak- file, and temperature. age (Figure 3a). Similarly, the subthreshold leakage and the junction BTBT are strongly Circuit techniques to reduce leakage in logic coupled through the doping profile. Since circuits are mostly designed for the Figure 3b shows the different leakage com- highest performance—to satisfy overall system ponents of a 25-nm device at different dop- cycle time requirements, for example—they ing profiles (oxide thickness and VDD typically consist of large gates, highly parallel remained constant). A strong “halo” doping architectures with logic duplication. The leak- reduces the subthreshold current but results age power consumption is substantial for such in a high BTBT. Reducing the halo strength circuits. However, not every application lowers the BTBT, but increases subthreshold requires a fast circuit to operate at the highest current considerably. We conclude that the performance level all the time. Modules in magnitude of leakage components and their which computation is bursty (such as certain relative dominance with respect to each other functional units or cache sections) are often depend strongly on device geometry and dop- idle. Thus, there is an opportunity to reduce ing profile. the leakage power consumed by such circuits. The basic physical mechanisms governing Researchers have proposed different circuit 70 IEEE MICRO techniques to reduce leakage Table 1. Circuit techniques to reduce leakage. energy without impacting performance by using this Runtime techniques slack. In Table 1, we catego- Design time techniques Standby leakage reduction Active leakage reduction rize these techniques based on Dual Vth Natural Stacking DVTS when and how they use the Sleep Transistor available timing slack. Dual FBB/RBB Vth statically assigns high Vth to some transistors in the noncritical paths at design 15,000 time to reduce leakage cur- Single low Vth Single high V rent.
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