electronics

Article Electrical Characteristics of Bulk FinFET According to Spacer Length

Jinsu Park 1, Jaemin Kim 1, Sanchari Showdhury 1, Changhwan Shin 1 , Hwasung Rhee 2, Myung Soo Yeo 2, Eun-Chel Cho 1,* and Junsin Yi 1,*

1 College of Information and Communication Engineering, Sungkyunkwan University, Suwon-Si 16419, Korea; [email protected] (J.P.); [email protected] (J.K.); [email protected] (S.S.); [email protected] (C.S.) 2 Technology Quality and Reliability Foundry Division, Samsung Electronics Co. LTD., Suwon-Si 16677, Korea; [email protected] (H.R.); [email protected] (M.S.Y.) * Correspondence: [email protected] (E.-C.C.); [email protected] (J.Y.)



Received: 9 June 2020; Accepted: 6 August 2020; Published: 11 August 2020


Abstract: This paper confirms that the electrical characteristics of FinFETs such as the on/off ratio, drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) can be improved by optimizing the FinFET spacer structure. An operating voltage that can maintain a life of 10 years or more when hot-carrier injection is extracted. An excellent on/off ratio (7.73 107) and the best SS value × were found at 64.29 mV/dec with a spacer length of 90 nm. Under hot carrier-injection conditions, the supply voltages that meet the 10-year lifetime condition are 1.11 V, 1.18 V, and 1.32 V for spacer lengths of 40 nm, 80 nm, and 120 nm, respectively. This experiment confirmed that, even at low drain voltages, the shorter is the spacer length, the greater is the deterioration. However, this increasing maximum operating voltage is very small when compared to the increase in the driving voltage required to achieve similar performance when the spacer length is increased; therefore, the effective life is expected to decrease. The results indicate that structural optimization must be performed to increase the driving current of the FinFET and prevent degradation of the analog performance.

Keywords: metal-oxide-semiconductor field-effect transistor; fin field-effect transistor; short-channel effects; drain-induced barrier lowering; self-heating effect

1. Introduction The performance of semiconductors is improved by scaling the gate length up to 10–15 nm [1–3]. However, as the distance between source and drain regions decreases, the electric field in the channel increases, while the ability of the gate to control the channel region decreases. This is known as “short channel effect (SCE)”. If the gate length is reduced more than 10–15 nm, it causes source-to-drain direct tunneling, resulting in the degradation of SCE. Previous research work already showed the limitations of the device scaling, and the Drain-Induced-Barrier-Lowering (DIBL) due to SCE [4–11]. As a result, multi-gate FinFETs were introduced to reduce the leakage current and improve the gate controllability of the transistor channel. The FinFET structure also reduces the occurrence of gate-oxide traps and gate critical paths, owing to the reduction of the hot-carrier effect caused by lightly-doped drain (LDD) formation, resulting in a decrease in the gate-induced drain leakage (GIDL). In the off state, the effective channel length is larger than the physical gate length due to the undoped spacer regions. In the on state, the effective channel length is equal to the physical gate length of the device [12,13]. While the introduction of spacer improves the short-channel performance of the devices, drive current is reduced due to higher series resistance in the spacer regions. Furthermore, the parasitic capacitance increases with the increased device transconductance, causing no improvement in unit-gain frequency.

Electronics 2020, 9, 1283; doi:10.3390/electronics9081283 www.mdpi.com/journal/electronics Electronics 2020, 9, x FOR PEER REVIEW 2 of 9

Electronicsin the spacer2020, 9, 1283regions. Furthermore, the parasitic capacitance increases with the increased device2 of 7 transconductance, causing no improvement in unit-gain frequency. In this work, we tried to solve these problems by optimizing the spacer structure of the FinFET. In this work, we tried to solve these problems by optimizing the spacer structure of the We present a bulk-Si N-channel FinFET device (bulk N-FinFET) that has desirable transistor FinFET. We present a bulk-Si N-channel FinFET device (bulk N-FinFET) that has desirable transistor characteristics and competitive short-channel performance. The important parameters in bulk characteristics and competitive short-channel performance. The important parameters in bulk N-FinFETs, including DIBL, SS, drive current, and S/D subthreshold off-state leakage current, are N-FinFETs, including DIBL, SS, drive current, and S/D subthreshold off-state leakage current, are combined to reflect the overall performance of the device and provide a criterion for the design of combined to reflect the overall performance of the device and provide a criterion for the design of innovative devices. innovative devices.

2.2. Device Device Structure Structure and and Simulation Simulation Setup Setup AA top-view top-view SEM SEM imageimage of the bulk bulk FinFET FinFET used used for for the the measurement measurement is shown is shown in Figure in Figure 1a.1 Thea. important geometrical parameters of a FinFET are defined in Figure 1b, namely the height (Hfin), The important geometrical parameters of a FinFET are defined in Figure1b, namely the height (H fin), width (Wfin), transistor length (L), and spacer length (LSD). The device design parameters of the width (Wfin), transistor length (L), and spacer length (LSD). The device design parameters of the FinFETFinFET are are summarized summarized in in Table Table1. These1. These devices devices feature feature a high-k a high-k gate gate dielectric dielectric (2.3-nm (2.3-nm HfSiON HfSiON on aon 1-nma 1-nm interfacial interfacial oxide) oxide) and and 100 100 nm ofnm polycrystalline of polycrystalline silicon silicon on top on of top a 5-nmof a 5-nm TiNmetal TiN metal gate. Thegate. S The/D accessS/D access region region is formed is formed by the selectiveby the selective epitaxial epitaxial growth ofgrowth Si on theof Si source on the and source drain and areas, drain followed areas, byfollowed NiPt silicidation. by NiPt silicidation.

(a) (b)

FigureFigure 1. 1.(a )(a Top-view) Top-view SEM SEM image image of the of bulk the FinFET;bulk FinFET; and (b and) definition (b) definition of fin height, of fin fin height, width, fin channel width, length,channel and length, pitch and in FinFETs. pitch in FinFETs.

TableTable 1. 1.Device Device structure structure parameters parameters of of FinFETs. FinFETs.

Device ParametersDevice Parameters Value Value Gate lengthGate (L) length (L) 70 70nm nm Fin widthFin (W finwidth) (Wfin) 40 40nm nm Fin height (Hfin) 30 nm Fin height (Hfin) 30 nm Number of fins 5 Fin pitchNumber of fins 200 5 nm Spacer length (LSD)Fin pitch 200 40~100 nm nm Spacer length (LSD) 40~100 nm To understand the dependence of the electrical properties of a bulk FinFET on the spacer length, To understand the dependence of the electrical properties of a bulk FinFET on the spacer 3D TCAD simulations were performed using Atlas TCAD. For device simulation, along with the length, 3D TCAD simulations were performed using Atlas TCAD. For device simulation, along with inversion layer mobility models of Lombardi CVT, SRH, and Auger recombination, LAT.TEMP models the inversion layer mobility models of Lombardi CVT, SRH, and Auger recombination, LAT.TEMP were also included. The S/D regions were N-doped at the concentration 1 1021 cm 3 and the channel models were also included. The S/D regions were N-doped at the concentration× − 1×10 cm−3 and regions were P-doped at the concentration 1 1017 cm 3. the channel regions were P-doped at the concentration× − 1×10 cm−3. After applying voltages of 0.1 and 1 V to the drain, the DC simulation of a five-fin FinFET structure After applying voltages of 0.1 and 1 V to the drain, the DC simulation of a five-fin FinFET was performed, and the on/off current, DIBL, SS, and lattice temperatures were extracted using the structure was performed, and the on/off current, DIBL, SS, and lattice temperatures were extracted Ids–Vgs graph for changes in the spacer length. using the Ids–Vgs graph for changes in the spacer length.

Electronics 2020, 9, x FOR PEER REVIEW 3 of 9

3. Results and Discussion Electronics 2020, 9, 1283 3 of 7 3.1. Off-State Leakage Current Electronics 2020, 9, x FOR PEER REVIEW 3 of 9 3. ResultsFigure and2 shows Discussion the transfer curve and on/off current change according to the spacer length change in3. Resultsa bulk andN-FinFET. Discussion As the spacer length increases, the source and drain resistances also increase.3.1. Off-State The Leakageincrease Current in source resistance causes the degradation in on-state current. For low-power 3.1. Off-State Leakage Current operation,Figure the2 shows spacer the length transfer should curve be and designed on /off tocurrent be as short change as accordingpossible. However, to the spacer when length the changespacer lengthin a bulk becomes N-FinFET.Figure shorter 2 shows As than the the spacer 60transfer nm, length thecurve effective and increases, on/off channel cu therrent source length change and decreasesaccording drain resistancestorapidly the spacer resulting alsolength increase. in the increase changein leakage in a bulkcurrent. N-FinFET. Therefore, As the whenspacer thelength spacer increases, length the is source 80 nm, and the drain on/off resistances ratio will also be the The increaseincrease. insource The increase resistance in source causes resistance the degradation causes the degradation in on-state in on-state current. current. For low-power For low-power operation, highest, at 7.73 × 10. Further increase in spacer length increases the source and drain resistance the spaceroperation, length the should spacer belength designed should be to designed be as short to be asas short possible. as possible. However, However, when when the the spacer spacer length andbecomes the increasedlength shorter becomes thansource shorter 60 resistance nm, than the 60 eff causesnm,ective the channeltheeffective degradation lengthchannel decreaseslength in on-state decreases rapidly current. rapidly resulting resulting in in the the increase in leakageincrease current. in leakage Therefore, current. when Therefore, the spacerwhen the length spaceris length 80 nm, is 80 the nm, on the/o ffon/offratio ratio will will be be the the highest, at 7.73 highest,107. Further at 7.73 × increase 10 . Further in spacerincrease lengthin spacer increases length increases the source the source and drainand drain resistance resistance and the ×and the increased source resistance causes the degradation in on-state current. increased source resistance causes the degradation in on-state current.

(a) (a) (b)( b)

FigureFigure 2. 2.Figure ((aa)) Transfer Transfer 2. (a) Transfer curve; curve; curve; and and and( (bb)) on/off( onb) /on/offoff currentcurrent current characteristicscharacteristics characteristics of of ofN-type N-type N-type bulk bulk bulk FinFET FinFET FinFET according according according to to to spacer length. spacerspacer length. length. Figure 3 shows the changes in the DIBL and SS with changes in the spacer length. As the FigureFigure 33 shows shows the the changes changes in thein the DIBL DIBL and SSand with SS changeswith changes in the spacerin the length.spacer Aslength. the length As the of length of the spacer increases, the effective channel length increases. In addition, the length of the lengththe spacer ofspace-charge the increases, spacer region increases, the e ffformedective the at channel theeffective interface length channe between increases.l lengththe channel In increases. addition, and drain In the also addition, length increases, of the the and, length space-charge thus, of the space-chargeregion formedthe DIBL region at decreases. the formed interface On atthe the betweenother interface hand, the as between the channel size of the andthe channel electric drain field alsoand from drain increases, the also drain increases, and, to the thus, channel and, the thus, DIBL thedecreases. DIBLregion decreases. On decreases the other On and the hand, the other total as hand, volume the size as of the ofthe the sizedepletion electric of the region electric field increases, from field the itfrom is drain causing the to drain the the problem channelto the ofchannel region regiondecreases decreasesan and increase the and totalof the the volume SS. total As indicatedvolume of the depletion inof Table the depletion 2, region when increases,the region spacer increases,length it is causing is 90 itnm, is the thecausing problem lowest the SS of valueproblem an increase of of 64.29 mV/V is obtained. anof theincrease SS. As of indicated the SS. As in indicated Table2, when in Table the spacer 2, when length the spacer is 90 nm, length the lowestis 90 nm, SS valuethe lowest of 64.29 SS mVvalue/V ofis 64.29 obtained. mV/V is obtained.

Figure 3. Drain-induced barrier lowering and sub-threshold slope characteristics comparison of N-type

bulk FinFET according to spacer length. Electronics 2020, 9, x FOR PEER REVIEW 4 of 9

Figure 3. drain-induced barrier lowering and sub-threshold slope characteristics comparison of N-type bulk FinFET according to spacer length.

Table 2. Electrical properties of bulk FinFET according to spacer length. Electronics 2020, 9, 1283 4 of 7 LSD (nm) On/Off Ration DIBL (mV/V) SS (mV/dec) 40 × 5 130.70 107.24 Table 2. Electrical properties3.18 10 ofbulk FinFET according to spacer length. 6 50 2.67 × 10 78.19 78.08 LSD (nm) On/Off Ration7 DIBL (mV/V) SS (mV/dec) 60 3.20 × 10 36.40 70.17 40 3.18 105 130.70 107.24 × 7 50 70 2.676.91 10× 6 10 19.4778.19 67.30 78.08 × 60 3.20 107 7 36.40 70.17 80 7.73× × 10 18.68 64.79 70 6.91 107 19.47 67.30 × 7 80 90 7.736.05 10× 7 10 18.4118.68 64.29 64.79 × 90 6.05 107 7 18.41 64.29 100 3.88× × 10 17.64 66.82 100 3.88 107 17.64 66.82 × 3.2. Impact Ionization 3.2. Impact Ionization Hot carriers produced by impact ionization are important components that degrade the device Hot carriers produced by impact ionization are important components that degrade the device reliability [14–16]. Hot carriers, which have sufficient energy to pass through the gate insulator, reliability [14–16]. Hot carriers, which have sufficient energy to pass through the gate insulator, impact impact the Si–SiO2 interface, significantly impairing the transistor performance. the Si–SiO interface, significantly impairing the transistor performance. The degree2 of device damage due to hot carriers is generally analyzed in terms of the substrate The degree of device damage due to hot carriers is generally analyzed in terms of the substrate current. Figure 4a shows the substrate current according to the spacer-length change. When the current. Figure4a shows the substrate current according to the spacer-length change. When the spacer spacer length shortens below 60 nm, the substrate current increases rapidly because of impact length shortens below 60 nm, the substrate current increases rapidly because of impact ionization. ionization. The hot carriers generated by impact ionization further accelerate the deterioration of the The hot carriers generated by impact ionization further accelerate the deterioration of the device by device by increasing the lattice temperature. Figure 4b shows the correlation between the substrate increasing the lattice temperature. Figure4b shows the correlation between the substrate current and current and lattice temperature, according to the spacer-length change. The mechanism behind SHE lattice temperature, according to the spacer-length change. The mechanism behind SHE is the impact is the impact ionization that occurs at the junction between the P-doped and N-doped regions. ionization that occurs at the junction between the P-doped and N-doped regions.

(a) (b)

FigureFigure 4.4. ((a)) SubstrateSubstrate currentcurrent versusversus gategate voltagevoltage characteristics;characteristics; and ((bb)) comparisoncomparison ofof substratesubstrate currentcurrent andand latticelattice temperaturetemperature ofof N-typeN-type bulkbulk FinFETFinFET accordingaccording toto spacerspacer length.length.

IfIf aa positivepositive bias bias is is applied applied to theto then-doped n-doped region region (i.e., (i.e., drain drain region), region), the energy the energy band in band the N-type in the materialN-type material will be lower will be than lower that inthan the that steady in the state. steady On applying state. On a moreapplying positive a more bias, positive the energy bias, band the inenergy the N-type band regionin the N-type will be lowerregion [ 17will]. Anbe increasedlower [17] bias. An attracts increased electrons, bias attracts which areelectrons, minority which carriers are inminority the P-type carriers region. in Suchthe P-type carriers region. are accelerated Such carr byiers the are positive accelerated bias, and by thethe incoming positive electronsbias, and willthe collideincoming with electrons the other will ions. collide Thus, with they willthe createother anions electron-hole. Thus, they pair will (EHP). create The an holeselectron-hole generated pair at this(EHP). time The pass holes through generated the substrate at this time and partlypass thro flowugh to the gatesubstrate to form and the partly gate current.flow to the Therefore, gate to when the impact ionization increases, the substrate current will increase.

3.3. Hot-Carrier Degradation Figure5 shows a graph of the change in transconductance over time after channel hot-electron injection into real FinFET devices with different spacer lengths. A voltage ranging from 1.2 V to 2.0 V − Electronics 2020, 9, x FOR PEER REVIEW 6 of 9

3.3. Hot-Carrier Degradation Figure 5 shows a graph of the change in transconductance over time after channel hot-electron Electronics 2020, 9, 1283 5 of 7 injection into real FinFET devices with different spacer lengths. A voltage ranging from 1.2 V to −2.0 V was applied between the drain and source, and the same gate voltage was applied. The stress wasapplication applied betweentime was the drainincreased and source,from and100 thes to same 3800 gate s. voltage When wasthe applied.spacer Thelength stress is applicationsmall, the timetransconductance was increased deteriorates from 100 ssignificantly to 3800 s. Whenat a small the spacerdrain voltage. length isAs small, the spacer the transconductance length increases, deterioratesthe deterioration significantly also increases at a small at drainlarge voltage.drain volt Asages. the spacer As observed length increases,previously, the even deterioration at low drain also increasesvoltages, atwhen large the drain spacer voltages. length As is observed40 nm, impact previously, ionization even atoccurs low drainbecause voltages, of the wheneffect theof a spacer large lengthelectric is field. 40 nm, Thus, impact a very ionization fast deterioration occurs because rate of is the observed. effect of aHowever, large electric if a field.high Thus,drain avoltage very fast is deteriorationapplied, deterioration rate is observed. due to impact However, ionization if a high occurs drain voltageeven in is a applied,FinFET with deterioration 100-nm spacer due to impactlength. ionizationIn addition, occurs it can even be interpreted in a FinFET that with more 100-nm deterior spaceration length. occurs Inat addition,high voltages it can because be interpreted the electron that moreinterface deterioration trap area widens. occurs at high voltages because the electron interface trap area widens.

(a) (b)

(c)

FigureFigure 5.5. TransconductanceTransconductance degradation for didifferentfferent spacerspacer lengths under the stress conditions of: ((aa)) LSDLSD == 40 nm; (b) LSD = 8080 nm; nm; and ( c)) LSD LSD = 120120 nm nm.

ThisThis trendtrend isis clearlyclearly presentedpresented inin FigureFigure6 6,, which which shows shows the the lifetime lifetime of of the the devices devices with with HCE HCE degradation.degradation. We considerconsider the lifetimelifetime asas thethe timetime atat whichwhich thethe devicedevice showsshows 10%10% transconductancetransconductance degradation.degradation. The The supply supply voltage voltage which which meets meets the the 10-year 10-year lifetime lifetime condition condition at ata spacer a spacer length length of of40 40nm nm is 1.11 is 1.11 V; that V; that for fora spacer a spacer length length of 80 of nm 80 is nm 1.18 is V; 1.18 and V; that and for that a spacer for a spacer length lengthof 120 ofnm 120 is 1.32 nm V. is 1.32As a V. result As a resultof this of experiment, this experiment, it is itconfirmed is confirmed that, that, the the shorter shorter is isthe the spacer, spacer, the the easier easier is thethe deterioration, even at low drain voltages. However, this increase is very small when compared to the increase in the driving voltage required to achieve a similar performance when the spacer length is increased; thus, the effective life is expected to decrease. Electronics 2020, 9, x FOR PEER REVIEW 7 of 9

deterioration, even at low drain voltages. However, this increase is very small when compared to the increase in the driving voltage required to achieve a similar performance when the spacer length is Electronics 2020, 9, 1283 6 of 7 increased; thus, the effective life is expected to decrease.

(a) (b)

(c)

Figure 6. Device lifetime for different stress bias conditions with different spacer lengths under the Figure 6. Device lifetime for different stress bias conditions with different spacer lengths under the stress conditions obtained by extrapolation with Figure 5 of: (a) LSD = 40 nm; (b) LSD = 80 nm; and stress conditions obtained by extrapolation with Figure5 of: ( a) LSD = 40 nm; (b) LSD = 80 nm; and ((cc)) LSDLSD= = 120120 nm.nm.

4.4. ConclusionsConclusions AccordingAccording to to Moore’s Moore’s Law, Law, the channelthe channel length length of the of transistor the transistor is reducing is reducing continuously; continuously; however, duehowever, to problems due to such problems as deterioration such as deterioration of the subthreshold of the subthreshold characteristics characteristics of the transistor of the as atransistor result of theas deepeninga result of ofthe the deepening SCE, it is no of longer the SCE, possible it is tono expect longer an improvementpossible to expect in performance an improvement because ofin aperformance reduction in because device size.of a reduction To improve in thedevice performance size. To improve of the transistor, the performance a device of having the transistor, a 3D gate a structuredevice having in which a 3D a transistorgate structure structure in which is changed, a transistor rather structure than simply is changed, scaling therather channel than length,simply wasscaling developed. the channel length, was developed. InIn thisthis study,study, itit waswas confirmedconfirmed thatthat thethe characteristicscharacteristics suchsuch asas onon/off/off ratio,ratio, DIBL,DIBL, andand SSSS werewere improvedimproved throughthrough optimizationoptimization ofof thethe FinFETFinFET spacerspacer structure.structure. InIn addition,addition, anan operatingoperating voltagevoltage thatthat couldcould maintain a a life life of of 10 10 years years or or more more under under hot-carrier hot-carrier injection injection conditions conditions was was extracted. extracted. As Ascould could be beseen seen from from the the results, results, structural structural optimiza optimizationtion was was required required to to increase increase the drive currentcurrent ofof thethe FinFETFinFET andand preventprevent degradationdegradation ofof the the analog analog performance. performance.

AuthorAuthor Contributions:Contributions:Conceptualization, Conceptualization, J.P.; J.P.; methodology, methodology, J.P. J.P. and and J.K.; J.K.; software, software, J.P.; J.P.; resources, resources, J.P. and J.P. C.S.;and writing—originalC.S.; writing—original draft preparation,draft preparat J.P.;ion, writing—review J.P.; writing—review and editing, andJ.P., edit S.S.,ing, E.-C.C.,J.P., S.S., and E.-C.C., J.Y.; supervision, and J.Y.; E.-C.C, and J.Y.; and funding acquisition, M.S.Y. and H.R. All authors have read and agreed to the published version of the manuscript. Funding: This work was supported by Korea Institute for Advancement of Technology (No. P0012453) and Samsung Electronics (No. s-2019-2141-026). Electronics 2020, 9, 1283 7 of 7

Acknowledgments: This research was funded and conducted under pthe Competency Development Program for Industry Specialistsy of the Korean Ministry of Trade, Industry and Energy (MOTIE), operated by Korea Institute for Advancement of Technology (KIAT). (No. P0012453, Next-generation Display Expert Training Project for Innovation Process and Equipment, Materials Engineers.) Conflicts of Interest: The authors declare no conflict of interest.

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