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Electrical Characteristics of Bulk Finfet According to Spacer Length

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Electrical Characteristics of Bulk Finfet According to Spacer Length electronics Article Electrical Characteristics of Bulk FinFET According to Spacer Length Jinsu Park 1, Jaemin Kim 1, Sanchari Showdhury 1, Changhwan Shin 1 , Hwasung Rhee 2, Myung Soo Yeo 2, Eun-Chel Cho 1,* and Junsin Yi 1,* 1 College of Information and Communication Engineering, Sungkyunkwan University, Suwon-Si 16419, Korea; [email protected] (J.P.); [email protected] (J.K.); [email protected] (S.S.); [email protected] (C.S.) 2 Technology Quality and Reliability Foundry Division, Samsung Electronics Co. LTD., Suwon-Si 16677, Korea; [email protected] (H.R.); [email protected] (M.S.Y.) * Correspondence: [email protected] (E.-C.C.); [email protected] (J.Y.) Received: 9 June 2020; Accepted: 6 August 2020; Published: 11 August 2020 Abstract: This paper confirms that the electrical characteristics of FinFETs such as the on/off ratio, drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) can be improved by optimizing the FinFET spacer structure. An operating voltage that can maintain a life of 10 years or more when hot-carrier injection is extracted. An excellent on/off ratio (7.73 107) and the best SS value × were found at 64.29 mV/dec with a spacer length of 90 nm. Under hot carrier-injection conditions, the supply voltages that meet the 10-year lifetime condition are 1.11 V, 1.18 V, and 1.32 V for spacer lengths of 40 nm, 80 nm, and 120 nm, respectively. This experiment confirmed that, even at low drain voltages, the shorter is the spacer length, the greater is the deterioration. However, this increasing maximum operating voltage is very small when compared to the increase in the driving voltage required to achieve similar performance when the spacer length is increased; therefore, the effective life is expected to decrease. The results indicate that structural optimization must be performed to increase the driving current of the FinFET and prevent degradation of the analog performance. Keywords: metal-oxide-semiconductor field-effect transistor; fin field-effect transistor; short-channel effects; drain-induced barrier lowering; self-heating effect 1. Introduction The performance of semiconductors is improved by scaling the gate length up to 10–15 nm [1–3]. However, as the distance between source and drain regions decreases, the electric field in the channel increases, while the ability of the gate to control the channel region decreases. This is known as “short channel effect (SCE)”. If the gate length is reduced more than 10–15 nm, it causes source-to-drain direct tunneling, resulting in the degradation of SCE. Previous research work already showed the limitations of the device scaling, and the Drain-Induced-Barrier-Lowering (DIBL) due to SCE [4–11]. As a result, multi-gate FinFETs were introduced to reduce the leakage current and improve the gate controllability of the transistor channel. The FinFET structure also reduces the occurrence of gate-oxide traps and gate critical paths, owing to the reduction of the hot-carrier effect caused by lightly-doped drain (LDD) formation, resulting in a decrease in the gate-induced drain leakage (GIDL). In the off state, the effective channel length is larger than the physical gate length due to the undoped spacer regions. In the on state, the effective channel length is equal to the physical gate length of the device [12,13]. While the introduction of spacer improves the short-channel performance of the devices, drive current is reduced due to higher series resistance in the spacer regions. Furthermore, the parasitic capacitance increases with the increased device transconductance, causing no improvement in unit-gain frequency. Electronics 2020, 9, 1283; doi:10.3390/electronics9081283 www.mdpi.com/journal/electronics Electronics 2020, 9, x FOR PEER REVIEW 2 of 9 Electronicsin the spacer2020, 9, 1283regions. Furthermore, the parasitic capacitance increases with the increased device2 of 7 transconductance, causing no improvement in unit-gain frequency. In this work, we tried to solve these problems by optimizing the spacer structure of the FinFET. In this work, we tried to solve these problems by optimizing the spacer structure of the We present a bulk-Si N-channel FinFET device (bulk N-FinFET) that has desirable transistor FinFET. We present a bulk-Si N-channel FinFET device (bulk N-FinFET) that has desirable transistor characteristics and competitive short-channel performance. The important parameters in bulk characteristics and competitive short-channel performance. The important parameters in bulk N-FinFETs, including DIBL, SS, drive current, and S/D subthreshold off-state leakage current, are N-FinFETs, including DIBL, SS, drive current, and S/D subthreshold off-state leakage current, are combined to reflect the overall performance of the device and provide a criterion for the design of combined to reflect the overall performance of the device and provide a criterion for the design of innovative devices. innovative devices. 2.2. Device Device Structure Structure and and Simulation Simulation Setup Setup AA top-view top-view SEM SEM imageimage of the bulk bulk FinFET FinFET used used for for the the measurement measurement is shown is shown in Figure in Figure 1a.1 Thea. important geometrical parameters of a FinFET are defined in Figure 1b, namely the height (Hfin), The important geometrical parameters of a FinFET are defined in Figure1b, namely the height (H fin), width (Wfin), transistor length (L), and spacer length (LSD). The device design parameters of the width (Wfin), transistor length (L), and spacer length (LSD). The device design parameters of the FinFETFinFET are are summarized summarized in in Table Table1. These1. These devices devices feature feature a high-k a high-k gate gate dielectric dielectric (2.3-nm (2.3-nm HfSiON HfSiON on aon 1-nma 1-nm interfacial interfacial oxide) oxide) and and 100 100 nm ofnm polycrystalline of polycrystalline silicon silicon on top on of top a 5-nmof a 5-nm TiNmetal TiN metal gate. Thegate. S The/D accessS/D access region region is formed is formed by the selectiveby the selective epitaxial epitaxial growth ofgrowth Si on theof Si source on the and source drain and areas, drain followed areas, byfollowed NiPt silicidation. by NiPt silicidation. (a) (b) FigureFigure 1. 1.(a )(a Top-view) Top-view SEM SEM image image of the of bulk the FinFET;bulk FinFET; and (b and) definition (b) definition of fin height, of fin fin height, width, fin channel width, length,channel and length, pitch and in FinFETs. pitch in FinFETs. TableTable 1. 1.Device Device structure structure parameters parameters of of FinFETs. FinFETs. Device ParametersDevice Parameters Value Value Gate lengthGate (L) length (L) 70 70nm nm Fin widthFin (W finwidth) (Wfin) 40 40nm nm Fin height (Hfin) 30 nm Fin height (Hfin) 30 nm Number of fins 5 Fin pitchNumber of fins 2005 nm Spacer length (LSD)Fin pitch 200 40~100 nm nm Spacer length (LSD) 40~100 nm To understand the dependence of the electrical properties of a bulk FinFET on the spacer length, To understand the dependence of the electrical properties of a bulk FinFET on the spacer 3D TCAD simulations were performed using Atlas TCAD. For device simulation, along with the length, 3D TCAD simulations were performed using Atlas TCAD. For device simulation, along with inversion layer mobility models of Lombardi CVT, SRH, and Auger recombination, LAT.TEMP models the inversion layer mobility models of Lombardi CVT, SRH, and Auger recombination, LAT.TEMP were also included. The S/D regions were N-doped at the concentration 1 1021 cm 3 and the channel models were also included. The S/D regions were N-doped at the concentration× − 1×10 cm−3 and regions were P-doped at the concentration 1 1017 cm 3. the channel regions were P-doped at the concentration× − 1×10 cm−3. After applying voltages of 0.1 and 1 V to the drain, the DC simulation of a five-fin FinFET structure After applying voltages of 0.1 and 1 V to the drain, the DC simulation of a five-fin FinFET was performed, and the on/off current, DIBL, SS, and lattice temperatures were extracted using the structure was performed, and the on/off current, DIBL, SS, and lattice temperatures were extracted Ids–Vgs graph for changes in the spacer length. using the Ids–Vgs graph for changes in the spacer length. Electronics 2020, 9, x FOR PEER REVIEW 3 of 9 3. Results and Discussion Electronics 2020, 9, 1283 3 of 7 3.1. Off-State Leakage Current Electronics 2020, 9, x FOR PEER REVIEW 3 of 9 3. ResultsFigure and2 shows Discussion the transfer curve and on/off current change according to the spacer length change in3. Resultsa bulk andN-FinFET. Discussion As the spacer length increases, the source and drain resistances also increase.3.1. Off-State The Leakageincrease Current in source resistance causes the degradation in on-state current. For low-power 3.1. Off-State Leakage Current operation,Figure the2 shows spacer the length transfer should curve be and designed on /off tocurrent be as short change as accordingpossible. However, to the spacer when length the changespacer lengthin a bulk becomes N-FinFET.Figure shorter 2 shows As than the the spacer 60transfer nm, length thecurve effective and increases, on/off channel cu therrent source length change and decreasesaccording drain resistancestorapidly the spacer resulting alsolength increase. in the increase changein leakage in a bulkcurrent. N-FinFET. Therefore, As the whenspacer thelength spacer increases, length the is source 80 nm, and the drain on/off resistances ratio will also be the The increaseincrease. insource The increase resistance in source causes resistance the degradation causes the degradation in on-state in on-state current.
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