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Leakage Current – Reverse-Biased Diode Leakage – Subthreshold Leakage – Tunneling Through Gate Oxide

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Leakage Current – Reverse-Biased Diode Leakage – Subthreshold Leakage – Tunneling Through Gate Oxide EEC 216 Lecture #9: Leakage Rajeevan Amirtharajah University of California, Davis Outline • Announcements • Review: Energy Recovery Circuits • Finish Lecture 8 • Leakage Mechanisms • Circuit Styles for Low Leakage • Cache SRAM Design Examples • Next Topic: Subthreshold Circuits R. Amirtharajah, EEC216 Winter 2009 2 Outline • Announcements • Review: Energy Recovery Circuits • Finish Lecture 8 • Leakage Mechanisms • Circuit Styles for Low Leakage • Cache SRAM Design Examples • Next Topic: Subthreshold Circuits R. Amirtharajah, EEC216 Winter 2009 3 Adiabatic Charging Analysis R Φ(t) CL Vc (t) ⎛ dVc ⎞ Φ =RC⎜ ⎟ +Vc ⎝ dt ⎠ • Solve differential equation assuming input is voltage ramp with duration T R. Amirtharajah, EEC216 Winter 2009 4 Energy Dissipated With Ramp Driver ∞ ∞Φ()V − ( ) t 2 E= i t() V t= dt c dt diss ∫RR() ∫ 0 0 R T Φ()V − ( ) t 2 ∞Φ( V − ( ) t)2 = ∫ c dt + ∫ c dt 0 R T R RC 2 ⎡ RC RC T− RC⎤ = CVDD ⎢1− + e ⎥ T ⎣ T T ⎦ • Consider the extreme cases of RC with respect to T – RC << T implies less energy dissipation R. Amirtharajah, EEC216 Winter 2009 5 Example Voltage Ramp: Stepwise Charging ΦN-1 ΦN vout + CT Φ1 VN −1 − + Φ0 Out CT V1 − Φ + GND CT V0 − R. Amirtharajah, EEC216 Winter 2009 6 Next Stage Controlled Energy Recovery Φ0 Φ1 −1 F1 P0 P1 x F0 F1 P0 y0 P1 y1 Φ1 R. Amirtharajah, EEC216 Winter 2009 7 Cascaded Logic Energy Recovery Timing Φ0 y0 Φ1 y1 • Charge nth stage nodes and then discharge (n-1)th stage nodes • How do we implement the energy recovery phase? R. Amirtharajah, EEC216 Winter 2009 8 Energy Recovery System Block Diagram DC CLOCK / ENERGY POWER RECOVERY AC DRIVER LOGIC V DD Φ0KΦN • Use circuits to generate power / clock waveforms • Generators must use as little power as possible – Resonant RLC circuits often used in these applications – Minimize parasitic losses in power / clock generator R. Amirtharajah, EEC216 Winter 2009 9 Outline • Announcements • Review: Energy Recovery Circuits • Finish Lecture 8 • Leakage Mechanisms • Circuit Styles for Low Leakage • Cache SRAM Design Examples • Next Topic: Subthreshold Circuits R. Amirtharajah, EEC216 Winter 2009 10 CMOS Inverter Example Idyn I sc Itun CL I subth R. Amirtharajah, EEC216 Winter 2009 11 Components of CMOS Power Dissipation • Dynamic Power – Charging and discharging load capacitances • Short Circuit (Overlap) Current – Occurs when PMOS and NMOS devices on simultaneously • Static Current – Bias circuitry in analog circuits • Leakage Current – Reverse-biased diode leakage – Subthreshold leakage – Tunneling through gate oxide R. Amirtharajah, EEC216 Winter 2009 12 Extremely Brief MOSFET Review μC W 2 Saturation: I = ()ox VVV−1 +λ () D 2 L GS T DS W ⎛ V 2 ⎞ ⎜ DS ⎟ Triode: ICD = μ ox VVV⎜GS()− T DS − ⎟ L ⎝ 2 ⎠ V V GS ⎛ − DS ⎞ nkT kT Subthreshold:I= I eq ⎜1 − eq ⎟ DS ⎜ ⎟ ⎝ ⎠ “Classical” OSFET model, will discuss deep submicron M modifications as necessary R. Amirtharajah, EEC216 Winter 2009 13 Subthreshold Conduction + VVGS< T nn p • Weak inversion, MOSFET partially conducting • n+ source – p+ bulk – n+ drain forms parasitic bipolar • Approximate current with exponential function R. Amirtharajah, EEC216 Winter 2009 14 Drain Current vs. Gate-Source Voltage 10−4 Quadratic Linear 10−6 I DS 10−8 10−10 Subthreshold 10−12 0 5.0 150. 10. 25. .2 VT VGS R. Amirtharajah, EEC216 Winter 2009 15 Subthreshold Current Equation V V GS ⎛ − DS ⎞ nkT kT I= I eq 1⎜ − eq ⎟() 1+ λV DS ⎜ ⎟ DS ⎝ ⎠ • Is and n rametersacal pare empiri • Typically, n ≥ 1 often ranging around n 1≈ . 5 • Usually want small subthreshold leakage for digital designs – Define quality metric: inverse of rate of decline of current wrt V below V GS T kT S= nln() 10 – Subthreshold slope factor S: q R. Amirtharajah, EEC216 Winter 2009 16 Subthreshold Slope Factor • Ideal case: n = 1 – S evaluates to 60 mV/decade (each 60 mV VGS drops below VT, current drops by 10X) – Typically n = 1.5 implies slower current decrease at 90 mV/decade – Current rolloff further decreased at high temperature, where fast CMOS logic tends to operate • n determined by intrinsic device topology and structure – Changing n requires different process, like SOI R. Amirtharajah, EEC216 Winter 2009 17 Leakage Currents in Deep Submicron G I7, I8 SD I2, I3, I6 I5 I1 I4 B • Many physical mechanisms produce static currents in deep submicron R. Amirtharajah, EEC216 Winter 2009 18 Transistor Leakage Mechanisms 1. pn Reverse Bias Current (I1) 2. Subthreshold (Weak Inversion) (I2) 3. Drain Induced Barrier Lowering (I3) 4. Gate Induced Drain Leakage (I4) 5. Punchthrough (I5) 6. Narrow Width Effect (I6) 7. Gate Oxide Tunneling (I7) 8. Hot Carrier Injection (I8) R. Amirtharajah, EEC216 Winter 2009 19 pn Reverse Bias Current (I1) • Reverse-biased pn junction current has two main components – Minority carrier drift near edge of depletion region – Electron-hole pair generation in depletion region of reverse-biased junction – If both n and p regions doped heavily, Zener tunneling may also be present • In MOSFET, additional leakage can occur – Gated diode device action (gate overlap of drain-well pn junctions) – Carrier generation in drain-well depletion regions influenced by gate • Function of junction area, doping concentration • Minimal contributor to total off current R. Amirtharajah, EEC216 Winter 2009 20 Drain Current vs. Gate-Source Voltage 10−4 Quadratic Linear 10−6 I DS 10−8 10−10 Subthreshold 10−12 0 5.0 150. 10. 25. .2 VT VGS R. Amirtharajah, EEC216 Winter 2009 21 Subthreshold Current Equation V V GS ⎛ − DS ⎞ nkT kT I= I eq 1⎜ − eq ⎟() 1+ λV DS ⎜ ⎟ DS ⎝ ⎠ • Is and n rametersacal pare empiri • Typically, n ≥ 1 often ranging around n 1≈ . 5 • Usually want small subthreshold leakage for digital designs – Define quality metric: inverse rate of decline of current wrt V below V GS T kT S= nln() 10 – Subthreshold slope factor S: q R. Amirtharajah, EEC216 Winter 2009 22 Detailed Subthreshold Current Equation ⎛ q ⎞⎛ ⎛ − qVDS ⎞⎞ IAD = exp⎜ VVVV()GS−0 T −γS η + D1⎟⎜ − exp⎜ ⎟⎟ ⎝ nkT ⎠⎝ ⎝ kT ⎠⎠ 2 W ⎛ kT ⎞ 1 . 8 AC= μ0 ox ⎜ ⎟ e L ⎝ q ⎠ • VT0 = zero bias threshold voltage, • μ0 = zero bias mobility • Cox = gate oxide capacitance per unit area • γ = linear body effect coefficient (small source voltage) • η = DIBL coefficient R. Amirtharajah, EEC216 Winter 2009 23 Subthreshold Slope of Various Processes S (mV / Technology Doping decade) 0.8 μm, 5 V CMOS LDD 86 0.6 μm, 5 V CMOS LDD 80 0.35 μm, 3.3 V BiCMOS LDD 80 0.35 μm, 2.5 V CMOS HDD 78 0.25 μm, 1.8 V CMOS HDD 85 • Roy & Prasad, p. 216 R. Amirtharajah, EEC216 Winter 2009 24 Drain Induced Barrier Lowering (I3) • DIBL occurs when drain depletion region interacts with source near channel surface – Lowering source potential barrier – Source injects carriers into channel without influence of gate voltage – DIBL enhanced at higher drain voltage, shorter effective channel length – Surface DIBL happens before deep bulk punchthrough • DIBL does not change S but lowers VT – Higher surface, channel doping and shallow junctions reduce DIBL leakage current mechanism R. Amirtharajah, EEC216 Winter 2009 25 Gate Induced Drain Leakage (I4) • GIDL current appears in high E-field region under gate / drain overlap causing deep depletion – Occurs at low VG and high VD bias – Generates carriers into substrate from surface traps, band-to-band tunneling – Localized along channel width between gate and drain – Seen as “hook” in I-V characteristic causing increasing current for negative VG – Thinner oxide, higher VDD, lightly-doped drain enhance GIDL • Can be major obstacle to reducing off current R. Amirtharajah, EEC216 Winter 2009 26 Revised Drain Current vs. Gate Voltage 10−4 10−6 DIBL I DS 10−8 GIDL Subthreshold 10−10 I1,I2 10−12 − 5.0 0 5.0 150. 10. 25. .2 VT VGS • Roy & Prasad, p. 217 R. Amirtharajah, EEC216 Winter 2009 27 Punchthrough VDS nn p • Source / Drain depletion regions “touch” deep inside channel R. Amirtharajah, EEC216 Winter 2009 28 Punchthrough Channel Current (I5) • Space-charge condition allows channel current to flow deep in subgate region – Gate loses control of subgate channel region • Current varies quadratically with drain voltage – Subthreshold slope factor S increases to reflect increase in drain leakage • Regarded as subsurface version of DIBL R. Amirtharajah, EEC216 Winter 2009 29 Gate Oxide Tunneling (I7) 2 −BEOX IOX = AEOX e • High E-field EOX can cause direct tunneling through gate oxide or Fowler-Nordheim (FN) tunneling through oxide bands • Typically, FN tunneling at higher field strength than operating conditions (likely remain in future) • Significant at oxide thickness < 50 Angstroms • Could become dominant leakage mechanism as oxides get thinner – High K dielectrics might make better – Interesting circuit design issues (see ISSCC 2004) R. Amirtharajah, EEC216 Winter 2009 30 Other Leakage Effects • Narrow Width Effect (I6) –VT increases for geometric gate widths around 0.5 μm in non-trench isolated technologies – Opposite effect in trench isolated technologies: VT decreases for widths below 0.5 μm • Hot Carrier Injection (I8) – Short channel devices susceptible to energetic carrier injection into gate oxide – Measurable as gate and substrate currents – Charges are a reliability risk leading to device failure – Increased amplitude as length reduced unless VDD scaled accordingly R. Amirtharajah, EEC216 Winter 2009 31 Leakage Summary 10−6 Weak inversion + pn junction + DIBL + GIDL (V = 3.9 V) 10−8 D Weak inversion + pn junction + I DS DIBL (VD = 2.7 V) 10−10 Weak inversion + pn junction (S = 80 mV/decade, VD = 0.1 V) 10−12 pn junction 10−14 • Roy & Prasad, p. 219 • No punchthrough • No width effect • No gate leakage R. Amirtharajah, EEC216 Winter 2009 32 Leakage Current Estimation PIV= leak ∑DSi DS i i • Parallel transistors, simply add leakage contributions for each one • For series connected devices, calculating leakage currents more complex – Equate subthreshold currents through each device in series stack – Solve for VDS1 (first device in series stack) in terms of VDD assuming source voltage small – Remaining voltages must sum to total voltage drop across series stack R.
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