http://dx.doi.org/10.5573/JSTS.2013.13.5.522 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.13, NO.5, OCTOBER, 2013

Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET

Ki-Ju Baek*, Kee-Yeol Na**, Jeong-Hyeon Park***, and Yeong-Seuk Kim*

Abstract—In this paper, simple but very effective , automotive electronics, sensor techniques to suppress subthreshold hump effect for interface and flat panel display driver applications [1-3]. high-voltage (HV) complementary metal-oxide- Shallow trench isolation (STI) is generally used instead semiconductor (CMOS) technology are presented. of the local oxidation of silicon (LOCOS) because Two methods are proposed to suppress subthreshold MOSFET has been scaled down to satisfy low power, hump effect using a simple layout modification high speed, and small size requirements for modern approach. First, the uniform gate oxide method is applications. STI technology offers a better isolation and based on the concept of an H-shaped gate layout larger device density. However, the abrupt transition design. Second, the gate work function control from the field to an active region in the STI edge method is accomplished by local ion implantation. For significantly influenced the electrical characteristics of our experiments, 0.18 μm 20 V class HV CMOS HV , resulting in the subthreshold hump effect technology is applied for HV MOSFETs fabrication. and inverse narrow width effect (INWE) [4, 5]. The root From the measurements, both proposed methods are cause of the subthreshold hump effect is well recognized very effective for elimination of the inverse narrow [6]. The threshold voltage (VT) at the channel edges is width effect (INWE) as well as the subthreshold hump. reduced by the enhanced fringing electric field due to field crowding. Another reason for the hump Index Terms—shallow trench isolation (STI), predominantly in the HV n-channel MOSFET subthreshold hump effect, high-voltage, MOSFET, (nMOSFET) is the lower surface doping concentration at work function, layout, narrow width effect (NWE), the channel edges due to the boron. The boron inverse narrow width effect (INWE) segregation more easily induces the depletion of the channel edge. For this entire mechanism, a parasitic edge

I. INTRODUCTION with reduced VT is observed at the channel edge. Therefore, the subthreshold hump can define as a Recently, embedding high-voltage (HV) devices into current summation of a parasitic edge transistor and main the advanced low-voltage (LV) complementary metal- channel HV MOSFET [7]. As a result, there is an oxide-semiconductor (CMOS) technology has been an increase in the subthreshold swing and off-state important trend of a cost-effective system on a chip current, which is especially harmful for low power (SoC) solution in the areas of power management applications. In addition, the subthreshold hump at the negative body bias worsens the functionality of the

Manuscript received Apr. 12, 2013; accepted Jun. 22, 2013 analog circuit, such as current mismatch in cascode * Dept. of Semiconductor Eng., Chungbuk National University, current mirrors [8]. The off-state leakage and device Cheongju, 361-763, Korea mismatching caused by the subthreshold hump are also ** Dept. of Semiconductor Electronics, Chungbuk Provincial College, Okcheon, Korea limitations of the device scale-down and analog circuit *** DSD Division, Magnachip Semiconductor, Cheongju, Korea design using small geometry MOSFET [9, 10]. E-mail : [email protected]

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In order to solve the subthreshold hump problem, 2). In modern CMOS technology, the commonly used many solutions have been proposed [11-17]. It is possible gate material is n+ and p+ doped polycrystalline silicon to reduce the oxide recess and corner rounding at the STI (poly-Si) and the gate work function depends on dopant corner using an additional complicated process [11-16]. and doping concentration of ion implantation. Thus, to

A relatively simple approach to eliminate the VT control gate work function, local ion implantation was difference between the parasitic edge transistor and the applied. Both of techniques are simple and effective to main channel MOSFET is a large angle tilted ion suppress subthreshold hump. In addition, we also present implantation of specific dopant to the sidewalls of the the limitations of each proposed method. trench [17]. However, the parameters of the large angle tilted ion implantation must be controlled carefully and II. DEVICE STRUCTURE AND FABRICATION additional photolithography is required. Thus, the process of CMOS technologies embedded HV devices A 0.18 μm HV CMOS technology was applied for would be more complicated and increase the fabrication fabrication. The major features of the HV CMOS cost. In addition, the extra process steps required for HV technology are a quadruple well (HV n-well, HV p-well, MOSFET can cause the degradation of the electrical n-well, p-well), dual gate oxide (7 nm, 50 nm), STI, dual characteristics of LV devices. As a result, an alternative gate material (i.e. n+ and p+ doped poly-Si gate) and solution without any extra fabrication process is desirable. cobalt salicide (CoSi2) for source and drain. Several simple approaches have been proposed using The major process flow is as follows: HV n-well and layout modification. Oishi et al. have proposed an H- p-well formation, STI formation, lightly doped n-drift shaped gate structure which can successfully suppress the and p-drift junction ion implantation and drive-in for HV isolation edge effect [5]. However it needs to be a larger MOSFETs, retrograded n-well and p-well formation for size and is not a suitable structure for HV devices which LV MOSFETs, thick gate oxidation (46 nm), selective are more complicated than LV devices. Another method wet etching to remove oxide for LV device area, thin gate is channel doping control using the baseline p-well [18]. oxidation (7 nm), undoped poly-Si deposition (250 nm), The p-well ion implantation easily compensates for the gate patterning, lightly doped drain (LDD) junction reduced VT of parasitic edge transistor in HV devices. formation by ion implantation and SiO2/Si3N4 (15 nm / This technique is well-known and a commonly used 55 nm) dielectrics spacer formation, n+ source and drain method in HV CMOS technologies. However, relatively junction ion implantation (As+, 50 keV, and 5×1015/cm2), + high and fixed p-well doping concentration causes large p+ source and drain junction ion implantation (BF2 , 20 15 2 VT shifts of narrow channel devices. Park et al. proposed keV, and 4×10 /cm ), CoSi2 formation, Si3N4 capping another simple method using undoped poly-Si for the layer deposition and BPSG for poly-to-metal (PMD) elimination of parasitic edge for HV devices dielectric with chemical mechanical polishing (CMP) [19]. However this method may not be sufficient to planarization, contact, and four levels of metal suppress severe subthreshold hump characteristics interconnections with TEOS inter-metal dielectrics with because the VT shift of undoped poly-Si is 0.56 V. CMP planarization. In this paper, we describe the characteristics of the A cross sectional view and layout of the fabricated HV subthreshold hump effect of a 0.18 μm 20 V class HV nMOSFETs are shown in Fig. 1. The n-drift region of the MOSFETs and proposed two suppression techniques for source and drain sides is lightly doped to endure a the subthreshold hump using only layout modification breakdown voltage (BV) higher than 25 V. To reduce without any extra fabrication processes. The first is the contact resistance, the poly-Si gate, n+ source, and drain uniform gate oxide method (Proposed 1) which is used to are adopted by the CoSi2. The minimum channel length eliminate the parasitic edge transistor, whereby the STI and width of the test structure are 1.6 μm and 1.0 μm, divot of the channel edge is located on the outside of the respectively. poly-Si gate and the gate oxide thickness of the channel area is to be uniform. The second method is gate work function control using local ion implantation (Proposed

524 KI-JU BAEK et al : SUPPRESSION TECHNIQUES OF SUBTHRESHOLD HUMP EFFECT FOR HIGH-VOLTAGE MOSFET

(a)

Fig. 2. Measured drain current versus gate voltage (I -V ) D GS characteristics for different VBS from the fabricated HV nMOSFET.

(b)

Fig. 1. (a) Cross-sectional view, (b) layout of fabricated HV nMOSFETs.

III. EXPERIMENTAL RESULTS AND DISCUSSION

In this section, we will describe the characteristics of the subthreshold hump effect of the fabricated HV Fig. 3. Measured VT as a function of channel width (W) from the fabricated HV nMOSFET. nMOSFETs in applied HV CMOS technology and propose two suppression techniques of subthreshold hump using only layout modification without any extra higher due to oxide recess. Thus, the VT difference fabrication processes. between the parasitic edge transistor and the main channel MOSFET increases with the negative body bias.

1. I-V Characteristics at Subthreshold Regime Fig. 3 shows the measured VT of HV MOSFETs on the channel width variation. The channel widths of test

Fig. 2 shows the measured drain current versus gate structures range from 1.0 to 10.0 μm. The VT of the HV voltage (ID-VGS) characteristics of HV nMOSFET which nMOSFETs reduces as the channel width decreases; thus were measured at different negative body voltages (VBS). the INWE are shown in Fig. 3. The VT difference The channel length (L) and width (W) of the test structure between the wide and narrow channels of HV nMOSFET are 3.6 μm and 10.0 μm, respectively. The drain voltage is 80 mV. The narrow channel device shows stronger

(VDS) is applied for 0.1 V. As VBS increases in the electrical characteristics of the parasitic edge transistor negative direction, the hump strength of HV nMOSFET and the drain current of the narrow channel device is increases due to the reduced sensitivity of the parasitic dominated by the parasitic edge transistor. For the wide edge transistor to the body bias compared with the main channel device, the drain current of the parasitic edge channel MOSFET. It is well known that the body transistor can be neglected. coefficient is a function of the body doping concentration Fig. 4 shows transmission electron microscopy (TEM) and the gate oxide capacitance. The transistor becomes image of the fabricated HV nMOSFET. The TEM less sensitive to the body bias if the body doping micrograph shows a cross sectional view around the STI concentration is lower or the gate oxide capacitance is corner. The upper active corner rounding is reasonable

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(a)

Fig. 4. TEM micrograph image of the fabricated HV nMOSFET. The thickness of gate oxide in the channel edge and center are 46 nm and 50 nm, respectively.

but the gate oxide thinning is clearly shown at the channel edge. The gate oxide thickness at the channel edge is about 46 nm, while the thickness of gate oxide at the channel center is 50 nm. The gate oxide thinning is one of the root causes of the subthreshold hump effect. Since the doping concentration at the surface of HV (b) nMOSFET is considerably low for high junction BV, the Fig. 5. Layout of HV nMOSFET for suppression of hump effect boron segregation more easily induces depletion of the (a) Proposed 1 (uniform gate oxide), (b) Proposed 2 (gate work channel due to field crowding. Boron segregation at the function control, shadow represents p+ doped poly-Si gate).

STI edges is another root cause of subthrehold hump of

HV nMOSFET. Thus the fabricated HV nMOSFETs have test structure of the gate work function control using both subthreshold hump effect and INWE. local ion implantation (Proposed 2). In modern CMOS technology, n+ or p+ doped poly-Si by ion implantation 2. Proposed Suppression Methods of Subthreshold is used as the gate material and the gate work function Hump depends on its dopant and doping concentration. The

nMOSFET with p+ doped poly-Si gate has higher VT This section describes our approach to solving the than the nMOSFET with n+ doped poly-Si gate due to subthreshold hump issue in the applied HV CMOS flat band voltage difference. If the parasitic edge technology. Both of the proposed methods are limited to transistor has higher VT than the main channel MOSFET, layout modification. Thus, no additional lithography or the channel of the parasitic edge transistor cannot easily special processing steps are required in the applied be depleted and subthreshold hump can be suppressed. fabrication process. Thus, to control the gate work function of the parasitic Fig. 5 shows proposed layouts to prevent parasitic edge transistor, selective p+ ion implantation was applied edge transistor turn-on. Fig. 5(a) shows the test structure for the gate end cap and poly-Si gate located at the of the uniform gate oxide method (Proposed 1). To channel edge. The gate end cap of the poly-Si gate (LE) is eliminate the parasitic edge transistor, the active layer of 0.3 μm. The overlap length of the p+ doped poly-Si gate test structures is designed to enclose the poly-Si gate. and silicon active layer (LO) is 0.3 μm at each channel Thus, the STI divot of the channel edge is located outside edge to prevent lithography misalignment. The baseline the poly-Si gate and the gate oxide thickness of the n+ and p+ source/drain ion implantations were used for channel edge is identical to that of the channel center the n+ and p+ doped poly-Si, respectively. Both p+ and area. The uniform gate oxide thickness is helpful to n+ poly-Si are connected electrically through a CoSi2 obtain better gate oxide reliability and there is also no layer. The measured VT of HV nMOSFET with the n+ boron segregation at channel edge. Fig. 5(b) shows the and p+ poly-Si are 0.96 V and 1.97 V, respectively.

526 KI-JU BAEK et al : SUPPRESSION TECHNIQUES OF SUBTHRESHOLD HUMP EFFECT FOR HIGH-VOLTAGE MOSFET

The measured ID-VGS characteristics of HV well in the narrow channel device. On the other hand, the nMOSFETs for the conventional and proposed methods proposed method 2 has no lateral diffusion and the 0.3 are shown in Fig. 6. The conventional method [18] and μm overlap length only affect VT increase. Therefore, VT our two proposed methods can suppress subthreshold shift is small compared to the conventional method [18]. hump effectively. However, the conventional method Fig. 8 shows the measured VT of the conventional and [19] is not sufficient to suppress subthreshold hump at a proposed methods as a function of the channel length. large negative body voltage. The channel lengths of the test structures are from 1.6 to

Fig. 7 shows the measured VT of the conventional and 9.6 μm, and W is identical to 10.0 μm. The VBS are proposed methods as a function of the channel width. applied at 0 V and -5 V. The short channel effect (SCE) is

The INWE is shown in both the reference and shown in all devices. However, smaller VT reduction as L conventional method [19]. However, there is no VT decreases is shown in all applied methods compare to the change regardless of the channel width for the proposed reference device. The INWE of the reference device method 1. But, the conventional method [18] and the results in a more severe SCE. These characteristics are proposed method 2 show the narrow width effect (NWE) shown more apparently at a large body voltage (VBS=-5 like MOSFET with LOCOS isolation. The VT of the V). Suppression of subthreshold hump can also help conventional method [18] increases abruptly as the suppress the SCE and well described in the previous channel width decreases because of relatively high study as the mixing effect [5]. surface doping concentration and lateral diffusion of p- Fig. 9 shows the measured drain saturation current

Fig. 6. Measured ID-VGS characteristics for different VBS from Fig. 8. Measured VT as a function of channel length (L) from the fabricated HV nMOSFETs for conventional and proposed the fabricated HV nMOSFETs for conventional and proposed methods. methods.

Fig. 7. Measured VT as a function of channel width (W) from Fig. 9. Measured drain saturation current (ID.SAT) as a function the fabricated HV nMOSFETs for conventional and proposed of channel width (W) from the fabricated HV nMOSFETs for methods. conventional and proposed methods.

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Table 1. Advantage and disadvantage of the proposed techniques Techniques Advantages Disadvantages Channel doping control - High V shift of narrow width devices [18] - Simple and cost effective T by p-well ion implantation - BV lowering by lateral diffusion of p-well Gate work function control [19] - Simple and cost effective - Imperfect suppression of severe hump by undoped poly-Si - Simple and cost effective Proposed 1 Uniform gate oxide - High I shift of narrow width devices - Good gate oxide reliability D Gate work function control Proposed 2 - Simple and cost effective - Strict photo-alignment control by p+ poly-Si

conventional method [19] is frequently observed due to high surface doping concentration and lateral diffusion of p-well. The conventional method [19] results in a limitation of device scale-down. As discussed previously, both of the proposed

techniques are effective to suppress subthreshold hump effect. Even though both of the proposed techniques have limitations, these techniques are very simple and still applicable. The advantages and disadvantages of the proposed techniques are summarized in Table 1.

Fig. 10. BV characteristics of the fabricated HV nMOSFETs for conventional and proposed methods (VGS = VBS = 0 V). V. CONCLUSIONS

We have proposed two simple and effective methods (ID.SAT) of the conventional and proposed methods as a for suppression of hump effect in a subthreshold regime. function of the channel width. The VDS and VGS are Both of the simple techniques used layout modification. applied at the same 20 V. ID.SAT of the proposed method 1 increases abruptly as W decreases. Such enhancement of Even though both proposed techniques have disadvantages, these techniques eliminate the ID.SAT is due to additional channel width that is formed by the n-drift layers and extension of the active layer. The subthreshold hump successfully. Obviously, elimination total W of the minimun narrow channel device using the of the subthreshold hump can reduce standby leakage proposed method 1 changes from 1.0 μm to 1.6 μm. As currents and power consumption as well as subthreshold current matching. We expect that these techniques are a result, ID.SAT of the narrow channel device is increased by 55%. HV MOSFETs are usually used with very large very effective methods for suppressing hump effect for W. If narrower channel device using the proposed method HV devices. 1 is employed for circuit design, W enhancement must be compensated. ACKNOWLEDGMENTS Fig. 10 shows the measured off-state BV characteristics. The geometry of the measured devices is This research was supported by the National Research a minimum size. The channel length and width are 1.6 Foundation of Korea (NRF) grant funded by the Korea

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Ki-Ju Baek received the B.S. degree Jeong-Hyeon Park received his B.S. in Electronics Engineering from the and M.S. degrees in Electronics University of Ulsan, Ulsan, Korea, in Engineering from Kyungpook National 2001, and the M.S., degree in University, Daegu, Korea, in 1994 Semiconductor Engineering from and 1996, respectively. Currently he Chungbuk National University, is with Magnachip semiconductor, Cheongju, Korea, in 2008. He is Korea. His research interests include currently working toward the Ph.D. degree with CMOS device physics and reliability. Department of Semiconductor Engineering, Chungbuk National University. From 2000 to 2010, he was with Magnachip Semiconductor, Korea, where he worked on Yeong-Seuk Kim received his B.S. the high voltage CMOS device and technology and M.S. degrees in Electronics development. From 2010 to 2012, he was with FSLab, Engineering from Seoul National Korea, where he worked on IC design for display and University, Korea, in 1980 and 1982, power applications. His research interests include respectively, and a Ph.D. degree in semiconductor device and analog integrated circuit Electrical Engineering from the design. University of Florida in 1990. From 1982 to 1985, he worked with the Central Research Laboratories of Gold Star, Seoul, Korea, where he Kee-Yeol Na received the M.S. designed analog and digital IC's for consumer electronics. degree in Electronics Engineering in From 1990 to 1993, he joined the Advanced Products 1997 and Ph.D. degree in Semicon- Research and Development Laboratory of Motorola, ductor Engineering in 2007, both Austin, Texas, where he worked on the characterization from Chungbuk National University, and modeling of bipolar transistors, CMOS and Cheongju, Korea. In 1997, he joined EEPROM technology development for advanced Hynix Semiconductor. (formerly LG microcontrollers. Since 1993, he has been on the faculty Semicon), Korea. He was a research engineer where he of Department of Semiconductor Engineering at worked on data storage stand-alone flash memory, high- Chungbuk National University, Korea. His research voltage device for DDI and embedded flash memory interests include low voltage analog and mixed-signal technology development. From 2001 to 2004, he was in integrated circuit design for RF, baseband and biomedical with Flasys, Korea, where he worked on embedded flash applications and dc-dc converters. memory IP development as a device manager. From 2007 to 2008, he spent his postdoctoral research in IHP, Frankfurt(Oder), Germany. Since 2008, he has been on the faculty of Semiconductor Electronics in Chungbuk Provincial College. His research fields include nonvolatile memory device, novel CMOS device concepts, high-performance power devices and analog integrated circuit design.