EE3032 Introduction to VLSI Design Jin-Fu Li Department of Electrical Engineering National Central University Jhongli, Taiwan A C B C=AxB abcd z Outline Chapter 1: Introduction to CMOS Circuits Chapter 2: MOS Transistor Theory Chapter 3: Fabrication of CMOS Integrated Circuits Chapter 4: Electrical Characteristics of CMOS Circuits Chapter 5: Elements of Physical Design Chapter 6: Combinational Circuit Design Chapter 7: Sequential Circuit Design Chapter 8: Introduction to 3D Integration using TSV Appendix Homeworks Chapter 1 Introduction to CMOS Circuit Design Jin-Fu Li Advanced Reliable Syym(E)L.stems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan Outline Introduction MOS Transistor Switches CMOS Logic Circuit and System Representation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 1 Binary Counter a Present Next state A state b abAB B 0001 0110 1011 1100 A = a’b + ab’ CK B = a’b’ + ab’ CLR Source: Prof. V. D. Agrawal Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 1-bit Multiplier A C B C=AxB Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 2 Switch: MOSFET MOSFETs are basic electronic devices used to direct and control logic signals in IC design MOSFET: Metal-Oxide-Semiconductor Field- Effect Transistor N-type MOS (NMOS) and P-type MOS (PMOS) Voltage-controlled switches A MOSFET has four terminals: gate, source, drain, and substrate (body) Complementary MOS (CMOS) Using two types of MOSFETs to create logic networks NMOS & PMOS Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Silicon Lattice and Dopant Atoms Pure silicon consists of a 3D lattice of atoms Silicon is a Group IV element and it forms covalent bonds with four adjacent atoms It is a poor conduc tor N-type (P-type) semiconductor By introducing small amounts of Group V-As (Group III-B) into the silicon lattice Si Si Si Si Si Si Si Si Si - + + - Si Si Si Si As Si Si B Si Si Si Si Si Si Si Si Si Si Lattice of pure Lattice of N-type Lattice of P-type Silicon Semiconductor Semiconductor Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 3 P-N Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 NMOS Transistor Four terminals: gate, source, drain, body Gate–oxide–body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal–oxide–semiconductor (MOS) capacitor Even though gate is no longer made of metal SourceGate Drain Polysilicon SiO2 n+ n+ p bulk Si Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8 4 NMOS Operations Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltag e Source-body and drain-body diodes are OFF No current flows, transistor is OFF SourceGate Drain Polysilicon SiO2 0 n+ n+ S D p bulk Si Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9 NMOS Operations (Cont.) When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON SourceGate Drain Polysilicon SiO2 1 n+ n+ S D p bulk Si Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10 5 PMOS Operations Similar, but doping and voltages reversed Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior SourceGate Drain Polysilicon SiO2 p+ p+ n bulk Si Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11 Threshold Voltage Every MOS transistor has a characterizing parameter called the threshold voltage VT The specific value of VT is established during the manufacturing process Threshold voltage of an NMOS and a PMOS NMOS PMOS V V Drain A Source A VDD + VDD VDD VGSp Gate V =1 VDD-|VTp| V =1 V Mn A V - Mp A A + Mn On A Gate Mp Off VGSn - Source VTn VA=0 VA=0 0 Mn Off Drain 0 Mp On Gate-source voltage Logic translation Gate-source voltage Logic translation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12 6 MOS Transistor is Like a Tap… Source: Prof. Banerjee, ECE, UCSB Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13 MOS Switches NMOS symbol and characteristics Vth 5v 5v 5v-V 00v 00v th PMOS symbol and characteristics 0v Vth 5v 5v 0v Vth Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14 7 CMOS Switch A complementary CMOS switch Transmission gate -s -s Symbols a C b a b a b s s s 0v 55v 55v Characteristics 0v 0v 5v Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 CMOS Logic-Inverter The NOT or INVERT function is often considered the simplest Boolean operation F(x)=NOT(x)=x’ Vdd Vin Vout Vin Vout Vdd Vdd Vdd Indeterminate 0110 Vdd/2 logic level Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16 8 Combinational Logic Serial structure S1=0 S1=0 S1=1 S1=1 a S2=0 S2=1 S2=0 S2=1 S1 01 S1 0 a!=b a!=b S2 S2 1 a!=b a=b b S1=0 S1=0 S1=1 S1=1 a S2=0 S2=1 S2=0 S2=1 S1 0 1 S1 0 a=b a!=b S2 1 a!=b a!=b S2 b Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17 Combinational Logic Parallel structure S1=0 S1=0 S1=1 S1=1 aS1S2=0 S2=1 S2=0 S2=1 01 0 a!=b a=b S1 S2 S2 1 a=b a=b b S1=0 S1=0 S1=1 S1=1 S1 a S2=0 S2=1 S2=0 S2=1 01 0 a=b a=b S1 S2 S2 1 a=b a!=b b Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18 9 NAND Gate Output A A 0 1 0 1 1 B B 1 10 A Output B Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19 NOR Gate A B A 0 1 Output 0 1 0 B 1 00 A Output B Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20 10 Compound Gate F = ((AB) + (CD)) A B A C D B F F C D A C B D Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21 Structured Logic Design CMOS logic gates are intrinsically inverting The output always produces a NOT operation acting on the input variables For example, the inverter shown below illustrates this property 1 VDD a=1 f0f=0 0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22 11 Structured Logic Design The inverting nature of CMOS logic circuits allows us to construct logic circuits for AOI and OAI expressions using a structured approach AOI logic function Implements the operations in the order AND then OR then NOT E.g., g (a, b, c, d ) = a.b + c.d OAI logic function Implements the operations in the order OR then AND then NOT E.g., g (a, b, c, d ) = (a + b) ⋅ (c + d ) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23 Structured Logic Design Behaviors of nMOS and pMOS groups Parallel-connected nMOS OR-NOT operations Parallel-connected pMOS AND-NOT operations Series-connected nMOS AND-NOT operations Series-connected pMOS OR-NOT operations Consequently, wired groups of nMOS and pMOS are logical duals of another Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24 12 Dual Property If an NMOS group yields a function of the form g = a ⋅ (b + c ) then an identically wired PMOS array gives the dual function G = a + (b ⋅ c) where the AND and OR operations have been interchanged This is an interesting property of NMOS-PMOS logic that can be exploited in some CMOS designs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25 An Example of Structured Design X = a + b ⋅ (c + d ) VDD c b d a Group 1 Group 2 Group 3 X b a c d Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26 13 An Example of XOR Gate Boolean equation of the two input XOR gate a ⊕ b = a ⋅ b + a ⋅ b, this is not in AOI form But, a ⊕ b = a ⋅ b + a ⋅ b , this is in AOI form Therefore, a ⊕ b = (a ⊕ b) = a ⋅ b + a ⋅ b VDD VDD a b a b • • • • b a b a • • a ⊕ b • • a ⊕ b a a a a b b bb XOR Gate XNOR Gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27 Multiplexer A 11 B 10 Y A C 01 1 Y D 00 B 0 S S1 S0 -S A A B Y S Y B C -S D S1 -S1 S0 -S0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28 14 Static CMOS Summary In static circuits at every point in time (except when switching), the output is connected to either Vdd or Gnd through a low resistance path Fan-in of n (or n it)inputs) requires 2n (n N-type and n P- type) devices Non-ratioed logic: gates operate independent of PMOS or NMOS sizes No path ever exists between Vdd and Gnd: low static power Fully-restored logic (NMOS passes “0” only and PMOS passes “1” only Gates must be inverting Advanced Reliable Systems (ARES) Lab.