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System Buses EE2222 Computer Interfacing and Microprocessors
System Buses EE2222 Computer Interfacing and Microprocessors Partially based on Computer Organization and Architecture by William Stallings Computer Electronics by Thomas Blum 2020 EE2222 1 Connecting • All the units must be connected • Different type of connection for different type of unit • CPU • Memory • Input/Output 2020 EE2222 2 CPU Connection • Reads instruction and data • Writes out data (after processing) • Sends control signals to other units • Receives (& acts on) interrupts 2020 EE2222 3 Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write • Timing 2020 EE2222 4 Input/Output Connection(1) • Similar to memory from computer’s viewpoint • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer 2020 EE2222 5 Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • e.g. spin disk • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals (control) 2020 EE2222 6 What is a Bus? • A communication pathway connecting two or more devices • Usually broadcast (all components see signal) • Often grouped • A number of channels in one bus • e.g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown 2020 EE2222 7 Bus Interconnection Scheme 2020 EE2222 8 Data bus • Carries data • Remember that there is no difference between “data” and “instruction” at this level • Width is a key determinant of performance • 8, 16, 32, 64 bit 2020 EE2222 9 Address bus • Identify the source or destination of data • e.g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system • e.g. -
Getting Started with Your VXI-1394 Interface for Windows NT/98 And
VXI Getting Started with Your VXI-1394 Interface for Windows NT/98 VXI-1394 Interface for Windows NT/98 November 1999 Edition Part Number 322109D-01 Worldwide Technical Support and Product Information www.ni.com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin, Texas 78759-3504 USA Tel: 512 794 0100 Worldwide Offices Australia 03 9879 5166, Austria 0662 45 79 90 0, Belgium 02 757 00 20, Brazil 011 284 5011, Canada (Calgary) 403 274 9391, Canada (Ontario) 905 785 0085, Canada (Québec) 514 694 8521, China 0755 3904939, Denmark 45 76 26 00, Finland 09 725 725 11, France 01 48 14 24 24, Germany 089 741 31 30, Greece 30 1 42 96 427, Hong Kong 2645 3186, India 91805275406, Israel 03 6120092, Italy 02 413091, Japan 03 5472 2970, Korea 02 596 7456, Mexico (D.F.) 5 280 7625, Mexico (Monterrey) 8 357 7695, Netherlands 0348 433466, Norway 32 27 73 00, Poland 48 22 528 94 06, Portugal 351 1 726 9011, Singapore 2265886, Spain 91 640 0085, Sweden 08 587 895 00, Switzerland 056 200 51 51, Taiwan 02 2377 1200, United Kingdom 01635 523545 For further support information, see the Technical Support Resources appendix. To comment on the documentation, send e-mail to [email protected] © Copyright 1998, 1999 National Instruments Corporation. All rights reserved. Important Information Warranty The National Instruments VXI-1394 board is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. -
Mamaoma Writing EISA Bus Device Drivers
DEC OSF/l mamaoma Writing EISA Bus Device Drivers Part Number: AA-QOR6A-TE DEC OSF/1 Writing EISA Bus Device Drivers Order Number: AA-QOR6A-TE February 1994 Product Version: DEC OSF/1 Version 2.0 or higher This guide contains information systems engineers need to write device drivers that operate on the EISA bus. The guide describes EISA bus specific topics, including EISA bus architecture and the data structures that EISA bus drivers use. digital equipment corporation Maynard, Massachusetts Restricted Rights: Use, duplication, or disclosure by the U.S. Government is subject to restrictions as set forth in subparagraph (c) (1) (ii). Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description. Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid written license from Digital or an authorized sublicensor. © Digital Equipment Corporation 1994 All rights reserved. The following are trademarks of Digital Equipment Corporation: ALL-IN-I, Alpha AXP, AXP, Bookreader, CDA, DDIS, DEC, DEC FUSE, DECnet, DEC station, DECsystem, DECUS, DECwindows, DTIF, MASSBUS, MicroVAX, Q-bus, ULTRIX, ULTRIX Mail Connection, ULTRIX Worksystem Software, UNIBUS, VAX, V AXstation, VMS, XUI, and the DIGITAL logo. UNIX is a registered trademark licensed exclusively by X/Open Company Limited. Open Software Foundation, OSF, OSFIl, OSFlMotif, and Motif are trademarks of the Open Software Foundation, Inc. -
VME for Experiments Chairman: Junsei Chiba (KEK)
KEK Report 89-26 March 1990 D PROCEEDINGS of SYMPOSIUM on Data Acquisition and Processing for Next Generation Experiments 9 -10 March 1989 KEK, Tsukuba Edited by H. FUJII, J. CHIBA and Y. WATASE NATIONAL LABORATORY FOR HIGH ENERGY PHYSICS PROCEEDINGS of SYMPOSIUM on Data Acquisition and Processing for Next Generation Experiments 9 - 10 March 1989 KEK, Tsukuba Edited H. Fiflii, J. Chiba andY. Watase i National Laboratory for High Energy Physics, 1990 KEK Reports are available from: Technical Infonnation&Libraiy National Laboratory for High Energy Physics 1-1 Oho, Tsukuba-shi Ibaraki-ken, 305 JAPAN Phone: 0298-64-1171 Telex: 3652-534 (Domestic) (0)3652-534 (International) Fax: 0298-64-4604 Cable: KEKOHO Foreword This symposium has been organized to foresee the next generation of data acquisition and processing system in high energy physics and nuclear physics experiments. The recent revolutionary progress in the semiconductor and computer technologies is giving us an oppotunity to extend our idea on the experiments. The high density electronics of LSI technology provides an ideal front-end electronics such as readout circuits for silicon strip detector and multi-anode phototubes as well as wire chambers. The VLSI technology has advantages over the obsolite discrete one in the various aspects ; reduction of noise, small propagation delay, lower power dissipation, small space for the installation, improvement of the system reliability and maintenability. The small sized front-end electronics will be mounted just on the detector and the digital data might be transfered off the detector to the computer room with optical fiber data transmission lines. Then, a monster of bandies of signal cables might disappear from the experimental area. -
NCR 53C700/53C700-66 SCSI 1/0 Processor Data Manual
NCR 53C700/53C700-66 SCSI 1/0 Processor Data Manual The product(s) described in this publication is a licensed product of NCR Corporation. TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation. It is the policy of NCR Corporation to improve products as new technology, components, software, and firmware become available. NCR Corporation, therefore, reserves the right to change specifications without notice. NCR products are not intended for use in life-suppott appliances, devices, or systems. Use of an NCR product in such applications without the written consent ofthe appropriate NCR officer is prohibited. For information on updates to this or other NCR products, contact the NCR Microelectronic Products Division electronic bulletin board at (719) 596-1649. Copyright ©1993 By NCR Corporation Dayton, Ohio U.S.A. All Rights Reserved Printed in U.S.A. c Preface SCSI Specifications This manual assumes some prior knowledge of current and proposed SCSI standards. For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-1986 (SCSI-I) Global Engineering Documents 2805 McGaw Irvine, CA 92714 (800)-854-7179 or (714) 261-1455 .? Ask for document number X3.131-199X (SCSI-2) ENDL Publications 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia Prentice Hall Englewood Cliffs, NJ 07632 (201) 767-5937 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Inter face NCR Microelectronic Products Division Electronic Bulletin Board (719) 596-1649 The SCSI Electronic Bulletin Board (719) 574-0424 NCR 53C700/53C700-66 Data Manual Revision Record Page No. -
STD 7000 7802 6800 Processor Card USER's MANUAL
STD 7000 7802 6800 Processor Card USER'S MANUAL .: . o o NOTICE The information in this document is provided for reference only. Pro-Log does not assume any liability arising 0 out of the application or use of the information or products described herein. This document may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of Pro-Log, nor the rights of others. Printed in U.S.A. Copyright© 1981 by Pro-Log Corporation, Monterey, CA 93940. All rights reserved. However, any part of this document may be reproduced with Pro-Log Corporation cited as the source. STD 7000 7802 6800 Processor Card USER'S MANUAL o 2/82 aa uailUIlAIMIMIlIdIHI6IJYIWiiIIi&&iIlWiHiiiii1WGL&lil1l4JI£jj1, __ oGllI{fldf4IL1lfI[.JIilJI!1U1l4J!;;QI!IMf&bnUMliMJi1illldOif kLCH1LJ _"- _,L JLJ L _11 ____ ,BAGLin _ ta, _ h 'h41J1P i4I A;.u 4 FOREWORD This manual explains how to use Pro-Log's 7802 6800 Processor Card. It is structured to reflect the answers to o basic questions that you, the user, might ask yourself about the 7802. We welcome your suggestions on how we can improve our instructions. The 7802 is part of Pro-Log's Series 7000 STD BUS hardware. Our products are modular, and they are designed and built with second-sourced parts that are industry standards. They provide the industrial manager with the means of utilizing his own people to control the design, production, and maintenance of the company's products that use STD BUS hardware. -
PCI Express Basics & Background
PCI Express® Basics & Background Richard Solomon Synopsys Copyright © 2014, PCI-SIG, All Rights Reserved 1 Acknowledgements Thanks are due to Ravi Budruk, Mindshare, Inc. for much of the material on PCI Express Basics PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 2 Agenda . PCI Express Background . PCI Express Basics . PCI Express Recent Developments PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 3 PCI Express Background PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 4 Revolutionary AND Evolutionary . PCI™ (1992/1993) Revolutionary – Plug and Play jumperless configuration (BARs) – Unprecedented bandwidth • 32-bit / 33MHz – 133MB/sec • 64-bit / 66MHz – 533MB/sec – Designed from day 1 for bus-mastering adapters Evolutionary – System BIOS maps devices then operating systems boot and run without further knowledge of PCI – PCI-aware O/S could gain improved functionality – PCI 2.1 (1995) doubled bandwidth with 66MHz mode PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 5 Revolutionary AND Evolutionary . PCI-X™ (1999) Revolutionary – Unprecedented bandwidth • Up to 1066MB/sec with 64-bit / 133MHz – Registered bus protocol • Eased electrical timing requirements – Brought split transactions into PCI “world” Evolutionary – PCI compatible at hardware *AND* software levels – PCI-X 2.0 (2003) doubled bandwidth • 2133MB/sec at PCI-X 266 and 4266MB/sec at PCI-X 533 PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 6 Revolutionary AND Evolutionary . PCI Express – aka PCIe® (2002) Revolutionary – Unprecedented bandwidth • x1: up to 1GB/sec in *EACH* direction • x16: up to 16GB/sec in *EACH* direction – “Relaxed” electricals due to serial bus architecture • Point-to-point, low voltage, dual simplex with embedded clocking Evolutionary – PCI compatible at software level • Configuration space, Power Management, etc. -
Industrial I/O Solutions 12-1
Table of Contents / Industrial I/O Solutions 12-1 12 Industrial I/O Solutions 12-4 DAQ-Embedded Computers 12-5 Analog I/O and Multifunction Cards 12-9 Digital I/O and Multifunction Cards 12-15 USB I/O Modules and USB Hubs 12-18 Signal Conditioners and Terminal Boards 12-21 Serial Communication Cards 12-2 Product Introduction Advantech Data Acquisition and Control Solutions As a leading supplier of data acquisition products worldwide, Advantech offers a wide range of I/O devices with various interfaces and functions based on PC technology, from legacy ISA to modern USB and from signal-conditioning to graphical software tools. Advantech’s industrial I/O products are reliable, accurate, affordable, and suitable for many industrial automation applications (e.g., testing and measurement) and laboratory applications (e.g., monitoring, control, machine automation, and product testing). Signal Sensing Signal Conditioning Data Acquisition Signal Conditioners Embedded Computers Advantech’s signal conditioners provide sensor MIC-1800 series units are standalone embedded and signal conditioning on a per-module basis for computers with integrated data acquisition modules various types of sensors or signals. and signal conditioning to provide digital I/O, analog I/O, and counter functions. The palm-sized design with built-in terminals is suitable for space-limited applications. I/O Wiring Terminal Boards SuperSpeed USB 3.0 I/O Modules Equipment Sensor I/O wiring terminal boards offer convenient and SuperSpeed USB 3.0 I/O modules can be leveraged reliable signal wiring for a wide range of Advantech for a diverse range of industrial control applications. -
Stand-Alone VME Bus PC104 Bus ISA Bus STD Bus, & STD32
SYNCHRO / RESOLVER / LVDT CONVERTERS / BUS CARDS / AMPLIFIERS ABSOLUTE ENCODERS / READOUTS www.computerconversions.com 6 Dunton Court, East Northport, NY 11731 (631) 261-3300 Fax: (631) 261-3308 BUS CARD LEVEL PRODUCTS: SYNCHRO / RESOLVER / LVDT I/O VME Bus PC104 Bus Synchro / Resolver / LVDT I/O Synchro / Resolver / LVDT I/O Inputs: 1 - 12 Channels Synchro / Inputs: 1 - 4 Channels Synchro / Resolver, & 2-3 Wire LVDT Formats, Resolver and LVDT inputs with B-I-T & Forced Angle Self-Test Mods., B-I-T and Forced angle Self-Test, VBT True Wrap-Around Self-Test. Transformer Isolation opt.even on To 16 Bits, acc. 2', Tracking Rates to 60Hz. 200RPS. On-Board AC Reference Models., 16 Bits, 2.'acc.Tracking Rates options, Low cost Solid State and to 200RPS. Ultra Reliable and quick 100% Transformer Isolated models. delivery. AC Reference Supply Outputs: LVDT/ RVDT 1-12 Chan.s options. Synchro/Resolver: 1-4 Channels, high Outputs: 1-2 Channels Synchro / Res. power, output, drive 1.2 to 5VA, Low Low cost & Isol. mod's. 16 Bits, 1 - 4' Cost +/-12V. DC Bus powered & Reference acc. Loss detect, support for external Powered Converters. Transformer Isol ated Boosters upto 300VA. including I/O. Resolution: 14/16 Bits, accuracy 2'/ 4'. Disable control & BIT / Fault Report. All: A24/D16 6UH. Multispeed I/O, & All: No Violations, 0 - 70 and -40 - Mix & Match all I/O. 0 - 70 & -40 to +85C. +85C models. Software Demo w/ Conduction Cooled avail. PCI &COMPACT PCI ISA Bus All Plug and Play, with Software DLL's, PCI Same Selections 1-8 Inputs, Upto 4 High Power Output Channels, Transformer as on ISA Bus, CPCI Same Selections as on VME Bus. -
UPA—Sun'shighperformance Graphicsconnection
UPA—Sun’sHighPerformance GraphicsConnection TechnicalWhitePaper 1999 Sun Microsystems, Inc. All rights reserved. Printed in the United States of America. 901 San Antonio Road, Palo Alto, California 94303 U.S.A. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, Ultra, Sun Elite3D, Sun Enterprise, Java 3D, PGX, Java, SBus, and VIS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. OpenGL is a registered trademark of Silicon Graphics, Inc. THIS PUBLICATION IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOGRAPHICAL ERRORS. CHANGES ARE PERIODICALLY ADDED TO THE INFORMATION HEREIN; THESE CHANGES WILL BE INCORPORATED IN NEW EDITIONS OF THE PUBLICATION. SUN MICROSYSTEMS, INC. MAY MAKE IMPROVEMENTS AND/OR CHANGES IN THE PRODUCT(S) AND/OR THE PROGRAM(S) DESCRIBED IN THIS PUBLICATION AT ANY TIME. Please Recycle Contents Introduction. 1 Analyzing System Design and Application Performance. 2 Design Trade-offs . 2 An Overview of the UPA Interconnect . 3 Scalability, High Bandwidth, and Efficiency . 5 The UPA64S Graphics Bus. 6 Characterizing Application Performance and Bus Traffic. 7 UPA64S and Other Graphics Bus Technologies . -
USER MANUAL for USB 2.0 Card Bus Notice
USER MANUAL for USB 2.0 Card Bus Notice: This manual is designed to provide information about the USB2.0 Card Bus. Every effort has been made to make this manual as accurate as possible, but no warranty or fitness is implied. Information contained in this manual is subject to change without prior notice in order to improve reliability, design or function. The manufacturer will not be held responsible for technical or editorial omissions made herein, nor for the incidental or consequential damages resulting from its furnishing, performance, functionality or use. Subsequent changes to this manual will be incorporated into the next edition. We welcome any suggestion regarding this manual or our computer products. Trademarks All product names or trademarks are property of their respective owners. Overview The CardBus holds a secure place as the preferred high-performance add-in-mechanism for mobile computing platforms today and in the future. CardBus, the 32-bit high performance bus mastering architecture for PC Cards, was standardized by the PCMCIA. The transfer rate is up to 480Mbit/sec, and is very useful for PC Camera, HDD, Printer…etc, and many other devices with USB2.0 interface. Features Compliant with Universal Serial Bus Specification Revision 2.0 (Transfer Rate 1.5/12/480 Mbps) Compliant with Open Host Controller Interface Specification for USB Rev 1.0a Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95 All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction Plug & Play functions Supports 32 bit CardBus PC Card Type II slots Supports Bus Power Operation System Requirements Windows 98/98SE/2000/ME/XP Mac OS 10.1 1 USER MANUAL for USB 2.0 Card Bus Package Contents One USB2.0 CardBus One CD driver with user’s manual Cautions 1. -
PC Hardware Contents
PC Hardware Contents 1 Computer hardware 1 1.1 Von Neumann architecture ...................................... 1 1.2 Sales .................................................. 1 1.3 Different systems ........................................... 2 1.3.1 Personal computer ...................................... 2 1.3.2 Mainframe computer ..................................... 3 1.3.3 Departmental computing ................................... 4 1.3.4 Supercomputer ........................................ 4 1.4 See also ................................................ 4 1.5 References ............................................... 4 1.6 External links ............................................. 4 2 Central processing unit 5 2.1 History ................................................. 5 2.1.1 Transistor and integrated circuit CPUs ............................ 6 2.1.2 Microprocessors ....................................... 7 2.2 Operation ............................................... 8 2.2.1 Fetch ............................................. 8 2.2.2 Decode ............................................ 8 2.2.3 Execute ............................................ 9 2.3 Design and implementation ...................................... 9 2.3.1 Control unit .......................................... 9 2.3.2 Arithmetic logic unit ..................................... 9 2.3.3 Integer range ......................................... 10 2.3.4 Clock rate ........................................... 10 2.3.5 Parallelism .........................................