Firewire System Architecture, Second Edition
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
System Buses EE2222 Computer Interfacing and Microprocessors
System Buses EE2222 Computer Interfacing and Microprocessors Partially based on Computer Organization and Architecture by William Stallings Computer Electronics by Thomas Blum 2020 EE2222 1 Connecting • All the units must be connected • Different type of connection for different type of unit • CPU • Memory • Input/Output 2020 EE2222 2 CPU Connection • Reads instruction and data • Writes out data (after processing) • Sends control signals to other units • Receives (& acts on) interrupts 2020 EE2222 3 Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write • Timing 2020 EE2222 4 Input/Output Connection(1) • Similar to memory from computer’s viewpoint • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer 2020 EE2222 5 Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • e.g. spin disk • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals (control) 2020 EE2222 6 What is a Bus? • A communication pathway connecting two or more devices • Usually broadcast (all components see signal) • Often grouped • A number of channels in one bus • e.g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown 2020 EE2222 7 Bus Interconnection Scheme 2020 EE2222 8 Data bus • Carries data • Remember that there is no difference between “data” and “instruction” at this level • Width is a key determinant of performance • 8, 16, 32, 64 bit 2020 EE2222 9 Address bus • Identify the source or destination of data • e.g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system • e.g. -
Getting Started with Your VXI-1394 Interface for Windows NT/98 And
VXI Getting Started with Your VXI-1394 Interface for Windows NT/98 VXI-1394 Interface for Windows NT/98 November 1999 Edition Part Number 322109D-01 Worldwide Technical Support and Product Information www.ni.com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin, Texas 78759-3504 USA Tel: 512 794 0100 Worldwide Offices Australia 03 9879 5166, Austria 0662 45 79 90 0, Belgium 02 757 00 20, Brazil 011 284 5011, Canada (Calgary) 403 274 9391, Canada (Ontario) 905 785 0085, Canada (Québec) 514 694 8521, China 0755 3904939, Denmark 45 76 26 00, Finland 09 725 725 11, France 01 48 14 24 24, Germany 089 741 31 30, Greece 30 1 42 96 427, Hong Kong 2645 3186, India 91805275406, Israel 03 6120092, Italy 02 413091, Japan 03 5472 2970, Korea 02 596 7456, Mexico (D.F.) 5 280 7625, Mexico (Monterrey) 8 357 7695, Netherlands 0348 433466, Norway 32 27 73 00, Poland 48 22 528 94 06, Portugal 351 1 726 9011, Singapore 2265886, Spain 91 640 0085, Sweden 08 587 895 00, Switzerland 056 200 51 51, Taiwan 02 2377 1200, United Kingdom 01635 523545 For further support information, see the Technical Support Resources appendix. To comment on the documentation, send e-mail to [email protected] © Copyright 1998, 1999 National Instruments Corporation. All rights reserved. Important Information Warranty The National Instruments VXI-1394 board is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. -
A Technology Comparison Adopting Ultra-Wideband for Memsen’S File Sharing and Wireless Marketing Platform
A Technology Comparison Adopting Ultra-Wideband for Memsen’s file sharing and wireless marketing platform What is Ultra-Wideband Technology? Memsen Corporation 1 of 8 • Ultra-Wideband is a proposed standard for short-range wireless communications that aims to replace Bluetooth technology in near future. • It is an ideal solution for wireless connectivity in the range of 10 to 20 meters between consumer electronics (CE), mobile devices, and PC peripheral devices which provides very high data-rate while consuming very little battery power. It offers the best solution for bandwidth, cost, power consumption, and physical size requirements for next generation consumer electronic devices. • UWB radios can use frequencies from 3.1 GHz to 10.6 GHz, a band more than 7 GHz wide. Each radio channel can have a bandwidth of more than 500 MHz depending upon its center frequency. Due to such a large signal bandwidth, FCC has put severe broadcast power restrictions. By doing so UWB devices can make use of extremely wide frequency band while emitting very less amount of energy to get detected by other narrower band devices. Hence, a UWB device signal can not interfere with other narrower band device signals and because of this reason a UWB device can co-exist with other wireless devices. • UWB is considered as Wireless USB – replacement of standard USB and fire wire (IEEE 1394) solutions due to its higher data-rate compared to USB and fire wire. • UWB signals can co-exists with other short/large range wireless communications signals due to its own nature of being detected as noise to other signals. -
Mamaoma Writing EISA Bus Device Drivers
DEC OSF/l mamaoma Writing EISA Bus Device Drivers Part Number: AA-QOR6A-TE DEC OSF/1 Writing EISA Bus Device Drivers Order Number: AA-QOR6A-TE February 1994 Product Version: DEC OSF/1 Version 2.0 or higher This guide contains information systems engineers need to write device drivers that operate on the EISA bus. The guide describes EISA bus specific topics, including EISA bus architecture and the data structures that EISA bus drivers use. digital equipment corporation Maynard, Massachusetts Restricted Rights: Use, duplication, or disclosure by the U.S. Government is subject to restrictions as set forth in subparagraph (c) (1) (ii). Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description. Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid written license from Digital or an authorized sublicensor. © Digital Equipment Corporation 1994 All rights reserved. The following are trademarks of Digital Equipment Corporation: ALL-IN-I, Alpha AXP, AXP, Bookreader, CDA, DDIS, DEC, DEC FUSE, DECnet, DEC station, DECsystem, DECUS, DECwindows, DTIF, MASSBUS, MicroVAX, Q-bus, ULTRIX, ULTRIX Mail Connection, ULTRIX Worksystem Software, UNIBUS, VAX, V AXstation, VMS, XUI, and the DIGITAL logo. UNIX is a registered trademark licensed exclusively by X/Open Company Limited. Open Software Foundation, OSF, OSFIl, OSFlMotif, and Motif are trademarks of the Open Software Foundation, Inc. -
LPT, COM, 1394, USB, USB-C LPT IEEE 1284, LPT (Англ. Line Print Terminal; Также Параллельный Порт, По
LPT, COM, 1394, USB, USB-C LPT IEEE 1284, LPT (англ. Line Print Terminal; также параллельный порт, порт принтера) — международный стандарт параллельного интерфейса для подключения периферийных устройств персонального компьютера. В основном используется для подключения к компьютеру принтера, сканера и других внешних устройств (часто использовался для подключения внешних устройств хранения данных), однако может применяться и для других целей (организация связи между двумя компьютерами, подключение каких-либо механизмов телесигнализации и телеуправления). В основе данного стандарта лежит интерфейс Centronics и его расширенные версии (ECP, EPP). Название LPT образовано от наименования стандартного устройства принтера LPT1 (Line Printer Terminal или Line PrinTer) в операционных системах семейства MS-DOS. Параллельный порт Centronics — порт, используемый с 1981 года в персональных компьютерах фирмы IBM для подключения печатающих устройств, разработан фирмой Centronics Data Computer Corporation; уже давно стал стандартом де-факто, хотя в действительности официально на данный момент он не стандартизирован. Изначально этот порт был разработан только для симплексной (однонаправленной) передачи данных, так как предполагалось, что порт Centronics должен использоваться только для работы с принтером. Впоследствии разными фирмами были разработаны дуплексные расширения интерфейса (byte mode, EPP, ECP). Затем был принят международный стандарт IEEE 1284, описывающий как базовый интерфейс Centronics, так и все его расширения. Разъемы. Порт на стороне управляющего -
PC 97 Hardware Design Guide
Part 4 — Device Design Guidelines CHAPTER 21 Printers This chapter presents the requirements and recommendations for printers under the Microsoft Windows family of operating systems. Version 1.1 Includes changes to References for Printers Contents Overview for Printers.............................. ............... 312 Basic Printer Features............................. ................ 312 Basic Features for IEEE 1394 Printers. ................. 312 Basic Features for USB Printers . ............... 312 Basic Features for IEEE 1284 Printers. ................. 313 PC 97 Design for Printers .......................... ................ 314 Plug and Play for Printers. ............... 314 Power Management for Print Components . .............. 315 Device Drivers and Installation for Printers . .................... 315 References for Printers ............................ ................ 318 Checklist for Printers ............................. ................ 320 312 PC 97 Design — Part 4 Device Design Guidelines Overview for Printers This section presents the key design issues for printers under Microsoft Windows. Printers and other devices attached to parallel ports should be capable of high- speed, bidirectional data transfers. The design criteria for parallel devices follow those for parallel ports described in the “Serial, Parallel, and Wireless Support” chapter. The PC 97 requirements for printers and parallel ports seek to ensure the following: • Ensure maximum speed for transfer of parallel data between the system and the peripheral. • Ensure a true Plug and Play experience for users. Basic Printer Features This section summarizes the basic hardware requirements for printers for PC 97. Basic Features for IEEE 1394 Printers This section defines requirements for printers that use IEEE 1394. 1. Compliance with PC 97 requirements for IEEE 1394 Required This bus is recommended in PC 97 for support of fast, high-density data transfer. For information about implementing IEEE 1394 for PC 97, see the “IEEE 1394” chapter in Part 3 of this guide. -
From Camac to Wireless Sensor Networks and Time- Triggered Systems and Beyond: Evolution of Computer Interfaces for Data Acquisition and Control
Janusz Zalewski / International Journal of Computing, 15(2) 2016, 92-106 Print ISSN 1727-6209 [email protected] On-line ISSN 2312-5381 www.computingonline.net International Journal of Computing FROM CAMAC TO WIRELESS SENSOR NETWORKS AND TIME- TRIGGERED SYSTEMS AND BEYOND: EVOLUTION OF COMPUTER INTERFACES FOR DATA ACQUISITION AND CONTROL. PART I Janusz Zalewski Dept. of Software Engineering, Florida Gulf Coast University Fort Myers, FL 33965, USA [email protected], http://www.fgcu.edu/zalewski/ Abstract: The objective of this paper is to present a historical overview of design choices for data acquisition and control systems, from the first developments in CAMAC, through the evolution of their designs operating in VMEbus, Firewire and USB, to the latest developments concerning distributed systems using, in particular, wireless protocols and time-triggered architecture. First part of the overview is focused on connectivity aspects, including buses and interconnects, as well as their standardization. More sophisticated designs and a number of challenges are addressed in the second part, among them: bus performance, bus safety and security, and others. Copyright © Research Institute for Intelligent Computer Systems, 2016. All rights reserved. Keywords: Data Acquisition, Computer Control, CAMAC, Computer Buses, VMEbus, Firewire, USB. 1. INTRODUCTION which later became international standards adopted by IEC and IEEE [4]-[7]. The design and development of data acquisition The CAMAC standards played a significant role and control systems has been driven by applications. in developing data acquisition and control The earliest and most prominent of those were instrumentation not only for nuclear research, but applications in scientific experimentation, which also for research in general and for industry as well arose in the early sixties of the previous century, [8]. -
NCR 53C700/53C700-66 SCSI 1/0 Processor Data Manual
NCR 53C700/53C700-66 SCSI 1/0 Processor Data Manual The product(s) described in this publication is a licensed product of NCR Corporation. TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation. It is the policy of NCR Corporation to improve products as new technology, components, software, and firmware become available. NCR Corporation, therefore, reserves the right to change specifications without notice. NCR products are not intended for use in life-suppott appliances, devices, or systems. Use of an NCR product in such applications without the written consent ofthe appropriate NCR officer is prohibited. For information on updates to this or other NCR products, contact the NCR Microelectronic Products Division electronic bulletin board at (719) 596-1649. Copyright ©1993 By NCR Corporation Dayton, Ohio U.S.A. All Rights Reserved Printed in U.S.A. c Preface SCSI Specifications This manual assumes some prior knowledge of current and proposed SCSI standards. For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-1986 (SCSI-I) Global Engineering Documents 2805 McGaw Irvine, CA 92714 (800)-854-7179 or (714) 261-1455 .? Ask for document number X3.131-199X (SCSI-2) ENDL Publications 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia Prentice Hall Englewood Cliffs, NJ 07632 (201) 767-5937 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Inter face NCR Microelectronic Products Division Electronic Bulletin Board (719) 596-1649 The SCSI Electronic Bulletin Board (719) 574-0424 NCR 53C700/53C700-66 Data Manual Revision Record Page No. -
Cable Discharge Event (CDE) Automated Test System Based on TLP Method
Cable Discharge Event (CDE) Automated Test System Based on TLP Method Draft V3-2016.03.18 Wei Huang, Jerry Tichenor Web: www.esdemc.com Email: [email protected] Tel: (+1) 573-202-6411 Fax: (+1) 877-641-9358 Address: 4000 Enterprise Drive, Suite 103, Rolla, MO, 65401 Cable Discharge Event (CDE) Background What is CDE Event ? A Cable Discharge Event (CDE) is electrostatic discharge(s) between metal of a cable connector and the mating cable connector or plug. It is very common in daily life. When CDE happens, transient high current and high voltage pulses are generated into the connector pins and cause potential damage to the system with connector. The pulse characteristic is determined by the cable type, cable length, physical arrangement of the cable and system with connector, and system with connector side circuitry. A Generic CDE System Concept Why understanding CDE robustness is important ? The discharge processes are complicated due to the number of pins involved and their connections to a system. In addition, the occurrence rate and severity of the static discharge is important to design a robust system. Basic System Features: A well repeatable test setup to reproduce cable discharge events Pulse injection level covers different types of cable connections Additional System Features: Automatic computer controlled test for all available connector pins Automatic remove DUT residue charge safely after each pulse safely Integrate current and voltage probes to monitor CDE events on each pin ESDEMC Collected Cable Pins and Practical Passive -
PCI Express Basics & Background
PCI Express® Basics & Background Richard Solomon Synopsys Copyright © 2014, PCI-SIG, All Rights Reserved 1 Acknowledgements Thanks are due to Ravi Budruk, Mindshare, Inc. for much of the material on PCI Express Basics PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 2 Agenda . PCI Express Background . PCI Express Basics . PCI Express Recent Developments PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 3 PCI Express Background PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 4 Revolutionary AND Evolutionary . PCI™ (1992/1993) Revolutionary – Plug and Play jumperless configuration (BARs) – Unprecedented bandwidth • 32-bit / 33MHz – 133MB/sec • 64-bit / 66MHz – 533MB/sec – Designed from day 1 for bus-mastering adapters Evolutionary – System BIOS maps devices then operating systems boot and run without further knowledge of PCI – PCI-aware O/S could gain improved functionality – PCI 2.1 (1995) doubled bandwidth with 66MHz mode PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 5 Revolutionary AND Evolutionary . PCI-X™ (1999) Revolutionary – Unprecedented bandwidth • Up to 1066MB/sec with 64-bit / 133MHz – Registered bus protocol • Eased electrical timing requirements – Brought split transactions into PCI “world” Evolutionary – PCI compatible at hardware *AND* software levels – PCI-X 2.0 (2003) doubled bandwidth • 2133MB/sec at PCI-X 266 and 4266MB/sec at PCI-X 533 PCIe Technology Seminar Copyright © 2014, PCI-SIG, All Rights Reserved 6 Revolutionary AND Evolutionary . PCI Express – aka PCIe® (2002) Revolutionary – Unprecedented bandwidth • x1: up to 1GB/sec in *EACH* direction • x16: up to 16GB/sec in *EACH* direction – “Relaxed” electricals due to serial bus architecture • Point-to-point, low voltage, dual simplex with embedded clocking Evolutionary – PCI compatible at software level • Configuration space, Power Management, etc. -
Industrial I/O Solutions 12-1
Table of Contents / Industrial I/O Solutions 12-1 12 Industrial I/O Solutions 12-4 DAQ-Embedded Computers 12-5 Analog I/O and Multifunction Cards 12-9 Digital I/O and Multifunction Cards 12-15 USB I/O Modules and USB Hubs 12-18 Signal Conditioners and Terminal Boards 12-21 Serial Communication Cards 12-2 Product Introduction Advantech Data Acquisition and Control Solutions As a leading supplier of data acquisition products worldwide, Advantech offers a wide range of I/O devices with various interfaces and functions based on PC technology, from legacy ISA to modern USB and from signal-conditioning to graphical software tools. Advantech’s industrial I/O products are reliable, accurate, affordable, and suitable for many industrial automation applications (e.g., testing and measurement) and laboratory applications (e.g., monitoring, control, machine automation, and product testing). Signal Sensing Signal Conditioning Data Acquisition Signal Conditioners Embedded Computers Advantech’s signal conditioners provide sensor MIC-1800 series units are standalone embedded and signal conditioning on a per-module basis for computers with integrated data acquisition modules various types of sensors or signals. and signal conditioning to provide digital I/O, analog I/O, and counter functions. The palm-sized design with built-in terminals is suitable for space-limited applications. I/O Wiring Terminal Boards SuperSpeed USB 3.0 I/O Modules Equipment Sensor I/O wiring terminal boards offer convenient and SuperSpeed USB 3.0 I/O modules can be leveraged reliable signal wiring for a wide range of Advantech for a diverse range of industrial control applications. -
UPA—Sun'shighperformance Graphicsconnection
UPA—Sun’sHighPerformance GraphicsConnection TechnicalWhitePaper 1999 Sun Microsystems, Inc. All rights reserved. Printed in the United States of America. 901 San Antonio Road, Palo Alto, California 94303 U.S.A. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, Ultra, Sun Elite3D, Sun Enterprise, Java 3D, PGX, Java, SBus, and VIS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. OpenGL is a registered trademark of Silicon Graphics, Inc. THIS PUBLICATION IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOGRAPHICAL ERRORS. CHANGES ARE PERIODICALLY ADDED TO THE INFORMATION HEREIN; THESE CHANGES WILL BE INCORPORATED IN NEW EDITIONS OF THE PUBLICATION. SUN MICROSYSTEMS, INC. MAY MAKE IMPROVEMENTS AND/OR CHANGES IN THE PRODUCT(S) AND/OR THE PROGRAM(S) DESCRIBED IN THIS PUBLICATION AT ANY TIME. Please Recycle Contents Introduction. 1 Analyzing System Design and Application Performance. 2 Design Trade-offs . 2 An Overview of the UPA Interconnect . 3 Scalability, High Bandwidth, and Efficiency . 5 The UPA64S Graphics Bus. 6 Characterizing Application Performance and Bus Traffic. 7 UPA64S and Other Graphics Bus Technologies .