Gate Dielectric Process Technology for the Sub-1 Nm Equivalent Oxide

Bassett (continued from previous page) Gate Dielectric Process Technology for the Sub-1 nm

717 (1947); A. S. Grove, B. E. Deal, Equivalent Oxide Thickness (EOT) Era E. H. Snow, and C. T. Sah, Solid-State Electronics, 8, 145 (1965); and B. E. Deal, M. Sklar, A. S. Grove, and E. H. Future Technical Meetings Snow, J. Electrochem. Soc., 114, 266 by L. Colombo, J. J. Chambers, and H. Niimi (1967). 5. A review of the group’s work is he semiconductor industry is now where t is the physical thickness of constant of Si N , ~7.5) to the higher provided in B. E. Deal, A. S. Grove, E. SiO2 3 4 in its third generation of gate the interface layer, potentially without dielectric constant of the new gate H. Snow, and C. T. Sah, Trans. Metall. May 18-23, 2008 Oct. 4-9, 2009 dielectrics. The first generation nitrogen, t is the physical thickness dielectric (κ ≈ 15-20 for the HfO and Soc. AIME, 233, 524 (1965). For T SiON 2 was the silicon dioxide (SiO ) era from of the SiON film, κ is the dielectric ~4-24 for Hf based HfSiON. This third the papers by Fairchild researchers Phoenix, Arizona Vienna, Austria 2 the early 1960s to about the mid-1990s. constant of the nitrogen containing regime of gate dielectric technology during this time, see “Index to The benefits of SiO noted in the earlier SiO film, and the summation over “i” has also required the replacement of Published Technical Papers,” Bruce 2 2 articles in this issue of Interface included is for layers that do not have a uniform the doped poly-silicon gate electrodes Deal Papers, Collection M1051, Oct. 12-17, 2008 April 25-30, 2010 utilization as: (a) passivation of surface nitrogen profile. by metallic gate electrodes to both Department of Special Collections, dangling bonds and p-n junction Today, the era of SiON films with an reduce the poly-silicon depletion effect Stanford University Libraries, PRiME 2008 Vancouver, BC interfaces, (b) pattern/diffusion masking equivalent oxide thickness (EOT) in the and to improve the work function Stanford, California. ability, and (c) insulator supporting range of ~1.0-1.2 nm have been in mass match between the high-κ and gate 6. Bassett, To the Digital Age, Chapter 2. Honolulu, Hawaii medium for aluminum interconnects production for nearly a decade, meeting electrode materials, itself a significant 7. William E. Harding, IBM J. Res. Dev., Oct. 10-15, 2010 between sections of the integrated demanding transistor and reliability area of research. 25, 651 (1981); D. R. Kerr, J. S. Logan, circuit. In addition, the amorphous requirements. For SiON thickness less The methods utilized for the P. J. Burkhardt, and W. A. Pliskin, May 24-29, 2009 Las Vegas, NV SiO has a large energy gap (~9 eV) than ~1.0 nm, however, it was again fabrication of SiON for the second era IBM J. Res. Dev., 8, 376 (1964); J. M. 2 and a dielectric strength sufficient to found that direct tunneling leakage will be discussed in the first section, Eldridge and P. Balk, Trans. Metall. Soc. San Francisco, support electric field strengths of several currents became excessive through the status of HfSiON gate dielectric in AIME, 242, 539 (1968); J. M. Eldridge, California megavolts/cm, (106 V/cm); the latter the SiON. Scaling below ~1 nm for presented in the second section, and “A Thermochemical Evaluation of is especially critical for the required higher-performance devices and lower the appropriate metal gate issues will the Doping of SiO /Si with P O and 2 2 5 metal-oxide-semiconductor field than ~1.5 nm for lower-power devices briefly be summarized in the third B O ,” Research Report (8 December 2 3 effect transistor (MOSFET) operation. also became limited by poly-silicon section. 1966), IBM Research, Yorktown These latter benefits have enabled depletion as well as gate dielectric Heights, New York; P. Balk, “Effects the semiconductor industry to scale leakage. Initial solutions will require of Hydrogen Annealing on Silicon Silicon Oxynitride transistors down to about the 180 nm either higher content nitrogen in SiON Surfaces,” paper presented at the ECS technology node* , corresponding to an than currently in production or higher- 1965 spring meeting, San Francisco, SiON dielectrics were first SiO thickness of ~3 nm. At about this κ dielectric constant gate materials California, Extended Abstracts of For more information on these future meetings, contact ECS 2 introduced at an EOT of about 3 nm oxide thickness, direct tunneling leakage (κ ~ 10-20). the Electronics Division, Vol. 14, and at that time required less than Tel: 609.737.1902 Fax: 609.737.2743 currents rather than source-drain or Serious attention for alternate, higher Abstract 109, pp. 237-40; P. Balk, P. about 10 atomic percent nitrogen to substrate leakage currents, reached levels dielectric constant materials began in J. Burkhardt, and L. V. Gregor, Proc. www.electrochem.org minimize boron penetration and gate that were a significant portion of the about 1995 and have resulted in an IEEE, 53, 2133 (1965). leakage. Controlled incorporation of allowable device leakage (~ 33%). In extensive literature.3-5 Hafnium-based 8. “CTB Minutes, October 29, 1965,” nitrogen, especially concentration addition, at the sub 3 nm film thicknesses gate dielectrics have emerged as the 4 November 1965, 3, Box TAR 242, and depth profile, was critical to the regime, boron dopant penetration broad industrial choice for the high-κ IBM Technical History Project, IBM introduction of SiON. The key process from the boron-doped p+ poly-silicon gate dielectric material. The principal Archives, Somers, NY. that enabled the industry to introduce electrode through the SiO into the motivation for moving to high-κ gate 9. C. T. Sah, Proc. IEEE, 76, 1301 2 the first reliable SiON gate dielectric The Benefits of Membership Can Be Yours! channel region was a serious issue for dielectrics was the need to reduce the 6 (1988); Robert H. Dennard, IEEE was plasma nitridation of SiO2. pMOSFETs. An extensive literature has direct tunneling gate leakage currents. Trans. Electron Devices, 31, 1549 The advantage of plasma nitridation been published on the increasing SiO2 This was achieved by increasing the gate (1984). Dennard’s patent is Robert of SiO2 is its ability to (a.) control the gate leakage and boron penetration1,2 dielectric’s physical thickness inasmuch H. Dennard, “Field Effect Transistor dielectric layer thickness, (b.) precisely Join now for • Journal of The Electrochemical Society with decreasing oxide thickness and as the direct tunneling leakage current Memory,” U.S. Patent No. 3,387,286, control the content and/or location their impact on continued device is drastically reduced due to its filed 14 July 1967. of the nitrogen, and (c.) improve • Electrochemical and Solid-State Letters scaling as enunciated in Moore’s law. exponential dependence on the physical 10. This section is based on Bassett, To exceptional reliability. Plasma nitrided SiO2 can be The continuance of scaling gate dielectric thickness. Concurrently, the Digital Age, Chapter 5. created by (i.) top surface nitridation, • Interface, the ECS Member methodologies, however, has been the gate dielectric constant, κ, is 11. George Warfield, “Introduction,” (ii.) homogeneous SiON formation, discounts on all achieved by the incorporation of increased. These two concurrent IEEE Trans. Electron Devices, 14, 727 Magazine where the nitrogen is distributed nitrogen (~10 atomic %) in the SiO , changes result in the approximate (1967); Earl S. Schlegel, IEEE Trans. 2 uniformly through the oxide, and • Professional Development and whereby silicon oxynitride (SiON) constancy of the MOSFET’s capacitance, Electron Devices, 14, 728 (1967). ECS publications, (iii.) incorporation of nitrogen at the thicknesses ranging from ~3.0 nm a significant parameter controlling the 12. Bassett, To the Digital Age, Chapter 7. Education Si-SiO2 interface. Simulations have down to ~1.0 nm or so were achieved. speed of the device. This is achieved 13. J. C. Sarace, R. E. Kerwin, D. L. Klein, shown that top surface nitrogen page charges, The introduction of nitrogen in SiO by appropriately adjusting the ratio of and R. Edwards, Solid-State Electronics, • Discounts on Meetings and 2 profiles have better boron blocking to form SiON increases the effective the selected gate dielectric constant, κ, 11, 653 (1968); L. L. Vadasz, A. S. characteristics than other profiles. The Publications dielectric constant, κ. The higher to the dielectric’s physical thickness. Grove, T. A. Rowe, and G. E. Moore, meetings, and short bulk nitrogen concentration in SiON effective dielectric constant leads to a As a result the MOSFET electrically IEEE Spectrum, p. 28 (1969); F. Faggin has to be critically controlled, but even • Honors and Awards Program lower effective gate dielectric thickness behaves as though its gate dielectric and T. Klein, Solid-State Electronics, more critical is the concentration of N courses. that is referred to as the equivalent oxide thickness is smaller than its physical 13, 1125 (1970). • Career Center atoms at the Si-dielectric interface. thickness (EOT) described in general thickness (to reduce direct tunneling 14. Brian Santo, IEEE Spectrum, p. 108 The concentration of nitrogen by Eq. 1. leakage current) by the ratio of the at the interface has to follow the (November 1988). n dielectric constant of SiON (generally bonding constraint theory7 in order 15. Gordon E. Moore, Daedalus, 125, 55 EOT= + 3.9 (tSiON)i tSiO2 (1) slightly more than SiO ’s value of ~3.9 (Spring 1996). S ki 2 to minimize defects. According to i but significantly less than the dielectric 16. R. H. Dennard, F. H. Gaensslen, H-N. the bonding constraint theory, whose Yu, V. L. Rideout, E. Bassous, and A. www.electrochem.org R. LeBlanc, IEEE J. Solid-State Circuits, * The technology node refers to the metal line-to-line spacing—½ pitch—for a particular DRAM generation. The physical channel length 9, 256 (1974). for a logic chip consonant with the DRAM generation is about 45% of the technology node as discussed in the International Technology Roadmap for Semiconductors, ITRS.

50 The Electrochemical Society Interface • Fall 2007 The Electrochemical Society Interface • Fall 2007 51 Colombo, et al. (continued from previous page) criteria were originally established for the formation of low defect density glasses, the maximum average number of bonds (Nav) of ~3 is the limit for a low defect density dielectric. If a thin SiO2 layer (~0.5nm, about one molecular layer) is formed between the Si substrate and Si3N4, the average bonding coordination is reduced to 3.0, and is essentially the same as for the Si-SiO2 interfaces leading to significantly improved electrical performance. Monolayer-level nitrogen incorporation 14 -2 (~7 x 10 cm ) to form Si3-N bonding configurations in 8 the vicinity of the Si-SiO2 interface reduces gate leakage by approximately tenfold compared to pure SiO2 as shown in Fig. 9 1. The incorporation of nitrogen near the Si-SiO2 interface leads to reduced interfacial sub-oxide bonding which defines the transition region between the Si substrate and bulk SiO2. The modified interface structure results in the reduction of gate tunneling currents by increasing the tunneling barrier height. Although monolayer level incorporation of nitrogen at the interface improves leakage characteristics, further scaling will require higher bulk nitrogen levels. Increasing the nitrogen concentration in the bulk of the film by either direct nitridation or nitridation of the SiO2 base oxide reduces gate leakage. In the case of (SiO2)1-x(Si3N4)x solution, the gate leakage can be reduced by as much as a factor of Fig. 4. TEM micrographs of (a) Si/SiO /HfO /Poly Si where the maximum temperature was 700oC and (b) Si/SiO /HfSiON/Poly Si after 1050oC about 100.10 Figure 2 shows leakage current as a function of 2 2 2 annealing. silicon nitride fraction in SiON.11 The leakage reduction is clearly demonstrated for the solid solution in the vicinity of Fig. 1. Gate leakage current density as a function of gate the 50-50% composition point. Figure 3 further shows that the A few research groups have reported the amorphous nature of HfSiON.14,15 interface.18 The improvement in charge voltage for 2.0 and 3.0 nm EOT thick gate tunneling leakage current of SiON can indeed be decreased by increasing 9 that HfSiON is structurally stable, has a Thus, in general, the idea of creating trapping for the thinner HfON film currents compared to SiO2 (filled symbols). the nitrogen concentration in SiON to ~20 at.% as an example. high dielectric constant, has low charge HfSiON is that hafnium is added to was also followed by electron mobility Nitrogen concentrations in excess of ~20 at.%, however, results trapping, and high electron and hole silicon dioxide to increase the dielectric improvements (approaching ~ 90% of in large shifts in the threshold voltage which can be observed in mobility, typically ~90% and > 90% constant and nitrogen is added to the SiO electron mobility at an electric both nMOSFET and pMOSFET devices with the pMOSFET shift 2 of SiO universal mobility curve at an stabilize the material structure. An field of ~ 1 MV/cm). The presence of being larger. In addition, the leakage reduction of SiON with 2 electric field of 1 MV/cm, for HfSiON additional challenge observed with HfO a thin SiO or SiON interface and the high nitrogen is not sufficient for scaling dielectrics beyond the 2 2 having Hf and N concentrations of deposited by atomic layer deposition addition of Si to HfON have in general 45 nm technology node and high-κ is necessary to meet the ~11 at.% and 14 at.%, respectively. was large C-V hysterisis for n-channel been found to improve mobility as scaling requirements.12 The addition of ~14 at.% nitrogen to devices as a result of a high density shown in Figure 6 and decrease charge HfSiO (Hf ~11 at%) to form HfSiON was of trapped charge in the bulk of the trapping.18 The industry recognized the High-κ Dielectric Constant Materials found to stabilize the structure of the dielectric film.16 HfSiON on the other many benefits of HfSiON as a high-κ films such that the material remains hand has shown significantly lower gate dielectric and devoted considerable o The semiconductor community has been searching for amorphous up to 1100 C for low Hf trapped charge than HfO2 as shown in resources in order to introduce poly-Si/ high-κ gate dielectrics since about 1995. It appears that, after concentrations.14 Figure 4b shows a Figure 5.17 Subsequently, improvements HfSiON gate stack into the conventional investigating a multitude of materials, Hf-based gate dielectrics TEM micrograph of poly-Si/HfSiON/ in charge trapping were observed for flow. However, pMOSFET with poly- have emerged as the “final” choice for high-κ material. The Si after annealing at 1050oC where very thin hafnium oxynitride (HfON) Si gate electrode devices suffered principal motivation for moving to high-κ gate dielectrics no lattice fringes are observed due to on thin SiO2, (EOT ≤ 1.1 nm) with from a high threshold voltage (VT), a was the need to reduce direct tunneling leakage currents as the amorphous nature of the films. X- the improvement being attributed to a phenomenon that became known as discussed earlier. Figure 3 shows a comparison of the gate ray diffraction and Fourier Transform lower number of total defects in HfON pMOSFET VT offset; threshold voltages leakage of SiON and hafnium silicon oxynitride (HfSiON) as Infrared Spectroscopy data also support and the formation of a “silicate” at the offset as high as 0.5V have been observed a function of composition indicating that HfSiON is scalable beyond 1 nm EOT with much lower gate leakage than currently Fig. 2. Effect of nitrogen on the tunneling current of achieved with SiON. Lower leakage is clearly a benefit of the (SiO2)(1-x)•(Si3N4)(x) showing that the gate leakage can be reduced (a) (b) by about a factor of 100 by optimizing the nitrogen concentration physically thicker high-κ gate dielectrics, but only to first order (continuous curve is theory).11 because many other properties must be satisfied before adopting any specific high-κ material. One of the key properties of SiO2 and SiON is their amorphous state even after annealing at temperatures well above the typical complementary metal-oxide-semiconductor (CMOS) processing temperatures (~1050oC). It is generally agreed that amorphous gate dielectrics are preferred over crystalline materials. For example, hafnium oxide (HfO2) and hafnium silicon oxide (HfSiO) were key gate dielectrics studied in the early stages of high-κ development, but both have relatively low crystallization temperatures. Figure 4a shows a cross-sectional transmission electron micrograph (TEM) of HfO2 that clearly shows ordering, and indication of crystallization in the film after poly silicon deposition at about 700oC. HfSiO also crystallizes at temperatures lower than the maximum CMOS processing temperatures and, in addition, also suffers from phase separation that results in crystalline HfO2 phases in a matrix of HfSiO with a lower Hf concentration than the original as deposited uniform HfSiO.13 These results are less than desirable because polycrystalline films contain point defects and grain boundaries that place significant limitations on the device reliability. Therefore, more Fig. 5. Pulsed ID-VG measurements on nMOSFETs. Measurement involves applying a pulse of voltage at the gate terminal and calculating drain current by Fig. 3. Gate leakage of SiON and HfSiON as a function of EOT and .17 thermally stable dielectrics were preferable. measuring voltage across the drain terminal. (a) HfO2 and (b) HfSiON gate dielectrics composition.

52 The Electrochemical Society Interface • Fall 2007 The Electrochemical Society Interface • Fall 2007 53 Colombo, et al. (continued from previous page) criteria were originally established for the formation of low defect density glasses, the maximum average number of bonds (Nav) of ~3 is the limit for a low defect density dielectric. If a thin SiO2 layer (~0.5nm, about one molecular layer) is formed between the Si substrate and Si3N4, the average bonding coordination is reduced to 3.0, and is essentially the same as for the Si-SiO2 interfaces leading to significantly improved electrical performance. Monolayer-level nitrogen incorporation 14 -2 (~7 x 10 cm ) to form Si3-N bonding configurations in 8 the vicinity of the Si-SiO2 interface reduces gate leakage by approximately tenfold compared to pure SiO2 as shown in Fig. 9 1. The incorporation of nitrogen near the Si-SiO2 interface leads to reduced interfacial sub-oxide bonding which defines the transition region between the Si substrate and bulk SiO2. The modified interface structure results in the reduction of gate tunneling currents by increasing the tunneling barrier height. Although monolayer level incorporation of nitrogen at the interface improves leakage characteristics, further scaling will require higher bulk nitrogen levels. Increasing the nitrogen concentration in the bulk of the film by either direct nitridation or nitridation of the SiO2 base oxide reduces gate leakage. In the case of (SiO2)1-x(Si3N4)x solution, the gate leakage can be reduced by as much as a factor of Fig. 4. TEM micrographs of (a) Si/SiO /HfO /Poly Si where the maximum temperature was 700oC and (b) Si/SiO /HfSiON/Poly Si after 1050oC about 100.10 Figure 2 shows leakage current as a function of 2 2 2 annealing. silicon nitride fraction in SiON.11 The leakage reduction is clearly demonstrated for the solid solution in the vicinity of Fig. 1. Gate leakage current density as a function of gate the 50-50% composition point. Figure 3 further shows that the A few research groups have reported the amorphous nature of HfSiON.14,15 interface.18 The improvement in charge voltage for 2.0 and 3.0 nm EOT thick gate tunneling leakage current of SiON can indeed be decreased by increasing 9 that HfSiON is structurally stable, has a Thus, in general, the idea of creating trapping for the thinner HfON film currents compared to SiO2 (filled symbols). the nitrogen concentration in SiON to ~20 at.% as an example. high dielectric constant, has low charge HfSiON is that hafnium is added to was also followed by electron mobility Nitrogen concentrations in excess of ~20 at.%, however, results trapping, and high electron and hole silicon dioxide to increase the dielectric improvements (approaching ~ 90% of in large shifts in the threshold voltage which can be observed in mobility, typically ~90% and > 90% constant and nitrogen is added to the SiO electron mobility at an electric both nMOSFET and pMOSFET devices with the pMOSFET shift 2 of SiO universal mobility curve at an stabilize the material structure. An field of ~ 1 MV/cm). The presence of being larger. In addition, the leakage reduction of SiON with 2 electric field of 1 MV/cm, for HfSiON additional challenge observed with HfO a thin SiO or SiON interface and the high nitrogen is not sufficient for scaling dielectrics beyond the 2 2 having Hf and N concentrations of deposited by atomic layer deposition addition of Si to HfON have in general 45 nm technology node and high-κ is necessary to meet the ~11 at.% and 14 at.%, respectively. was large C-V hysterisis for n-channel been found to improve mobility as scaling requirements.12 The addition of ~14 at.% nitrogen to devices as a result of a high density shown in Figure 6 and decrease charge HfSiO (Hf ~11 at%) to form HfSiON was of trapped charge in the bulk of the trapping.18 The industry recognized the High-κ Dielectric Constant Materials found to stabilize the structure of the dielectric film.16 HfSiON on the other many benefits of HfSiON as a high-κ films such that the material remains hand has shown significantly lower gate dielectric and devoted considerable o The semiconductor community has been searching for amorphous up to 1100 C for low Hf trapped charge than HfO2 as shown in resources in order to introduce poly-Si/ high-κ gate dielectrics since about 1995. It appears that, after concentrations.14 Figure 4b shows a Figure 5.17 Subsequently, improvements HfSiON gate stack into the conventional investigating a multitude of materials, Hf-based gate dielectrics TEM micrograph of poly-Si/HfSiON/ in charge trapping were observed for flow. However, pMOSFET with poly- have emerged as the “final” choice for high-κ material. The Si after annealing at 1050oC where very thin hafnium oxynitride (HfON) Si gate electrode devices suffered principal motivation for moving to high-κ gate dielectrics no lattice fringes are observed due to on thin SiO2, (EOT ≤ 1.1 nm) with from a high threshold voltage (VT), a was the need to reduce direct tunneling leakage currents as the amorphous nature of the films. X- the improvement being attributed to a phenomenon that became known as discussed earlier. Figure 3 shows a comparison of the gate ray diffraction and Fourier Transform lower number of total defects in HfON pMOSFET VT offset; threshold voltages leakage of SiON and hafnium silicon oxynitride (HfSiON) as Infrared Spectroscopy data also support and the formation of a “silicate” at the offset as high as 0.5V have been observed a function of composition indicating that HfSiON is scalable beyond 1 nm EOT with much lower gate leakage than currently Fig. 2. Effect of nitrogen on the tunneling current of achieved with SiON. Lower leakage is clearly a benefit of the (SiO2)(1-x)•(Si3N4)(x) showing that the gate leakage can be reduced (a) (b) by about a factor of 100 by optimizing the nitrogen concentration physically thicker high-κ gate dielectrics, but only to first order (continuous curve is theory).11 because many other properties must be satisfied before adopting any specific high-κ material. One of the key properties of SiO2 and SiON is their amorphous state even after annealing at temperatures well above the typical complementary metal-oxide-semiconductor (CMOS) processing temperatures (~1050oC). It is generally agreed that amorphous gate dielectrics are preferred over crystalline materials. For example, hafnium oxide (HfO2) and hafnium silicon oxide (HfSiO) were key gate dielectrics studied in the early stages of high-κ development, but both have relatively low crystallization temperatures. Figure 4a shows a cross-sectional transmission electron micrograph (TEM) of HfO2 that clearly shows ordering, and indication of crystallization in the film after poly silicon deposition at about 700oC. HfSiO also crystallizes at temperatures lower than the maximum CMOS processing temperatures and, in addition, also suffers from phase separation that results in crystalline HfO2 phases in a matrix of HfSiO with a lower Hf concentration than the original as deposited uniform HfSiO.13 These results are less than desirable because polycrystalline films contain point defects and grain boundaries that place significant limitations on the device reliability. Therefore, more Fig. 5. Pulsed ID-VG measurements on nMOSFETs. Measurement involves applying a pulse of voltage at the gate terminal and calculating drain current by Fig. 3. Gate leakage of SiON and HfSiON as a function of EOT and .17 thermally stable dielectrics were preferable. measuring voltage across the drain terminal. (a) HfO2 and (b) HfSiON gate dielectrics composition.

52 The Electrochemical Society Interface • Fall 2007 The Electrochemical Society Interface • Fall 2007 53 Colombo, et al. device VT. Setting the pMOSFET work budget, the replacement process flow Hiroaki “Hiro” Niimi is a Group Annual. 2003 IEEE International, p. (continued from previous page) function near the band edge has proven may be the most likely integration Member of Technical Staff at Texas 41 (2003). to be more difficult, as compared to scheme that will enable the introduction Instruments. He is the author or co- 17. A. Shanware, M. R. Visokay, J. J. for pMOSFET devices. The pMOSFET VT nMOSFET, at technologically relevant of metal gates, in conjunction with the author of over 80 refereed publication Chambers, A. L. P. Rotondaro, J. offset quickly became a showstopper for EOTs of ~ 1 nm. As the EOT decreases high-κ gate dielectric, that can provide in journals and conference proceedings McPherson, and L. Colombo, in producing high performance devices with the desired in the field of silicon dioxide based Electron Devices Meeting, 2003, IEDM poly-Si/HfSiON devices, which threshold voltages.26 gate dielectrics, one book chapter, and ‘03 Technical Digest, IEEE International, required lower VT. Indeed, a plethora of over 10 U.S. patents in area of plasma p. 38.6.1 (2003). modifications to the nitridation for gate dielectrics. He may 18. P. D. Kirsch, M. A. Quevedo-Lopez, Metal Gate Electrodes gate first or replacement be reached at [email protected]. S. A. Krishnan, B. H. Lee, G. Pant, gate methodologies have M. J. Kim, R. M. Wallace, and B. E. been and continue to be As a result of the pMOSFET References Gnade, Appl. Phys. Lett., 89, 242909 discussed in the scientific V offset found in poly-Si/ (2006). T literature. high-k gate stacks, the industry 19. S. Park, L. Colombo, Y. Nishi, and K. 1. P. A. Packan, Pushing the Limits, Cho, Appl. Phys. Lett., 86, 073118-3 initiated a significant effort Science, 285, 2079 (1999). to the selection of nMOSFET Summary (2005). 2. D. A. Muller, T. Sorsch, S. Moccio, F. 20. C.-H. Lu, G. M. T. Wong, M. D. Deal, and pMOSFET “metal” gate H. Baumann, K. Evans-Lutterodt, and electrodes in order to obtain As we approach the W. Tsai, P. Majhi, C. O. Chui, M. R. G. Timp, Nature, 399, 759 (1999). Visokay, J. J. Chambers, L. Colombo, low threshold voltages (~ limits of SiON, HfSiON 3. High Dielectric Constant Materials: κ B. M. Clemens, and Y. Nishi, IEEE 0.25 eV) and to minimize the high- gate dielectrics VLSI MOSFET Applications (Springer depletion effect found in poly- with metal gate electrodes Electron Device Lett., 26, 445 (2005). Series in Advanced Microelectronics), 21. H. Y. Yu, C. Ren, Y.-C. Yeo, J. F. Kang, Si electrodes. Researchers have are being incorporated H. R. Huff and D. C. Gilmer, Editors, investigated many metal gate into some devices at the X. P. Wang, H. H. H. Ma, M.-F. Li, D. Berlin-Heidelberg-New York (2005). S. H. Chan, and D.-L. Kwong, IEEE electrode candidates, but the 45 nm technology node. 4. Materials Fundamentals of Gate industry has not converged Hafnium-based high-κ Electron Device Lett., 25, 337 (2004). Dielectrics, A. A. Demkov and A. 22. H. Alshareef, H. Harris, H. Wen, on one set of materials at dielectrics will usher in Navrotsky, Editors, Springer the present time. Three the third generation of C. Park, C. Huffman, K. Choi, H. Dordretch, Berlin, Heidelberg, New Luan, P. Majhi, B. Lee, R. Jammy, D. basic methodologies have CMOS gate dielectrics York (2005). and will enable the sub-1 Lichtenwalner, J. Jur, and A. Kingon, been pursued to set the Fig. 6. HfON and HfSiON electron mobility as a function of EOT for 5. High-k Gate Dielectrics, M. Houssa, 18 in VLSI Technology, 2006, Digest of work function: (i.) selection Si/SiO2/HfON, Si/SiO2/HfSiON, and Si/SiON/HfSiON. nm EOT era. Metal gates Editor, Institute of Physics Publishing, Technical Papers, 2006 Symposium, p. of a metal with appropriate will replace doped poly Bristol, UK (2004). vacuum work function, silicon electrodes to scale 7 (2006). 6. S. V. Hattangady, H. Niimi, and G. 23. H. N. Alshareef, H. F. Luan, K. Choi, (ii.) modification of the the inversion dielectric Lucovsky, Appl. Phys. Lett., 66, 3495 metal/dielectric interface, and (iii.) toward 1 nm, the work function thickness to levels not achievable by H. R. Harris, H. C. Wen, M. A. decreases to unacceptable values; this (1995). Quevedo-Lopez, P. Majhi, and B. modification of the gate dielectric using polysilicon. The sub-1 nm EOT era would 7. G. Lucovsky, Y. Wu, H. Niimi, V. effect is referred to as pMOSFET VT roll- H. Lee, Appl. Phys. Lett., 88, 112114 non-band edge metals. not have been possible without the Misra, and J. C. Phillips, Appl. Phys. The discrepancy between the vacuum off, which was found to increase with extensive knowledge gained perfecting (2006). increasing process temperature and/or Lett., 74, 2005 (1999). 24. A. Chatterjee, R. A. Chapman, G. work function and that observed in the previous generations of SiO2 and increasing metal (Hf) concentration in 8. H. Niimi and G. Lucovsky, J. Vac. Sci. Dixit, J. Kuehne, S. Hattangady, H. transistor devices is a result of poor SiON dielectrics. Tech. A, 17, 3185 (1999). control of the material composition at the dielectric. Yang, G. A. Brown, R. Aggarwal, The data on the effect of process 9. H. Niimi and G. Lucovsky, J. Vac. Sci. U. Erdogan, Q. He, M. Hanratty, D. the interface between the gate dielectric About the Authors Tech. B: Microelectronics and Nanometer and the metal gate electrode interface. temperature on work function have Rogers, S. Murtaza, S. J. Fang, R. Kraft, been clear for a few years now, although Structures, 17, 2610 (1999). A. L. P. Rotondaro, J. C. Hu, M. Terry, The placement of low work function Luigi Colombo is a TI Fellow in the the advantage of the conventional 10. H. Yang and G. Lucovsky, in Technical W.Lee, C. Fernando, A. Konecni, metals or high work function metals at Silicon Technology Development Group transistor flow has kept focus on gate Digest of IEEE International Electron G. Wells, D. Frystak, C. Bowen, M. the metal/dielectric interface have been at Texas Instruments in Dallas, TX. His first approaches. However, given the Device Meeting, The Institute of Rodder, and I.-C. Chen, in Technical found to change the effective work areas of expertise and interest include need to reduce gate dielectric leakage, Electrical and Electronics Engineers, Digest of IEEE International Electron function of the MOSFET and thus VT of deposition and/or growth of infrared reduce metal gate depletion and the p. 245, Washington, DC (1999). Device Meeting, p. 821 (1997). the device but this is also dependent on materials such as II-VI compounds, multi- 11. G. Lucovsky and J. L. Whitten, in 19-21 nature of the metal/dielectric interface 25. W. P. Maszara, Z. Krivokapic, P. King, the thermal budget. The reactions component oxides for capacitor gate chemistry, the benefits of a lower High Dielectric Constant Materials: J.-S. Goo, and M.-R. Lin, in Electron between the dielectric and metals and dielectric applications, ferromagnetic thermal budget process needs to be VLSI MOSFET Applications, H. R. Huff Devices Meeting, 2002, IEDM ‘02, the charges in the dielectrics have semiconductors such as chalcogenide implemented in order to integrate and D. C. Gilmer, Editors, 11, p. 315 Digest. International, p. 367 (2002). made setting the work function at the spinels, and nitrided SiO . He is the the high-κ/metal gate stack into the 2 Springer-Verlag, Berlin Heidelberg 26. S. Yamaguchi, K. Tai, T. Hirano, band edges difficult. The most effective author and co-author of over 125 transistor flow. (2005). T. Ando, S. Hiyama, J. Wang, Y. method to date of setting the nMOSFET publications in journals and conference One such approach is referred to 12. International Technology Roadmap Hagimoto, Y. Nagahama, T. Kato, K. work function has been modification of proceedings, 3 book chapters, and holds as the replacement gate process flow, of Semiconductors, in http://www. Nagano, M. Yamanaka, S. Terauchi, the gate dielectric by the introduction over 50 U.S. patents. He may be reached which enables decoupling the junction itrs.net/Links/2007Summer/2007_ S. Kanda, R. Yamamoto, Y. Tateshita, of lanthanide metals, with a non-band at [email protected]. Public_SF.htm (2007). edge metal electrode.22 In this case the formation from the dielectric/metal Y. Tagawa, H. Iwamoto, M. Saito, gate formation process.24 In this flow, 13. S. Ramanathan, P. C. McIntyre, J. N. Nagashima, and S. Kadomura, lanthanide metal or metal oxide reacts Jim Chambers is a Member of the a sacrificial gate electrode (e.g. poly Luning, P. S. Lysaght, Y. Yang, Z. in VLSI Technology, 2006, Digest of with the gate dielectric thus changing Technical Staff at Texas Instruments in Si) and a sacrificial gate dielectric, e.g., Chen, and S. Stemmer, J. Electrochem. Technical Papers, 2006 Symposium, p. the charge state of the dielectric. Work Dallas, TX. His current duties include Soc., 150, F173 (2003). SiO2, may be used and then removed 152 (2006). functions of 4.05 to 4.1 eV have been integrating high-k and metal gate 14. M. R. Visokay, J. J. Chambers, A. L. reported with the expected device after all the junctions are formed. Subsequently, the gate dielectric and/or electrode for the 45 nm node. Jim is the P. Rotondaro, A. Shanware, and L. threshold voltage of about 0.25 eV for author of over 30 publications and one Colombo, Appl. Phys. Lett., 80, 3183 nMOSFETs. Incorporation of Al in the the metal were deposited to form the gate electrode stack. A related process book chapter, and holds over 25 U.S. (2002). gate dielectric has also been used to shift patents in the area of SiON, high-k gate 15. M. A. Quevedo-Lopez, J. J. Chambers, the work function of pMOSFET devices that has been used to form the metal κ dielectrics, and metal gate electrodes. M. R. Visokay, A. Shanware, and toward the band edge but mobility gate electrode on high- is the NiSi Full Silicidation process (FUSI).25 The He is a member of the technical L. Colombo, Appl. Phys. Lett., 87, degradation has been observed as result committee for the Semiconductor 012902 (2005). 23 FUSI process has shown some very of Al diffusion into the substrate. The Interface Specialists Conference. He 16. A. Kerber, E. Cartier, L. Pantisano, M. data to date are clear in one respect; that encouraging results by using lanthanide metals for nMOSFET and noble metals may be reached at [email protected]. Rosmeulen, R. Degraeve, T. Kauerauf, is, metal gates reduce gate depletion, G. Groeseneken, H. E. Maes, and but it is challenging to obtain the for pMOSFET at the gate dielectric/FUSI interface. Because of its low thermal U. Schwalke, in Reliability Physics correct work functions that result in low Symposium Proceedings, 2003, 41st

54 The Electrochemical Society Interface • Fall 2007 The Electrochemical Society Interface • Fall 2007 55 Colombo, et al. device VT. Setting the pMOSFET work budget, the replacement process flow Hiroaki “Hiro” Niimi is a Group Annual. 2003 IEEE International, p. (continued from previous page) function near the band edge has proven may be the most likely integration Member of Technical Staff at Texas 41 (2003). to be more difficult, as compared to scheme that will enable the introduction Instruments. He is the author or co- 17. A. Shanware, M. R. Visokay, J. J. for pMOSFET devices. The pMOSFET VT nMOSFET, at technologically relevant of metal gates, in conjunction with the author of over 80 refereed publication Chambers, A. L. P. Rotondaro, J. offset quickly became a showstopper for EOTs of ~ 1 nm. As the EOT decreases high-κ gate dielectric, that can provide in journals and conference proceedings McPherson, and L. Colombo, in producing high performance devices with the desired in the field of silicon dioxide based Electron Devices Meeting, 2003, IEDM poly-Si/HfSiON devices, which threshold voltages.26 gate dielectrics, one book chapter, and ‘03 Technical Digest, IEEE International, required lower VT. Indeed, a plethora of over 10 U.S. patents in area of plasma p. 38.6.1 (2003). modifications to the nitridation for gate dielectrics. He may 18. P. D. Kirsch, M. A. Quevedo-Lopez, Metal Gate Electrodes gate first or replacement be reached at [email protected]. S. A. Krishnan, B. H. Lee, G. Pant, gate methodologies have M. J. Kim, R. M. Wallace, and B. E. been and continue to be As a result of the pMOSFET References Gnade, Appl. Phys. Lett., 89, 242909 discussed in the scientific V offset found in poly-Si/ (2006). T literature. high-k gate stacks, the industry 19. S. Park, L. Colombo, Y. Nishi, and K. 1. P. A. Packan, Pushing the Limits, Cho, Appl. Phys. Lett., 86, 073118-3 initiated a significant effort Science, 285, 2079 (1999). to the selection of nMOSFET Summary (2005). 2. D. A. Muller, T. Sorsch, S. Moccio, F. 20. C.-H. Lu, G. M. T. Wong, M. D. Deal, and pMOSFET “metal” gate H. Baumann, K. Evans-Lutterodt, and electrodes in order to obtain As we approach the W. Tsai, P. Majhi, C. O. Chui, M. R. G. Timp, Nature, 399, 759 (1999). Visokay, J. J. Chambers, L. Colombo, low threshold voltages (~ limits of SiON, HfSiON 3. High Dielectric Constant Materials: κ B. M. Clemens, and Y. Nishi, IEEE 0.25 eV) and to minimize the high- gate dielectrics VLSI MOSFET Applications (Springer depletion effect found in poly- with metal gate electrodes Electron Device Lett., 26, 445 (2005). Series in Advanced Microelectronics), 21. H. Y. Yu, C. Ren, Y.-C. Yeo, J. F. Kang, Si electrodes. Researchers have are being incorporated H. R. Huff and D. C. Gilmer, Editors, investigated many metal gate into some devices at the X. P. Wang, H. H. H. Ma, M.-F. Li, D. Berlin-Heidelberg-New York (2005). S. H. Chan, and D.-L. Kwong, IEEE electrode candidates, but the 45 nm technology node. 4. Materials Fundamentals of Gate industry has not converged Hafnium-based high-κ Electron Device Lett., 25, 337 (2004). Dielectrics, A. A. Demkov and A. 22. H. Alshareef, H. Harris, H. Wen, on one set of materials at dielectrics will usher in Navrotsky, Editors, Springer the present time. Three the third generation of C. Park, C. Huffman, K. Choi, H. Dordretch, Berlin, Heidelberg, New Luan, P. Majhi, B. Lee, R. Jammy, D. basic methodologies have CMOS gate dielectrics York (2005). and will enable the sub-1 Lichtenwalner, J. Jur, and A. Kingon, been pursued to set the Fig. 6. HfON and HfSiON electron mobility as a function of EOT for 5. High-k Gate Dielectrics, M. Houssa, 18 in VLSI Technology, 2006, Digest of work function: (i.) selection Si/SiO2/HfON, Si/SiO2/HfSiON, and Si/SiON/HfSiON. nm EOT era. Metal gates Editor, Institute of Physics Publishing, Technical Papers, 2006 Symposium, p. of a metal with appropriate will replace doped poly Bristol, UK (2004). vacuum work function, silicon electrodes to scale 7 (2006). 6. S. V. Hattangady, H. Niimi, and G. 23. H. N. Alshareef, H. F. Luan, K. Choi, (ii.) modification of the the inversion dielectric Lucovsky, Appl. Phys. Lett., 66, 3495 metal/dielectric interface, and (iii.) toward 1 nm, the work function thickness to levels not achievable by H. R. Harris, H. C. Wen, M. A. decreases to unacceptable values; this (1995). Quevedo-Lopez, P. Majhi, and B. modification of the gate dielectric using polysilicon. The sub-1 nm EOT era would 7. G. Lucovsky, Y. Wu, H. Niimi, V. effect is referred to as pMOSFET VT roll- H. Lee, Appl. Phys. Lett., 88, 112114 non-band edge metals. not have been possible without the Misra, and J. C. Phillips, Appl. Phys. The discrepancy between the vacuum off, which was found to increase with extensive knowledge gained perfecting (2006). increasing process temperature and/or Lett., 74, 2005 (1999). 24. A. Chatterjee, R. A. Chapman, G. work function and that observed in the previous generations of SiO2 and increasing metal (Hf) concentration in 8. H. Niimi and G. Lucovsky, J. Vac. Sci. Dixit, J. Kuehne, S. Hattangady, H. transistor devices is a result of poor SiON dielectrics. Tech. A, 17, 3185 (1999). control of the material composition at the dielectric. Yang, G. A. Brown, R. Aggarwal, The data on the effect of process 9. H. Niimi and G. Lucovsky, J. Vac. Sci. U. Erdogan, Q. He, M. Hanratty, D. the interface between the gate dielectric About the Authors Tech. B: Microelectronics and Nanometer and the metal gate electrode interface. temperature on work function have Rogers, S. Murtaza, S. J. Fang, R. Kraft, been clear for a few years now, although Structures, 17, 2610 (1999). A. L. P. Rotondaro, J. C. Hu, M. Terry, The placement of low work function Luigi Colombo is a TI Fellow in the the advantage of the conventional 10. H. Yang and G. Lucovsky, in Technical W.Lee, C. Fernando, A. Konecni, metals or high work function metals at Silicon Technology Development Group transistor flow has kept focus on gate Digest of IEEE International Electron G. Wells, D. Frystak, C. Bowen, M. the metal/dielectric interface have been at Texas Instruments in Dallas, TX. His first approaches. However, given the Device Meeting, The Institute of Rodder, and I.-C. Chen, in Technical found to change the effective work areas of expertise and interest include need to reduce gate dielectric leakage, Electrical and Electronics Engineers, Digest of IEEE International Electron function of the MOSFET and thus VT of deposition and/or growth of infrared reduce metal gate depletion and the p. 245, Washington, DC (1999). Device Meeting, p. 821 (1997). the device but this is also dependent on materials such as II-VI compounds, multi- 11. G. Lucovsky and J. L. Whitten, in 19-21 nature of the metal/dielectric interface 25. W. P. Maszara, Z. Krivokapic, P. King, the thermal budget. The reactions component oxides for capacitor gate chemistry, the benefits of a lower High Dielectric Constant Materials: J.-S. Goo, and M.-R. Lin, in Electron between the dielectric and metals and dielectric applications, ferromagnetic thermal budget process needs to be VLSI MOSFET Applications, H. R. Huff Devices Meeting, 2002, IEDM ‘02, the charges in the dielectrics have semiconductors such as chalcogenide implemented in order to integrate and D. C. Gilmer, Editors, 11, p. 315 Digest. International, p. 367 (2002). made setting the work function at the spinels, and nitrided SiO . He is the the high-κ/metal gate stack into the 2 Springer-Verlag, Berlin Heidelberg 26. S. Yamaguchi, K. Tai, T. Hirano, band edges difficult. The most effective author and co-author of over 125 transistor flow. (2005). T. Ando, S. Hiyama, J. Wang, Y. method to date of setting the nMOSFET publications in journals and conference One such approach is referred to 12. International Technology Roadmap Hagimoto, Y. Nagahama, T. Kato, K. work function has been modification of proceedings, 3 book chapters, and holds as the replacement gate process flow, of Semiconductors, in http://www. Nagano, M. Yamanaka, S. Terauchi, the gate dielectric by the introduction over 50 U.S. patents. He may be reached which enables decoupling the junction itrs.net/Links/2007Summer/2007_ S. Kanda, R. Yamamoto, Y. Tateshita, of lanthanide metals, with a non-band at [email protected]. Public_SF.htm (2007). edge metal electrode.22 In this case the formation from the dielectric/metal Y. Tagawa, H. Iwamoto, M. Saito, gate formation process.24 In this flow, 13. S. Ramanathan, P. C. McIntyre, J. N. Nagashima, and S. Kadomura, lanthanide metal or metal oxide reacts Jim Chambers is a Member of the a sacrificial gate electrode (e.g. poly Luning, P. S. Lysaght, Y. Yang, Z. in VLSI Technology, 2006, Digest of with the gate dielectric thus changing Technical Staff at Texas Instruments in Si) and a sacrificial gate dielectric, e.g., Chen, and S. Stemmer, J. Electrochem. Technical Papers, 2006 Symposium, p. the charge state of the dielectric. Work Dallas, TX. His current duties include Soc., 150, F173 (2003). SiO2, may be used and then removed 152 (2006). functions of 4.05 to 4.1 eV have been integrating high-k and metal gate 14. M. R. Visokay, J. J. Chambers, A. L. reported with the expected device after all the junctions are formed. Subsequently, the gate dielectric and/or electrode for the 45 nm node. Jim is the P. Rotondaro, A. Shanware, and L. threshold voltage of about 0.25 eV for author of over 30 publications and one Colombo, Appl. Phys. Lett., 80, 3183 nMOSFETs. Incorporation of Al in the the metal were deposited to form the gate electrode stack. A related process book chapter, and holds over 25 U.S. (2002). gate dielectric has also been used to shift patents in the area of SiON, high-k gate 15. M. A. Quevedo-Lopez, J. J. Chambers, the work function of pMOSFET devices that has been used to form the metal κ dielectrics, and metal gate electrodes. M. R. Visokay, A. Shanware, and toward the band edge but mobility gate electrode on high- is the NiSi Full Silicidation process (FUSI).25 The He is a member of the technical L. Colombo, Appl. Phys. Lett., 87, degradation has been observed as result committee for the Semiconductor 012902 (2005). 23 FUSI process has shown some very of Al diffusion into the substrate. The Interface Specialists Conference. He 16. A. Kerber, E. Cartier, L. Pantisano, M. data to date are clear in one respect; that encouraging results by using lanthanide metals for nMOSFET and noble metals may be reached at [email protected]. Rosmeulen, R. Degraeve, T. Kauerauf, is, metal gates reduce gate depletion, G. Groeseneken, H. E. Maes, and but it is challenging to obtain the for pMOSFET at the gate dielectric/FUSI interface. Because of its low thermal U. Schwalke, in Reliability Physics correct work functions that result in low Symposium Proceedings, 2003, 41st

54 The Electrochemical Society Interface • Fall 2007 The Electrochemical Society Interface • Fall 2007 55