Comparative Analysis of the Quantum Finfet and Trigate Finfet Based on Modeling and Simulation

Journal of Computational Electronics (2019) 18:492–499 https://doi.org/10.1007/s10825-018-01294-z

Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation

N. P. Maity1 · Reshmi Maity1 · S. Maity2 · S. Baishya3

Published online: 2 January 2019 © Springer Science+Business Media, LLC, part of Springer Nature 2019

Abstract A comparative analysis of the trigate fn-shaped feld-efect transistor (FinFET) and quantum FinFET (QFinFET) is carried out by using density gradient quantization models in the Synopsys three-dimensional (3-D) technology computer-aided design (TCAD) platform. The gate dielectric stack comprising 0.5 nm SiO 2 (k = 3.9) and 2 nm HfO 2 (k = 22) contributes to an efective oxide thickness of 0.86 nm and is kept constant throughout the study. The results demonstrate that the QFinFET can overcome the limitations of current FinFET devices when scaling down to the atomic level. An analytical model including quantum-mechanical efects for evaluation of the drain current of the FinFET is established and validated using the TCAD software. The degradation in the drive current with downscaling of the fn thickness for the trigate FinFET and the increase in the drive current for the QFinFET are presented. The results are improved by taking into account diferent channel lengths and body thicknesses to estimate the drain current–gate voltage and gate capacitance–gate voltage characteristics for both the trigate FinFET and QFinFET. The drain-induced barrier lowering and subthreshold swing are also analyzed for the trigate FinFET and QFinFET at diferent technology nodes, revealing excellent characteristics. It is clearly established that the QFinFET can overcome the limitations faced by current FinFET devices when scaling the silicon down to the atomic level and may represent the next generation of FinFET devices.

Keywords Trigate FinFET · QFinFET · DIBL · SS · TCAD

1 Introduction the degradation of the subthreshold swing, and the increase in the OFF-current are major issues [1]. The electrical The concept of “more Moore” describes the persistent scal- parameters of a MOSFET change as the dimensions of the ing of feature sizes of metal–oxide–semiconductor feld- device are reduced. Therefore, a major concern is to identify efect transistors (MOSFETs). This remarkable efort has appropriate technologies for further scaling of MOS tran- been the key driver generating today’s sophisticated elec- sistors, leading to the proposal of the tunnel FET (TFET) tronic component technologies. However, further scaling [2]. TFETs are based on band-to-band tunneling and do not of MOSFETs faces challenges regarding device perfor- sufer from SCEs. Despite their advantages, TFETs sufer mance due to several short-channel efects (SCEs). The from drawbacks such as lower ON-current and ambipolar- signifcant increments in the tunneling (leakage) current, ity. To minimize these efects, fn-shaped FETs (FinFETs) were proposed, ofering better control over SCEs, higher ON-current, greater immunity to subthreshold swing (SS) * N. P. Maity degradation, and high carrier mobility [3]. Indeed, double- [email protected] gate FETs (DGFETs) can decrease SCEs, and the FinFET 1 Department of Electronics and Communication Engineering, is a prominent DGFET. Mizoram University (A Central University, Government FinFET technology [4–6] used in state-of-the-art devices of India), Aizawl 796 004, India faces great challenges when scaling down beyond the 7-nm 2 Department of Electronics and Communication Engineering, technology node [7], primarily due to threshold voltage roll- Tezpur University (A Central University, Government of, drain-induced barrier lowering (DIBL), and SS degra- of India), Tezpur 784 028, India dation. In short-channel MOS transistors, the decrease of 3 Department of Electronics and Communication Engineering, the threshold voltage and resulting subthreshold current National Institute of Technology, Silchar 788 010, India

Vol:.(1234567890)1 3 Journal of Computational Electronics (2019) 18:492–499 493 variation at higher drain voltage is known as DIBL. DIBL fn height. Meanwhile, the electrostatic control is much is a very important short-channel efect, being a foremost greater at the top of the fns compared with at the bot- reason for the large slope of the saturation drain current tom. In addition, the defect density is greater for slop- versus the drain voltage in the weak inversion region. Simi- ing than rectangular fns. This increases the unavoidable larly, the SS of a MOS transistor can be evaluated by letting leakage current in the device in terms of the gate-induced → the oxide capacitance go to infnity (C ox ∞ ). In a typical drain leakage (GIDL) current [13] because of the large MOS transistor, the SS is limited to 60 mV/dec at room feld efect in the drain terminal region. A fully depleted temperature. These efects are responsible for the degrada- device, viz. the silicon-on-insulator (SOI) MOSFET, has tion of the transistor performance [8, 9]. Use of a channel been suggested for realization of advanced integrated cir- shorter than 10 nm requires a body thickness of 5 nm or less, cuit (IC) technology [14]. As soon as the body doping which becomes challenging during fabrication of modern concentration causes a reduction in the ON-current, the electronic devices. The tiny 3-D fn standing alone can be body should remain undoped. However, an undoped body broken and/or washed away during cleaning, particularly is leakier [15]. Thus, to reduce this unwanted subthreshold when using sonication for enhanced particle removal, which leakage current while controlling the channel efectively, is signifcant for cleaning of 3-D reliefs [7]. A further con- it has been stated that the body thickness should be on the straint is that, when the silicon body thickness is decreased order of one-third of the channel length of a device [16]. below 5 nm, the band structure starts to depend on the thick- Nowadays, the channel length of a device must be on the ness, which actually favors device performance [10]. Due order of 15 nm or lower, thus requiring a body thickness to the quantum confnement efect, the bandgap gets wider, of 5 nm or lower. Nonetheless, it is very challenging to in turn increasing the available barrier height, signifcantly produce SOI wafers with diameter of 300 nm to 450 nm decreasing the subthreshold leakage current, and improving and silicon body thickness of 5 nm. To date, the percent- the control over the OFF-current. This permits additional age diference has been approximately 5 %, corresponding aggressive scaling of the channel length, with the positive to 0.25 nm [7], indicating that further scaling may not be side efect of reducing the temperature dependence of the appropriate. These are the efects that prevent development device performance parameters [11]. Note that, when the of the performance of state-of-the-art device technology, body thickness is lower than 8 nm, the opposite gate termi- motivating the search for novel structures that will permit nal and top gate terminal over the narrow portion of the fn aggressive scaling towards the end of the silicon technol- are bringing up the rear control over the inversion charge ogy era. concentration. This efect efectively negates any advantage The quantum FinFET concept was proposed by Viktor of using a double- or triple-gate transistor design [10]. This Koldiaev and Rimma Pirogova in a famous patent in 2014 can be understood based on the strong overlap between the [7]. This modern semiconductor device includes a low- two-dimensional (2-D) inversion layer of the two gates. As doped vertical superthin body (VSTB) fn designed on a a consequence, the potential applied on both sides of the dielectric wall, a single gate on one side of the fn, and a 2-D fn creates a carrier concentration in the body that is twice self-aligned source and drain on opposite sides of the fn. It that for a single-gate design, which greatly increases car- is connected to the bulk wafer at the bottom portion, with rier–carrier scattering. As a result, the mobility is degraded isolation on the top portion, the channel and the gate dielec- by the ballistic velocity [11]. In addition, scattering due to tric. The gate electrode is on the opposite portion of the the roughness of the silicon/silicon dioxide (Si/SiO2) inter- dielectric (STI Wall). The body of the QFinFET is prepared face will further degrade the mobility. Thus, manufacturing self-aligned to the STI hard mask, permitting close-ftting double- or triple-gate transistors turns out to be very dif- control over the thickness of the body. The source terminal cult, without advantages in terms of device performance. On and drain terminal are formed by vertically etching the holes the other hand, scaling the fn thickness imposes a limit on in the STI wall and flling with high-doped crystalline or the possibility of realizing high aspect ratios, which cannot polysilicon material appropriately doped with silicides or be achieved practically below thicknesses of 3 nm due to metal contacts or a Schottky barrier source and drain. Either mechanical instability [7]. Despite these issues, it is essential a gate-frst or gate-last process fow can be implemented. to identify an approach that surpasses the present state of the Herein, a comparative analysis between the traditional art for FinFETs at the 7-nm node technology and beyond. trigate FinFET and the QFinFET is presented. The investi- In literature, it is recommended that use of triangular gations include the drain current–drain voltage, drain cur- fns can enable superior performance. In fact, Intel has rent–gate voltage, and gate capacitance-gate voltage charac- also implemented sloping rather than rectangular fns [12]. teristics for several channel lengths and body thicknesses (fn However, scaling of such triangular fns cannot provide thicknesses) with corresponding channel widths. Modeling high aspect ratios, as the scaling of the thickness limits and simulation of the proposed devices are carried out using their height. The threshold voltage VT depends on the 3-D Synopsys TCAD. The proposed QFinFET could be used 1 3 494 Journal of Computational Electronics (2019) 18:492–499 in various multithreshold applications, thus the QFinFET may well represent the next possible solution for scaling of semiconductor devices to the atomic level. The DIBL and subthreshold swing are also analyzed for the trigate FinFET as well as QFinFET at diferent technology nodes.

2 Device structure

Figures 1 and 2 show the device structure and a cross-sectional view of the QFinFET and trigate FinFET, respectively. The modeling and device simulations are carried out using the density gradient quantization models in Sentaurus TCAD software. In the model, the quantum potential value is a function of the carrier densities and their gradients. The gradient quantization model solves the quantum potential calculations self-consistently with the Poisson and carrier continuity equa- tions. The new FinFET device consists of a vertical superthin body, unlike the traditional FinFET device. The gate dielectric stack consists of 0.5 nm of silicon dioxide (SiO 2, k = 3.9) and

Fig. 2 a The structure and b a cross-sectional view of the trigate Fin- FET

2 nm of hafnium oxide (HfO2, k = 22) [17-18], which contributes to an efective oxide thickness (EOT) of 0.86 nm and is kept constant throughout the study. The height of the fn in the trigate FinFET is 25 nm, providing an approximate efective channel width of 55 nm with a body thickness of 5 nm. The height of the VSTB is chosen such that the efective channel width is the same, i.e., 55 nm. The source and drain terminals in the QFinFET structure are formed by etching holes in the dielectric slab on the opposite side of the QFinFET with respect to the gate. A steep retrograde doping profle is used to overwhelm the infuence of the threshold voltage roll-of. The materials used for forming the source/drain terminals are polysilicon (poly-Si) and tungsten metal. The body is doped to 1 × 1016 cm−3, and the source/drain is doped to 2 × 1020 cm−3. The temperature is fxed to 300 K, and the work function of the gate is 4.2 eV.

3 Analytical model

The quantum inversion charge in the channel region of a MOSFET structure adopts a constant value of Fig. 1 a The structure and b a cross-sectional view of the QFinFET Qinv = (kT∕q) × COX , where COX = ox∕tox is the oxide 1 3 Journal of Computational Electronics (2019) 18:492–499 495 capacitance per unit area, T is the temperature, q is the elec- was derived from the expression for the current density tron charge, ox is the oxide permittivity, tox is the oxide Jqm =−q n(x, y) dVf(x)∕dx [23]. After integrating Jqm in k y z I thickness, and is Boltzmann’s constant. Considering the the and direction, D(qm) can be calculated. Considering carrier confnement in the silicon layer, the inversion charge the quantum inversion charge, qinv(x) from Eq. (1) and insert- can be written quantum-mechanically as [19], ing it into Eq. (3), one gets

Eg q (x) = ( ) mi,j g × ln 1 + exp − El + − (x) + V (x) , inv 2P i,j i,j 2 s f (1) i,j i where s(x) is the surface potential and Eg is the energy gap. i ∗ W Here, = (qkT)∕() . In this case, m = m , I = Fin mi,j g 2P j D(qm) L 2D i,j mj = m∗m∗ m∗ = 0.98 × m m∗ = 0.19 × m g = 2 Eff 2P i j , i 0 , j 0 , i , VD Eg × ln 1 + exp − El + − (x) + V (x) dV (x). gj = 4 , and = q∕kT . mi and mj are the efective masses of i,j s f f 2 (4) the electron in the longitudinal and transverse direction, 0 x ≪ 1 log (1 + x) ≈ (x) respectively, and m0 is the rest mass of the electron. The We now consider , then , and l energy levels Ei,j are calculated considering the band dia- using this assumption in Eq. (4) yields gram to be nearly an infnite rectangular well for the FinFET W I = Fin mi,j g El = 22i2 2qm∗ T2 D(qm) L 2D i,j structure, which gives [20] i,j i,j Fin , Eff VD Vf(x) where is the quasi-Fermi potential, given by [21] Eg − El + − (x) + V (x) × dV (x). i,j s f f 2 (5) V n 0 2mkT D m V (x) = ln exp − − 1 Then, after integrating, f � � nq ⎡⎡ ⎧ 1 ⎫ ⎤ � � 2 ⎢⎢ ⎪ ⎪ ⎥ W Eg V � � (2) I = Fin mi,j g − El + − (x) V + D . C ⎢⎢ ⎨−1 ⎬ ⎥ D(qm) 2D i,j i,j s D LEff 2 2 VG−VFB⎢⎢ ⎪ ⎪ ⎥ x (VD∕ 3C) × � ⎣⎣� + 1⎩ × aT ⎭ ⎦ , L Fin (6) � eff � ⎤ � � The fnal expression for the drain current considering ⎥ ⎥ quantum-mechanical efects obtained for a FinFET device −1 −1 where (n∕m) = 2 + P VG − ⎦VFB , a = 0.2 nm , P = 7.5 V , is thus and C = 1V . Equation (2) describes the variation of the 2 W Eg V quasi-Fermi potential along the channel. To evaluate the I =− Fin mi,j g El + − (x) V + D . D(qm) L 2D i,j i,j 2 s D 2 drain current, including quantum-mechanical efects, for Eff FinFET devices, the drift component as well as the difusion (7) I component should be used. Thus, the drain current, D(qm) , of Quantum-mechanical efects occur in FinFET devices a multigate device considering quantum-mechanical efects at lower technology nodes and cannot be ignored. For this can be obtained by integrating the current density expres- reason, Eq. (7) is developed considering the quantum- x = 0 sion in the y and z direction and setting the value of to mechanical efects for multigate devices such as FinFET. x = L eff as follows [22]: However, in a FinFET, fn engineering is critical to mini- VD mize the leakage components and OFF-current and to W Fin maximize the ON-current. Fin engineering requires bal- ID(qm) = qinv(x) × dVf(x), (3) LEff ancing of the fn height and thickness, oxide thickness, and 0 channel length [22]. where is the mobility, Leff is the effective channel length, and WFin is the width of the fn. Equation (3)

1 3 496 Journal of Computational Electronics (2019) 18:492–499

4 Results and discussion

First, an adjustment is determined to describe the diference between the TCAD simulation results and the experimental results at VDS values of 0.9 V and 0.5 V [24–25], to authenticate the simulated physics model. The device is fabricated using a conventional FinFET [24], and the adjustment is applied because the verifed TCAD physics model [26] will be used in all the FinFET structure simulations. Here, the Fermi–Dirac distribution is used in all the TCAD simulations, as done in Refs. [27, 28], because it is efective for indistinguishable particles such as elec- trons [29]. We also use the bandgap narrowing model and Fig. 4 The drain current versus the drain voltage for the trigate Fin- Shockley–Read–Hall (SRH) recombination in the TCAD FET and QFinFET simulations. A high-feld saturation model is applied, and certain mobility parameters are adjusted as in Ref. [30] to enable the drain current versus gate voltage characteris- voltages, quantum-mechanical efects play a very impor- tics to be plotted. Excellent agreement between the TCAD tant role, owing to the structural and electrical confnement. simulation results and experimental results is found, as This fgure shows that the ON-state current is signifcantly shown in Fig. 3. The proposed TCAD simulation model improved in the Q-FinFET as compared with the trigate Fin- parameters are therefore standardized and used throughout FET. The drain current–gate voltage characteristics for both this work. devices are shown in Fig. 5. The channel length is decreased In this study, the trigate FinFET and QFinFET are com- from 20 nm to 11 nm in steps of 3 nm. The characteristics in pared with respect to their drive strength, gate capacitance, the graphs are the same. subthreshold swing, and immunity to SCEs, viz. drain- In this investigation, the body thickness Tfin and the W induced barrier lowering. The device simulations are carried efective channel width eff are kept constant. The top out such that the efective channel width and the thickness gate oxide thickness is greater than the sidewall oxide of the fn are kept the same for the trigate FinFET and QFin- thickness. The length of the channel is kept fxed at 20 nm, FET. Figure 4 shows a plot of the drain current with respect while the thickness of the body is decreased from 11 nm to the drain voltage for a gate-to-source voltage of 0.7 V and to 5 nm in steps of 3 nm; the results are depicted in Fig. 5. a channel length of 20 nm. The characteristic is identical in Both devices again show the same characteristics. The cor- all the graphs, clearly showing that, in the saturated region, responding efective channel width are Weff = 77 nm for the TCAD software and analytical modeling results for the Tfin = 11 nm , Weff = 56 nm for Tfin = 8 nm , and Weff = 35 nm QFinFET are comparatively closer compared with the linear for Tfin = 5 nm . Weff is calculated as Weff = Tfin + 2 × Hfin , region, as quantum-mechanical efects are less dominant at where Hfin is the height of the fn. lower drain supply voltages. However, at higher gate supply

Fig. 5 I V Fig. 3 The calibration of the TCAD simulation against the published The D– G characteristics for diferent channel lengths at con- experimental results at diferent drain voltage values stant body thickness

1 3 Journal of Computational Electronics (2019) 18:492–499 497

Fig. 7 The gate capacitance versus the gate voltage for diferent gate lengths (indicated by arrow) for a body thickness of 5 nm Fig. 6 The ID–VG characteristics for diferent body thicknesses at constant channel length

Note that the trigate FinFET shows more leakage current compared with the QFinFET. It is seen that the QFinFET and the conventional trigate FinFET perform in a similar fashion for the diferent channel lengths. The QFinFET shows better leakage current reduction with signifcantly less SS. The degradation in the ON-current ION in the trigate FinFET from Fig. 6 can be attributed to the source/ drain region to gate resistance, which increases as the body thickness is increased, although the ION IOFF ratio remains I identical. High ON can be achieved by reducing the source/ drain resistance. It is observed that, for the QFinFET, the source and drain Fig. 8 The gate capacitance versus the gate voltage for diferent fn terminals are not part of the body; in fact, they are formed thicknesses (indicated by arrow head) for a channel length of 20 nm by etching holes in the dielectric slab and flling with the required source/drain material. In this investigation, tungsten material was used to form the source and drain terminals, followed by heavily doped polysilicon. This process of forming the source and drain terminals of the transistor is benefcial in terms of reducing the efect of the source/drain feld lines on the channel region, thereby improving the con- stancy of the threshold voltage with respect to the applied drain terminal voltage. The great advantage of the QFin- FET is that it can be straightforwardly modifed to achieve various threshold voltages. Multithresholding can thus be implemented in a FinFET by changing the work function of the metal and gate underlap. In classical modeling techniques, the gate capacitance is Fig. 9 The gate capacitance model for the QFinFET and the tri- modeled as the oxide capacitance COX and channel capaci- a b C gate FinFET tance CH connected in series. Since the physical oxide thickness is diferent from the real oxide thickness owing to the quantization at the silicon/silicon dioxide interface, this capacitance, thus reducing the total gate capacitance. Fig- approach gives erroneous results for nanoelectronic devices. ure 7 shows the variation of the gate capacitance versus One therefore introduces an additional component of the the gate voltage with the channel length as a parameter. In total capacitance, termed the quantum capacitance CQ , in Fig. 8, the body thickness is varied at fxed channel length. series with the oxide capacitance. Greater quantization at the The QFinFET presents greater total gate capacitance than silicon/silicon dioxide interface results in a lower quantum the trigate FinFET in both cases, thus exhibiting a higher

1 3 498 Journal of Computational Electronics (2019) 18:492–499

the switching of the drain current as well as the control over the gate.

5 Conclusions

Analytical modeling and TCAD simulations are applied to study a QFinFET and compare its performance with that of a trigate FinFET. The results show the degradation in the drive current with downscaling of the fn thickness for the trigate FinFET and the increase in the drive current for the QFinFET. It can be concluded that the QFinFET displays better leakage current reduction with signifcantly less SS Fig. 10 The DIBL for the trigate FinFET and QFinFET at diferent and DIBL, while the QFinFET shows higher gate capaci- technology nodes tance than the trigate FinFET. Also, the mechanical instability of the thin fn will become a severe constraint limiting the scaling of FinFETs. It can be concluded that QFinFETs can overcome these limitations on scaling of the silicon to the atomic level and may represent next-generation FinFET devices.

Acknowledgements The authors would like to thank Mr. Praveen Gunturi, National Institute of Technology, Silchar for his support of this technical work. The authors are highly indebted to TCAD Labora- tory, National Institute of Technology, Silchar, India for supporting this technical work.

Fig. 11 The SS of the trigate FinFET and QFinFET for diferent tech- References nology nodes 1. Abadi, R., Saremi, M.: A resonant tunneling nanowire feld efect transistor with physical contractions: a negative diferential resist- delay and lower operating speed. This phenomenon can be ance device for low power very large scale integration applica- understood based on the capacitance model shown in Fig. 9. tions. J. Electron. Mater. 47(2), 1091–1098 (2018) These results show the gate capacitance per gate, however 2. Imenabadi, R., Saremi, M., Vandenberghe, W.: A novel PNPN-like the semiconductor body capacitance CSC is shared by the Z-shaped tunnel feld-efect transistor with improved ambipolar behavior and RF performance. IEEE Trans. Electron Devices two gates in the trigate FinFET while the body capacitance 64(11), 4752–4758 (2017) is shared by the single gate in the QFinFET. Therefore, the 3. Saremi, M., Afzali-Kusha, A., Mohammadi, S.: Ground plane total gate capacitance of the QFinFET is greater compared fn-shaped feld efect transistor (GP-FinFET): a FinFET for low with that of the trigate FinFET. The subthreshold swing for leakage power circuits. Microelectron. Eng. 95, 74–82 (2012) 4. Sharma, S.M., Dasgupta, S., Kartikeyan, M.V.: Successive con- diferent technology nodes is shown in Fig. 10. The sub- formal mapping technique to extract inner fringe capacitance of threshold swing is one of the foremost parameters of any underlap DG-FinFET and its variations with geometrical param- FinFET device, expressing the speed of the device, i.e., eters. IEEE Trans. Electron Devices 64(2), 384–391 (2017) its switching rate from ON to OFF and OFF to ON. This 5. Yeh, W., Zhang, W., Yang, Y., Dai, A., Wu, K., Chou, T., Lin, C., Gan, K., Shih, C., Chen, P.: The observation of width quantization graph shows that, as the technology node decreases, the SS impact on device performance and reliability for high-k/metal tri- increases for the trigate FinFET as well as the QFinFET. gate FinFET. IEEE Trans. Device Mater. Reliab. 16(4), 610–616 However, the QFinFET is predicted to ofer a better SS. In (2016) this analysis, we use the density gradient quantization model 6. Chen, S., Hellings, G., Thijs, S., Linten, D., Groeseneken, G.: Process options impact on ESD diode performance in bulk Fin- and mobility model. FET technology. IEEE Trans. Electron Devices 63(9), 3424–3431 Figure 11 shows the DIBL for diferent technology nodes. (2016) As expected, as the technology node decreases, the DIBL 7. Koldiaev, V., Pirogova, R.: Vertical super thin body semiconductor increases. In this case also, the QFinFET ofers improved on dielectric wall devices and methods of their fabrication. U.S. Patent: 8796085 B2 (2014) performance compared with the trigate FinFET, clearly showing that the QFinFET device is better in terms of both

1 3 Journal of Computational Electronics (2019) 18:492–499 499

8. Dennard, R., Gaensslen, F., Yu, H., Rideout, V., Bassous, E., LeB- application to high-k material HfO 2 based MOS devices. Superlat- lanc, A.: Design of ion-implanted MOSFET’s with very small tices Microstruct. 111, 628–641 (2017) physical dimensions. IEEE J. Solid-State Circuits 9, 256–268 20. S. Harrison, D. Munteanu, J.L. Autran, A. Cros, R. Cerutti, T. (1974) Skotnicki, Electrical characterization and modeling of high perfor- 9. T. Tanaka, T. Usuki, T. Futatsugi, Y. Momiyama, T. Sugii, Vth mance SON DG MOSFET’s, in IEEE Proceedings of ESSDERC, fuctuation induced by statistical variation of pocket dopant pro- pp. 373–376 (2004) fle, in IEEE International Electron Devices Meeting, IEEE Press, 21. Van Overstraeten, R.J., Declerck, G.J., Muls, P.A.: Theory of the pp. 271–274 (2000) MOS transistor in weak inversion-new method to determine the 10. Majkusiak, B., Janik, T., Walczak, J.: Semiconductor thickness number of surface states. IEEE Trans. Electron Devices 22(5), efects in the double-gate SOI MOSFET. IEEE Trans. Electron 282–288 (1975) Devices 45(5), 1127–1134 (1998) 22. B. Raj, A.K. Saxena, S. Dasgupta, Quantum inversion charge and 11. Riddit, C., Alexander, C., Brown, A.R., Roy, S., Asenov, A.: Sim- drain current analysis for double-gate FinFET device: analytical ulation of “ab initio” quantum confnement scattering in UTB modeling and TCAD simulation approach, in IEEE Fourth UKSim MOSFETs using three-dimensional ensemble Monte Carlo. IEEE European Symposium on Computer Modeling and Simulation, pp. Trans. Electron Devices 58(3), 600–608 (2011) 526–530 (2010) 12. D. James, Intel Ivy Bridge unveiled—the frst commercial tri- 23. Munteanu, D., Utran, J., Loussier, X., Harrison, S., Cerutti, R., gate, high-k, metal-gate CPU, in IEEE Proceedings of Custom Skotnicki, T.: Quantum short channel compact modeling of drain Integrated Circuits Conference (2012) current in double gate MOSFET. Solid State Electron. 50, 680– 13. Gaynor, B.D., Hossoun, S.: Fin shape impact on FinFET leakage 686 (2006) with application to multithreshold and ultralow-leakage FinFET 24. Rios, R., Cappellani, A., Armstrong, M., Bundrevich, A., Gomez, design. IEEE Trans. Electron Devices 61(8), 2738–2744 (2014) H., Pai, R., Rahhal-orabi, N., Kuhn, K.: Comparison of junction- 14. Mazurier, J., Weber, O., Andrieu, F., Tofoli, A., Allain, F., Per- less and conventional trigate transistors with L g down to 26 nm. reau, P., Fenouillet-Beranger, C., Thomas, O., Belleville, M., IEEE Electron Device Lett. 32(9), 1170–1172 (2011) Faynot, O.: On the variability in planar FDSOI technology: from 25. Saha, R., Baishya, S., Bhowmick, B.: 3D analytical modeling of MOSFETs to SRAM cells. IEEE Trans. Electron Devices 58(8), surface potential, threshold voltage and subthreshold swing in 2326–2336 (2011) dual-material-gate (DMG) SOI FinFET. J. Comput. Electron. 17, 15. Majumdar, A., Ren, Z., Koester, S.J., Haensch, W.: Undoped-body 153–162 (2018) extremely thin SOI MOSFETs with back gates. IEEE Trans. Elec- 26. Sentaurus Device User Guide. Synopsys, Inc. (2015) tron Devices 56(10), 2270–2276 (2009) 27. Pal, A., Sarkar, A.: Analytical study of dual material surrounding 16. M.G. Bardon, P. Schuddinck, P. Raghavan, D. Jang, D. Yakimets, gate MOSFET to suppress short-channel efects (SCEs). Eng. Sci. A. Mercha, D. Verkest, A. Thean, Dimensioning for power and Technol. Int. J. 17, 205–212 (2014) performance under 10 nm: the limits of FinFETs scaling, in IEEE 28. Tripathi, S., Narendar, V.: A three-dimensional (3D) analytical Proceedings of International Conference on IC Design and Tech- model for subthreshold characteristics of uniformly doped Fin- nology Conference (2015) FET. Superlattices Microstruct. 83, 476–487 (2015) 17. Munteanu, D., Autran, J.L., Loussier, X., Harrison, S., Cerutti, 29. McKelvey, J.P.: Solid State and Semiconductor Physics. Harper R., Skotnicki, T.: Quantum short-channel compact modelling of and Row, New York (1996) drain-current in double-gate MOSFET. Solid-State Electron. 50, 30. Nawaz, S.M., Dutta, S., Chattopadhyay, A., Mallik, A.: Compari- 680–686 (2006) son of random dopant and gate-metal workfunction variability 18. Maity, N.P., Maity, R., Thapa, R.K., Baishya, S.: A tunneling cur- between junctionless and conventional FinFETs. IEEE Electron rent density model for ultra-thin HfO2 high-k dielectric material Device Lett. 35(6), 663–665 (2014) based MOS devices. Superlattices Microstruct. 95, 24–32 (2016) 19. Maity, N.P., Maity, R., Baishya, S.: Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model:

1 3