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Comparative Analysis of the Quantum Finfet and Trigate Finfet Based on Modeling and Simulation

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Comparative Analysis of the Quantum Finfet and Trigate Finfet Based on Modeling and Simulation Journal of Computational Electronics (2019) 18:492–499 https://doi.org/10.1007/s10825-018-01294-z Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation N. P. Maity1 · Reshmi Maity1 · S. Maity2 · S. Baishya3 Published online: 2 January 2019 © Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract A comparative analysis of the trigate fn-shaped feld-efect transistor (FinFET) and quantum FinFET (QFinFET) is carried out by using density gradient quantization models in the Synopsys three-dimensional (3-D) technology computer-aided design (TCAD) platform. The gate dielectric stack comprising 0.5 nm SiO­ 2 (k = 3.9) and 2 nm HfO­ 2 (k = 22) contributes to an efective oxide thickness of 0.86 nm and is kept constant throughout the study. The results demonstrate that the QFinFET can overcome the limitations of current FinFET devices when scaling down to the atomic level. An analytical model including quantum-mechanical efects for evaluation of the drain current of the FinFET is established and validated using the TCAD software. The degradation in the drive current with downscaling of the fn thickness for the trigate FinFET and the increase in the drive current for the QFinFET are presented. The results are improved by taking into account diferent channel lengths and body thicknesses to estimate the drain current–gate voltage and gate capacitance–gate voltage characteristics for both the trigate FinFET and QFinFET. The drain-induced barrier lowering and subthreshold swing are also analyzed for the trigate FinFET and QFinFET at diferent technology nodes, revealing excellent characteristics. It is clearly established that the QFinFET can overcome the limitations faced by current FinFET devices when scaling the silicon down to the atomic level and may represent the next generation of FinFET devices. Keywords Trigate FinFET · QFinFET · DIBL · SS · TCAD 1 Introduction the degradation of the subthreshold swing, and the increase in the OFF-current are major issues [1]. The electrical The concept of “more Moore” describes the persistent scal- parameters of a MOSFET change as the dimensions of the ing of feature sizes of metal–oxide–semiconductor feld- device are reduced. Therefore, a major concern is to identify efect transistors (MOSFETs). This remarkable efort has appropriate technologies for further scaling of MOS tran- been the key driver generating today’s sophisticated elec- sistors, leading to the proposal of the tunnel FET (TFET) tronic component technologies. However, further scaling [2]. TFETs are based on band-to-band tunneling and do not of MOSFETs faces challenges regarding device perfor- sufer from SCEs. Despite their advantages, TFETs sufer mance due to several short-channel efects (SCEs). The from drawbacks such as lower ON-current and ambipolar- signifcant increments in the tunneling (leakage) current, ity. To minimize these efects, fn-shaped FETs (FinFETs) were proposed, ofering better control over SCEs, higher ON-current, greater immunity to subthreshold swing (SS) * N. P. Maity degradation, and high carrier mobility [3]. Indeed, double- [email protected] gate FETs (DGFETs) can decrease SCEs, and the FinFET 1 Department of Electronics and Communication Engineering, is a prominent DGFET. Mizoram University (A Central University, Government FinFET technology [4–6] used in state-of-the-art devices of India), Aizawl 796 004, India faces great challenges when scaling down beyond the 7-nm 2 Department of Electronics and Communication Engineering, technology node [7], primarily due to threshold voltage roll- Tezpur University (A Central University, Government of, drain-induced barrier lowering (DIBL), and SS degra- of India), Tezpur 784 028, India dation. In short-channel MOS transistors, the decrease of 3 Department of Electronics and Communication Engineering, the threshold voltage and resulting subthreshold current National Institute of Technology, Silchar 788 010, India Vol:.(1234567890)1 3 Journal of Computational Electronics (2019) 18:492–499 493 variation at higher drain voltage is known as DIBL. DIBL fn height. Meanwhile, the electrostatic control is much is a very important short-channel efect, being a foremost greater at the top of the fns compared with at the bot- reason for the large slope of the saturation drain current tom. In addition, the defect density is greater for slop- versus the drain voltage in the weak inversion region. Simi- ing than rectangular fns. This increases the unavoidable larly, the SS of a MOS transistor can be evaluated by letting leakage current in the device in terms of the gate-induced → the oxide capacitance go to infnity (C ox ∞ ). In a typical drain leakage (GIDL) current [13] because of the large MOS transistor, the SS is limited to 60 mV/dec at room feld efect in the drain terminal region. A fully depleted temperature. These efects are responsible for the degrada- device, viz. the silicon-on-insulator (SOI) MOSFET, has tion of the transistor performance [8, 9]. Use of a channel been suggested for realization of advanced integrated cir- shorter than 10 nm requires a body thickness of 5 nm or less, cuit (IC) technology [14]. As soon as the body doping which becomes challenging during fabrication of modern concentration causes a reduction in the ON-current, the electronic devices. The tiny 3-D fn standing alone can be body should remain undoped. However, an undoped body broken and/or washed away during cleaning, particularly is leakier [15]. Thus, to reduce this unwanted subthreshold when using sonication for enhanced particle removal, which leakage current while controlling the channel efectively, is signifcant for cleaning of 3-D reliefs [7]. A further con- it has been stated that the body thickness should be on the straint is that, when the silicon body thickness is decreased order of one-third of the channel length of a device [16]. below 5 nm, the band structure starts to depend on the thick- Nowadays, the channel length of a device must be on the ness, which actually favors device performance [10]. Due order of 15 nm or lower, thus requiring a body thickness to the quantum confnement efect, the bandgap gets wider, of 5 nm or lower. Nonetheless, it is very challenging to in turn increasing the available barrier height, signifcantly produce SOI wafers with diameter of 300 nm to 450 nm decreasing the subthreshold leakage current, and improving and silicon body thickness of 5 nm. To date, the percent- the control over the OFF-current. This permits additional age diference has been approximately 5 %, corresponding aggressive scaling of the channel length, with the positive to 0.25 nm [7], indicating that further scaling may not be side efect of reducing the temperature dependence of the appropriate. These are the efects that prevent development device performance parameters [11]. Note that, when the of the performance of state-of-the-art device technology, body thickness is lower than 8 nm, the opposite gate termi- motivating the search for novel structures that will permit nal and top gate terminal over the narrow portion of the fn aggressive scaling towards the end of the silicon technol- are bringing up the rear control over the inversion charge ogy era. concentration. This efect efectively negates any advantage The quantum FinFET concept was proposed by Viktor of using a double- or triple-gate transistor design [10]. This Koldiaev and Rimma Pirogova in a famous patent in 2014 can be understood based on the strong overlap between the [7]. This modern semiconductor device includes a low- two-dimensional (2-D) inversion layer of the two gates. As doped vertical superthin body (VSTB) fn designed on a a consequence, the potential applied on both sides of the dielectric wall, a single gate on one side of the fn, and a 2-D fn creates a carrier concentration in the body that is twice self-aligned source and drain on opposite sides of the fn. It that for a single-gate design, which greatly increases car- is connected to the bulk wafer at the bottom portion, with rier–carrier scattering. As a result, the mobility is degraded isolation on the top portion, the channel and the gate dielec- by the ballistic velocity [11]. In addition, scattering due to tric. The gate electrode is on the opposite portion of the the roughness of the silicon/silicon dioxide (Si/SiO2) inter- dielectric (STI Wall). The body of the QFinFET is prepared face will further degrade the mobility. Thus, manufacturing self-aligned to the STI hard mask, permitting close-ftting double- or triple-gate transistors turns out to be very dif- control over the thickness of the body. The source terminal cult, without advantages in terms of device performance. On and drain terminal are formed by vertically etching the holes the other hand, scaling the fn thickness imposes a limit on in the STI wall and flling with high-doped crystalline or the possibility of realizing high aspect ratios, which cannot polysilicon material appropriately doped with silicides or be achieved practically below thicknesses of 3 nm due to metal contacts or a Schottky barrier source and drain. Either mechanical instability [7]. Despite these issues, it is essential a gate-frst or gate-last process fow can be implemented. to identify an approach that surpasses the present state of the Herein, a comparative analysis between the traditional art for FinFETs at the 7-nm node technology and beyond. trigate FinFET and the QFinFET is presented. The investi- In literature, it is recommended that use of triangular gations include the drain current–drain voltage, drain cur- fns can enable superior performance. In fact, Intel has rent–gate voltage, and gate capacitance-gate voltage charac- also implemented sloping rather than rectangular fns [12]. teristics for several channel lengths and body thicknesses (fn However, scaling of such triangular fns cannot provide thicknesses) with corresponding channel widths.
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