DOCSLIB.ORG

Challenges to EDA System from the View Point of Processor Design and Technology Drivers

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Challenges to EDA System from the View Point of Processor Design and Technology Drivers Challenges to EDA System from the View Point of Processor Design and Technology Drivers Mitsuo Saito Chief Fellow / VP Engineering Toshiba Corporation Semiconductor Company Copyright © 2009 Toshiba Corporation, All rights reserved. Contents Semiconductor Technology and Microprocessor Trend Our Processor Design Experiences ¾ Early Struggles for Processor Design ¾ Meet with Playstation • Development of Graphics and Emotion Engine for Playstation 2 ¾ Towards Cell Broadband Engine (Cell) • Development of Cell Processor • Targets of Cell Processor ¾ Towards SpursEngine • What is SpursEngine Makimoto’s Wave and What we have done? ¾ Historical Analysis of Development Today’s Situation and Challenge to EDA system ¾ What is necessary now? ¾ What will happen next? Summary Copyright © 2009 Toshiba Corporation, All rights reserved. 2 StillStill SemiconductorSemiconductor RoadmapRoadmap is is WorkingWorking :: MooreMoore’’ss LawLaw One Billion Transistors per Chip in 2010 (250Mgates) 1.E+10 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 # of Transistors / Chip 1.E+04 1.E+03 1980 1985 1990 1995 2000 2005 2010 From SEMATECH Data Copyright © 2009 Toshiba Corporation, All rights reserved. 3 First Micro Processor was born in 1971 Intel 4004 DIP16P, Address bus 12 bit, Data bus 4 bit Clock 741KHz P-MOS 10um Tr. 2300 11/15/1971 From : Wikipedia Copyright © 2009 Toshiba Corporation, All rights reserved. 4 ProcessorProcessor ClockClock RateRate perper YearYear 10000 6GHz 3.2GHz 5GHz 3.8GHz P4 PLAYSTATION3 2.93GHz Standard Processor Era 3.6GHz P4 2006/11/11 3.4GHz P4 Core2 Ext 4GHz Out of Order Execution 3.2GHz P4 3.0GHz P4 3GHz 2.0GHz 3.2GHz Pentium 4 XBox360 2GHz 1.4GHz 2005/12/10 Pentium 4 1GHz Athlon/PIII Multi core Era 1000 700MHz 800MHz Freq. ≠ Perf. RISC Era 600MHz 21264 Pentium III 733MHz 21164 XBox 500MHz Simpler the Better 600MHz 2001/11/15 21164 Pentium III 485MHz 300MHz 450MHz GameCube 275MHz 21164 Pentium II 2001/9/14 21064 200MHz 300MHz 300MHz Clock Rate (MHz) 187MHz 21064 Pentium II PlayStation2 21064 2000/3/4 200MHz 200MHz Pentium Pro Dreamecast 1998/11/24 100MHz 150MHz R4000 Pentium Pro 100 100MHz 100MHz Pentium Nintendo64 1996/6/18 Hiend Processor 66MHz Pentium x86 Processor 66MHz 33MHz 486DX2 PlayStation GAME console 1994/12/3 1999 SIA local clk(Hi-Perf.) 1999 SIA chip-across clk(Hi-Perf.) 10 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 991 992 993 994 995 996 997 998 999 000 001 002 003 004 005 006 007 Year (Chip or System Shipment) Copyright © 2009 Toshiba Corporation, All rights reserved. 5 Waves to Standardization and Customization Mass production (Standardization)：Factory efficiency S/W solution Enough performance with 10 million/month Performance became standard HW, SW Solution better than RISC + ASIC Severe competition Surplus supply Memory in Asia Price down Price slump X86 + MPU in US Standard Software PC Chipset Transistor, 1KDRAM(Intel) Memory, SPARC(SUN) Centric Emotion Tr Diode 4bit MPU(Intel) MPU R3000(MIPS) Design ('47) Engine Cell/B.E. Cell/B.E. 1957 1967 1977 1987 1997 2007 2017 TV, IC Invention CAD Revolution Power Consumption? Calculator, SW+HW Engine Killby patent Watch MOS GA ASIC System on a RISC Short life cycle Design crisis Chip New product development race Too much integration 100 design/month Co-design of dedicated H/W & S/W Various & small production (Customization)：Customer satisfaction Source : Makimoto’s Wave Copyright © 2009 Toshiba Corporation, All rights reserved. 6 AI Workstation (1986) Maybe the last paper and pencil based Design! Processor was a board based About 100 sets were sold, and reasonable revenue Copyright © 2009 Toshiba Corporation, All rights reserved. 7 AI Processor Chip (1988) •Silicon Compiler “Genesil” was Used Performance 12 MIPS @Dhrystone Registers 32bit × 32 Buses 32bit × 2 Bus Cycle 1 Clock min Clock Freq. 16MHz Max Process 1.2um 2 Layer Metal CMOS Tr.Cnt 113K Package 299pin PGA Copyright © 2009 Toshiba Corporation, All rights reserved. 8 First TRON Processor TX1 (1988) •Proprietary HDL (H2DL) was used Performance 5 MIPS Registers 32bit × 16 Buses 32bit × 2 Bus Cycle 2 Clock min Clock Freq. 25MHz Max Process 1.0um 2 Layer Metal CMOS Package 155-pin PGA Copyright © 2009 Toshiba Corporation, All rights reserved. 9 Incomplete GL Processor (1990) •Proprietary HDL (H2DL) was used Freq. 65MHz Inst. 4 Way SuperScalar Dhry. 100MIPS Linpack 66MFlops(Single) 35MFlops(Double) Power 3.3V/5~6W Process 0.5μmCMOS Package 448pin PGA Tr.cnt 2.5M Copyright © 2009 Toshiba Corporation, All rights reserved. 10 RISC Processor R8000 (1993) •Verilog was used Jointly developed with Silicon Graphics Inc. Copyright © 2009 Toshiba Corporation, All rights reserved. 11 R8000 Based Computer Board Designed by Silicon Graphics Inc. Copyright © 2009 Toshiba Corporation, All rights reserved. 12 Embedded RISC Processor TX39(1995) •Verilog was used •First Embedded RISC •32bit MIPS Architecture •40MHz/43MIPS •500mw •4KB I cache / 1KB D cache •4K page MMU (32 entry) Copyright © 2009 Toshiba Corporation, All rights reserved. 13 “GSP” in 1988 ・Gouraud Shading 10M Pixel/sec 30K Polygons/sec ・Flat Shading 160M Pixel/sec ・Lines 1M Lines/sec ・Clock 20MHz ・Technology 1.2μmCMOS ・Transistor Count 130K Transistors ・Chip size 11.5×11.3mm ・Package 144pin Flat Package Copyright © 2009 Toshiba Corporation, All rights reserved. 14 Molecular model image by GSP 5160 Polygons 6.4 frames/Sec 8 bit/pixel 16bit Z Buffer Copyright © 2009 Toshiba Corporation, All rights reserved. 15 First Generation Playstation Source : Wikipedia Copyright © 2009 Toshiba Corporation, All rights reserved. 16 Playstation Shipment History From: http://www.scei.co.jp/corporate/data/ 1000 16000 900 14000 800 12000 700 10000 600 500 8000 400 x10KTotal x10K/Quater 6000 300 4000 200 2000 100 0 0 96/3 97/3 98/3 99/3 00/3 01/3 02/3 03/3 04/3 05/3 06/3 07/3 08/3 PlayStation PlayStation 2 Playstation 3 Playstation Total 30 100 Playstation2 Total Playstation3 Total Copyright © 2009 Toshiba Corporation, All rights reserved. 17 Playstation was very successful, though Original business model was not making money from Hardware but Software license. In reality, could make money even from hardware, mainly because of semiconductor cost down. 3D graphics could get very good reputation. But It’s performance was not good enough yet. Emotion of the characters couldn’t be presented! By considering game console life cycle, hardware performance should be competitive at least for a few years An epoch-making graphic chip was the key for the next generation Embedded DRAM technology based graphics was employed Main processor had to have enough performance correspond to very high performance graphics. Special processor had to be developed Copyright © 2009 Toshiba Corporation, All rights reserved. 18 “Graphics Synthesizer ”(GS) 16.6mm×16.8mm 32Mbit Embedded DRAM 0.25μm 47.7 M transistors Designed by SONY, SCE and Toshiba Fabricated by SONY Copyright © 2009 Toshiba Corporation, All rights reserved. 19 Rendering performance Trend 100,000,000 Game Console Polygon/sec Personal Computer PS2 Graphics Work Station 10,000,000 Dream Cast 1,000,000 N64(?) PlayStation 100,000 1993 1994 1995 1996 1997 1998 1999 Copyright © 2009 Toshiba Corporation, All rights reserved. 20 How Emotion Engine was born? Toshiba could develop and provide the graphics chip for the first generation Playstaion. However, processor chip was provided by US company. Some engineers in Toshiba semiconductor division, began to consider to propose not only graphics but main processor for next generation Playstation, and it was called “Emotion Engine” afterwards. Started to approach to SCEI a few month after first generation Playstation was launched (12/3/1994). SCEI was interested in proposed Geometry Engine architecture, and started a joint technical investigation After main concept of Emotion Engine was accomplished, Toshiba team has started to develop the processor portion at the Silicon Valley office in 1996, before an agreement was done. Copyright © 2009 Toshiba Corporation, All rights reserved. 21 Emotion Engine Die Photo 15.02mm x 15.04mm Frequency : 300MHz Transistors : 13.5M Power : 18Watts Design Rule : 0.25um Gate Length : 0.18um Designed by SCE and Toshiba Fabricated by Toshiba Copyright © 2009 Toshiba Corporation, All rights reserved. 22 Emotion Engine Block Diagram COP2 E 128bit F COP1 VU1 Processor U FPU Core VU0 128 Inst. Data GIF Inst. Data Mem. Mem. to 16KB 16KB SP- Mem. Mem. Rendering I$ D$ 4KB 4KB Engine RAM (GS LSI) VIF0 VIF1 CPU VPU0 VPU1 System Bus 10ch 128-bit Memory I/O IPU DMAC Interface Interface External Memory Peripherals Copyright © 2009 Toshiba Corporation, All rights reserved. 23 Emotion Engine Peak Performance 7 Integer Performance(GIPS) 6 Bus Band width(Gbyte/Sec) Floating Point performance(GFLOPS) 5 4 3 2 1 0 Pentium2(400MHz) Pentium3(600MHz) EE(300MHz) Copyright © 2009 Toshiba Corporation, All rights reserved. 24 Emotion Engine Development History Spring 1997：Joint Development Agreement was done (Schedule was defined) Spring 1998 ：Design Completion has been delayed because of many Bugs of CPU and not enough speed ¾ Had to report Six month delay from the original schedule Spring 1998 ：Reorganize and enhance development team (82 engineers from Toshiba Japan), and Reset the Target date and specification ¾ #1 Design Completion 7/1998 ¾ Chip size=17x14.1mm2 Aug. 1998 ： EE#1 Design completion (8 month Delay) ¾ Relaxation of the target frequency（300MHz=>200MHz) ¾ Agreed to Relax voltage and temperature constraint Oct. 1998 ： Shipped the first sample and SCE started the system evaluation Dec. 31 1998 ： Shipped the software developable revised samples Feb. 1999 ： Presented at the conference（ISSCC）, fair reputation Mar. 1999 ： Next generation Playstation technical overview was presented at PlayStation Meeting 1999, and big impact on all over the world! EE#2 Design completed as scheduled and achieved 300MHz Target EE#3 Shrunken version(0.18um) development has been started Copyright © 2009 Toshiba Corporation, All rights reserved.
Load more

Recommended publications
  • Efficient Checker Processor Design
    Efficient Checker Processor Design Saugata Chatterjee, Chris Weaver, and Todd Austin Electrical Engineering and Computer Science Department University of Michigan {saugatac,chriswea,austin}@eecs.umich.edu Abstract system works to increase test space coverage by proving a design is correct, either through model equivalence or assertion. The approach is significantly more efficient The design and implementation of a modern micro- than simulation-based testing as a single proof can ver- processor creates many reliability challenges. Design- ify correctness over large portions of a design’s state ers must verify the correctness of large complex systems space. However, complex modern pipelines with impre- and construct implementations that work reliably in var- cise state management, out-of-order execution, and ied (and occasionally adverse) operating conditions. In aggressive speculation are too stateful or incomprehen- our previous work, we proposed a solution to these sible to permit complete formal verification. problems by adding a simple, easily verifiable checker To further complicate verification, new reliability processor at pipeline retirement. Performance analyses challenges are materializing in deep submicron fabrica- of our initial design were promising, overall slowdowns tion technologies (i.e. process technologies with mini- due to checker processor hazards were less than 3%. mum feature sizes below 0.25um). Finer feature sizes However, slowdowns for some outlier programs were are generally characterized by increased complexity, larger. more exposure to noise-related faults, and interference In this paper, we examine closely the operation of the from single event radiation (SER). It appears the current checker processor. We identify the specific reasons why advances in verification (e.g., formal verification, the initial design works well for some programs, but model-based test generation) are not keeping pace with slows others.
    [Show full text]
  • Mipspro C++ Programmer's Guide
    MIPSproTM C++ Programmer’s Guide 007–0704–150 CONTRIBUTORS Rewritten in 2002 by Jean Wilson with engineering support from John Wilkinson and editing support from Susan Wilkening. COPYRIGHT Copyright © 1995, 1999, 2002 - 2003 Silicon Graphics, Inc. All rights reserved; provided portions may be copyright in third parties, as indicated elsewhere herein. No permission is granted to copy, distribute, or create derivative works from the contents of this electronic documentation in any manner, in whole or in part, without the prior written permission of Silicon Graphics, Inc. LIMITED RIGHTS LEGEND The electronic (software) version of this document was developed at private expense; if acquired under an agreement with the USA government or any contractor thereto, it is acquired as "commercial computer software" subject to the provisions of its applicable license agreement, as specified in (a) 48 CFR 12.212 of the FAR; or, if acquired for Department of Defense units, (b) 48 CFR 227-7202 of the DoD FAR Supplement; or sections succeeding thereto. Contractor/manufacturer is Silicon Graphics, Inc., 1600 Amphitheatre Pkwy 2E, Mountain View, CA 94043-1351. TRADEMARKS AND ATTRIBUTIONS Silicon Graphics, SGI, the SGI logo, IRIX, O2, Octane, and Origin are registered trademarks and OpenMP and ProDev are trademarks of Silicon Graphics, Inc. in the United States and/or other countries worldwide. MIPS, MIPS I, MIPS II, MIPS III, MIPS IV, R2000, R3000, R4000, R4400, R4600, R5000, and R8000 are registered or unregistered trademarks and MIPSpro, R10000, R12000, R1400 are trademarks of MIPS Technologies, Inc., used under license by Silicon Graphics, Inc. Portions of this publication may have been derived from the OpenMP Language Application Program Interface Specification.
    [Show full text]
  • SPIM S20: a MIPS R2000 Simulator∗
    SPIM S20: A MIPS R2000 Simulator∗ 1 th “ 25 the performance at none of the cost” James R. Larus [email protected] Computer Sciences Department University of Wisconsin–Madison 1210 West Dayton Street Madison, WI 53706, USA 608-262-9519 Copyright °c 1990–1997 by James R. Larus (This document may be copied without royalties, so long as this copyright notice remains on it.) 1 SPIM SPIM S20 is a simulator that runs programs for the MIPS R2000/R3000 RISC computers.1 SPIM can read and immediately execute files containing assembly language. SPIM is a self- contained system for running these programs and contains a debugger and interface to a few operating system services. The architecture of the MIPS computers is simple and regular, which makes it easy to learn and understand. The processor contains 32 general-purpose 32-bit registers and a well-designed instruction set that make it a propitious target for generating code in a compiler. However, the obvious question is: why use a simulator when many people have workstations that contain a hardware, and hence significantly faster, implementation of this computer? One reason is that these workstations are not generally available. Another reason is that these ma- chine will not persist for many years because of the rapid progress leading to new and faster computers. Unfortunately, the trend is to make computers faster by executing several instruc- tions concurrently, which makes their architecture more difficult to understand and program. The MIPS architecture may be the epitome of a simple, clean RISC machine. In addition, simulators can provide a better environment for low-level programming than an actual machine because they can detect more errors and provide more features than an actual computer.
    [Show full text]
  • Microprocessors History of Computing Nouf Assaid
    MICROPROCESSORS HISTORY OF COMPUTING NOUF ASSAID 1 Table of Contents Introduction 2 Brief History 2 Microprocessors 7 Instruction Set Architectures 8 Von Neumann Machine 9 Microprocessor Design 12 Superscalar 13 RISC 16 CISC 20 VLIW 23 Multiprocessor 24 Future Trends in Microprocessor Design 25 2 Introduction If we take a look around us, we would be sure to find a device that uses a microprocessor in some form or the other. Microprocessors have become a part of our daily lives and it would be difficult to imagine life without them today. From digital wrist watches, to pocket calculators, from microwaves, to cars, toys, security systems, navigation, to credit cards, microprocessors are ubiquitous. All this has been made possible by remarkable developments in semiconductor technology enabling in the last 30 years, enabling the implementation of ideas that were previously beyond the average computer architect’s grasp. In this paper, we discuss the various microprocessor technologies, starting with a brief history of computing. This is followed by an in-depth look at processor architecture, design philosophies, current design trends, RISC processors and CISC processors. Finally we discuss trends and directions in microprocessor design. Brief Historical Overview Mechanical Computers A French engineer by the name of Blaise Pascal built the first working mechanical computer. This device was made completely from gears and was operated using hand cranks. This machine was capable of simple addition and subtraction, but a few years later, a German mathematician by the name of Leibniz made a similar machine that could multiply and divide as well. After about 150 years, a mathematician at Cambridge, Charles Babbage made his Difference Engine.
    [Show full text]
  • Three-Dimensional Integrated Circuit Design: EDA, Design And
    Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change.
    [Show full text]
  • MIPS IV Instruction Set
    MIPS IV Instruction Set Revision 3.2 September, 1995 Charles Price MIPS Technologies, Inc. All Right Reserved RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and / or in similar or successor clauses in the FAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the Copyright Laws of the United States. Contractor / manufacturer is MIPS Technologies, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94039-7311. R2000, R3000, R6000, R4000, R4400, R4200, R8000, R4300 and R10000 are trademarks of MIPS Technologies, Inc. MIPS and R3000 are registered trademarks of MIPS Technologies, Inc. The information in this document is preliminary and subject to change without notice. MIPS Technologies, Inc. (MTI) reserves the right to change any portion of the product described herein to improve function or design. MTI does not assume liability arising out of the application or use of any product or circuit described herein. Information on MIPS products is available electronically: (a) Through the World Wide Web. Point your WWW client to: http://www.mips.com (b) Through ftp from the internet site “sgigate.sgi.com”. Login as “ftp” or “anonymous” and then cd to the directory “pub/doc”. (c) Through an automated FAX service: Inside the USA toll free: (800) 446-6477 (800-IGO-MIPS) Outside the USA: (415) 688-4321 (call from a FAX machine) MIPS Technologies, Inc.
    [Show full text]
  • Average Memory Access Time: Reducing Misses
    Review: Cache performance 332 Miss-oriented Approach to Memory Access: Advanced Computer Architecture ⎛ MemAccess ⎞ CPUtime = IC × ⎜ CPI + × MissRate × MissPenalt y ⎟ × CycleTime Chapter 2 ⎝ Execution Inst ⎠ ⎛ MemMisses ⎞ CPUtime = IC × ⎜ CPI + × MissPenalt y ⎟ × CycleTime Caches and Memory Systems ⎝ Execution Inst ⎠ CPIExecution includes ALU and Memory instructions January 2007 Separating out Memory component entirely Paul H J Kelly AMAT = Average Memory Access Time CPIALUOps does not include memory instructions ⎛ AluOps MemAccess ⎞ These lecture notes are partly based on the course text, Hennessy CPUtime = IC × ⎜ × CPI + × AMAT ⎟ × CycleTime and Patterson’s Computer Architecture, a quantitative approach (3rd ⎝ Inst AluOps Inst ⎠ and 4th eds), and on the lecture slides of David Patterson and John AMAT = HitTime + MissRate × MissPenalt y Kubiatowicz’s Berkeley course = ()HitTime Inst + MissRate Inst × MissPenalt y Inst + ()HitTime Data + MissRate Data × MissPenalt y Data Advanced Computer Architecture Chapter 2.1 Advanced Computer Architecture Chapter 2.2 Average memory access time: Reducing Misses Classifying Misses: 3 Cs AMAT = HitTime + MissRate × MissPenalt y Compulsory—The first access to a block is not in the cache, so the block must be brought into the cache. Also called cold start misses or first reference misses. There are three ways to improve cache (Misses in even an Infinite Cache) Capacity—If the cache cannot contain all the blocks needed during performance: execution of a program, capacity misses will occur due to blocks being discarded and later retrieved. (Misses in Fully Associative Size X Cache) 1. Reduce the miss rate, Conflict—If block-placement strategy is set associative or direct mapped, conflict misses (in addition to compulsory & capacity misses) will 2.
    [Show full text]
  • MIPS Architecture • MIPS (Microprocessor Without Interlocked Pipeline Stages) • MIPS Computer Systems Inc
    Spring 2011 Prof. Hyesoon Kim MIPS Architecture • MIPS (Microprocessor without interlocked pipeline stages) • MIPS Computer Systems Inc. • Developed from Stanford • MIPS architecture usages • 1990’s – R2000, R3000, R4000, Motorola 68000 family • Playstation, Playstation 2, Sony PSP handheld, Nintendo 64 console • Android • Shift to SOC http://en.wikipedia.org/wiki/MIPS_architecture • MIPS R4000 CPU core • Floating point and vector floating point co-processors • 3D-CG extended instruction sets • Graphics – 3D curved surface and other 3D functionality – Hardware clipping, compressed texture handling • R4300 (embedded version) – Nintendo-64 http://www.digitaltrends.com/gaming/sony- announces-playstation-portable-specs/ Not Yet out • Google TV: an Android-based software service that lets users switch between their TV content and Web applications such as Netflix and Amazon Video on Demand • GoogleTV : search capabilities. • High stream data? • Internet accesses? • Multi-threading, SMP design • High graphics processors • Several CODEC – Hardware vs. Software • Displaying frame buffer e.g) 1080p resolution: 1920 (H) x 1080 (V) color depth: 4 bytes/pixel 4*1920*1080 ~= 8.3MB 8.3MB * 60Hz=498MB/sec • Started from 32-bit • Later 64-bit • microMIPS: 16-bit compression version (similar to ARM thumb) • SIMD additions-64 bit floating points • User Defined Instructions (UDIs) coprocessors • All self-modified code • Allow unaligned accesses http://www.spiritus-temporis.com/mips-architecture/ • 32 64-bit general purpose registers (GPRs) • A pair of special-purpose registers to hold the results of integer multiply, divide, and multiply-accumulate operations (HI and LO) – HI—Multiply and Divide register higher result – LO—Multiply and Divide register lower result • a special-purpose program counter (PC), • A MIPS64 processor always produces a 64-bit result • 32 floating point registers (FPRs).
    [Show full text]
  • Understanding Performance Numbers in Integrated Circuit Design Oprecomp Summer School 2019, Perugia Italy 5 September 2019
    Understanding performance numbers in Integrated Circuit Design Oprecomp summer school 2019, Perugia Italy 5 September 2019 Frank K. G¨urkaynak [email protected] Integrated Systems Laboratory Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 2/74 Who Am I? Born in Istanbul, Turkey Studied and worked at: Istanbul Technical University, Istanbul, Turkey EPFL, Lausanne, Switzerland Worcester Polytechnic Institute, Worcester MA, USA Since 2008: Integrated Systems Laboratory, ETH Zurich Director, Microelectronics Design Center Senior Scientist, group of Prof. Luca Benini Interests: Digital Integrated Circuits Cryptographic Hardware Design Design Flows for Digital Design Processor Design Open Source Hardware Integrated Systems Laboratory Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 3/74 What Will We Discuss Today? Introduction Cost Structure of Integrated Circuits (ICs) Measuring performance of ICs Why is it difficult? EDA tools should give us a number Area How do people report area? Is that fair? Speed How fast does my circuit actually work? Power These days much more important, but also much harder to get right Integrated Systems Laboratory The performance establishes the solution space Finally the cost sets a limit to what is possible Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 4/74 System Design Requirements System Requirements Functionality Functionality determines what the system will do Integrated Systems Laboratory Finally the cost sets a limit
    [Show full text]
  • Optimal Software Pipelining: Integer Linear Programming Approach
    OPTIMAL SOFTWARE PIPELINING: INTEGER LINEAR PROGRAMMING APPROACH by Artour V. Stoutchinin Schooi of Cornputer Science McGill University, Montréal A THESIS SUBMITTED TO THE FACULTYOF GRADUATESTUDIES AND RESEARCH IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTEROF SCIENCE Copyright @ by Artour V. Stoutchinin Acquisitions and Acquisitions et Bibliographie Services services bibliographiques 395 Wellington Street 395. nie Wellington Ottawa ON K1A ON4 Ottawa ON KI A ON4 Canada Canada The author has granted a non- L'auteur a accordé une licence non exclusive licence allowing the exclusive permettant à la National Library of Canada to Bibliothèque nationale du Canada de reproduce, loan, distribute or sell reproduire, prêter, distribuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic formats. la fome de microfiche/^, de reproduction sur papier ou sur format électronique. The author retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantialextracts fiom it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permission. autorisation- Acknowledgements First, 1 thank my family - my Mom, Nina Stoutcliinina, my brother Mark Stoutchinine, and my sister-in-law, Nina Denisova, for their love, support, and infinite patience that comes with having to put up with someone like myself. I also thank rny father, Viatcheslav Stoutchinin, who is no longer with us. Without them this thesis could not have had happened.
    [Show full text]
  • Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN)
    Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN). [Chapters 1, 2] • Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] Week 2 • MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] • Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4] Week 3 • CPU Organization: Datapath & Control Unit Design. [Chapter 5] Week 4 – MIPS Single Cycle Datapath & Control Unit Design. – MIPS Multicycle Datapath and Finite State Machine Control Unit Design. Week 5 • Microprogrammed Control Unit Design. [Chapter 5] – Microprogramming Project Week 6 • Midterm Review and Midterm Exam Week 7 • CPU Pipelining. [Chapter 6] • The Memory Hierarchy: Cache Design & Performance. [Chapter 7] Week 8 • The Memory Hierarchy: Main & Virtual Memory. [Chapter 7] Week 9 • Input/Output Organization & System Performance Evaluation. [Chapter 8] Week 10 • Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Week 11 • Final Exam. EECC550 - Shaaban #1 Lec # 1 Winter 2005 11-29-2005 Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals • Computing Element Choices: – Computing Element Programmability – Spatial vs. Temporal Computing – Main Processor Types/Applications • General Purpose Processor Generations • The Von Neumann Computer Model • CPU Organization (Design) • Recent Trends in Computer Design/performance • Hierarchy
    [Show full text]
  • IDT79R4600 and IDT79R4700 RISC Processor Hardware User's Manual
    IDT79R4600™ and IDT79R4700™ RISC Processor Hardware User’s Manual Revision 2.0 April 1995 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any respon- sibility for use of any circuitry described other than the circuitry embodied in an IDT product. ITD makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights, or other rights of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology’s products are not authorized for use as critical components in life sup- port devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accor- dance with instructions for use provided in the labeling, can be reasonably expected to result in a sig- nificant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
    [Show full text]