Analog Integrated Circuits

Jieh-Tsorng Wu 6 de febrero de 2003

1. Introduction Complete Small-Signal Model with Extrinsic Components 2. PN Junctions and Bipolar Junction Transis- tors Typical values of Extrinsic Components PN Junctions 3. MOS Transistors Small-Signal Junction Capacitance MOS Transistors Large-Signal Junction Capacitance Strong Inversion PN Junction in Forward Bias Channel Charge Transfer Characteristics PN Junction Avalanche Breakdown Simpliﬁed Channel Charge Transfer Charac- PN Junction Breakdown teristics

Bipolar Junction Transistor (BJT) MOST I-V Characteristics

Minority Carrier Current in the Base Region Threshold Voltage

Gummel Number (G) Square-Law I-V Characteristics

Base Transport Current Channel-Length Modulation

Forward Current Gain MOST Small-Signal Model in Saturation Re- gion BJT DC Large-Signal Model in Forward- Active Region OST Small-Signal Model in Saturation Re- gion Dependence of BF on Operating Condition MOST Small-Signal Capacitances in Satura- Collector Voltage Effects tion Region Base Transport Model Channel Capacitance in Saturation Region Ebers-Moll Model Complete MOST Small-Signal Model in Sat- Leakage Current uration Region

Common-Base Transistor Breakdown MOST Small-Signal Model in Triode Region

Common-Emitter Transistor Breakdown MOST Small-Signal Model in Cutoff Region

Small-Signal Model of Forward-Biased BJT Carrier Velocity Saturation

Charge Storage Effects of Carrier Velocity Saturation

1 Hot Carriers 5. Single-Transistor Gain Stages

Short-Channel Effects Unilateral Two-Port Network

Subthreshold Conduction in MOST Common-Emitter Conﬁguration Common-Emitter Conﬁguration - Bias Analy- 4. Integrated Circuit Technologies sis

Integrated-Circuit NPN Transistor Common-Emitter Configuration - Small- Lateral PNP Transistor Signal Analysis Common-Source Amplifier Vertical PNP Transistors Common-Source Configuration - Small- Advanced-Technology NPN Transistor Signal Analysis Base and Emitter Diffused Resistors Common-Emitter Configuration Small-Signal Base Pinch Resistor AC Analysis

Epitaxial Resistor Common-Source Conﬁguration Small-Signal AC Analysis Properties of IC Resistor Miller Approximation Capacitors Miller Approximation Equivalent Circuit Diodes Short-Circuit Current Gain CMOS Integrated-Circuit Technologies BJT Transition Frequency MOS Transistors MOST Transition Frequency Parasitic BJTs in CMOS Technologies MOST Transition Frequency - Weak Inversion Resistors in CMOS Technologies Complete AC Analysis of Common- Capacitors in CMOS Technologies Emitter(Source) Ampliﬁer

Matching Issues Complete AC Analysis of Common- Emitter(Source) Ampliﬁer Guidelines for Better Device Matching Common-Emitter Ampliﬁer with Emitter De- Transistor Pair Layout Example generation

Resistor Pair Layout Example Common-Emitter Ampliﬁer with Emitter De- generation Capacitor Pair Layout Example Common-Source Ampliﬁer with Source De- Capacitor Errors generation

Capacitor Layout Design Common-Base Conﬁguration

Analog Section Floor Plan Example Common-Base Conﬁguration AC Analysis

Noise-Coupling Layout Considerations Common-Gate Conﬁguration

Latch-Up in CMOS Technologies Common-Gate Configuration AC Analysis Common-Collector Configuration (Emitter 7. Differential Gain Stages Follower) Emitter-Coupled Pair Emitter Follower’s Voltage Gain Emitter-Coupled Pair Large-Signal Behavior Emitter Follower’s Input Impedance Emitter-Coupled Pair with Emitter Degenera- tion Emitter Follower’s Output Impedance Source-Coupled Pair Common-Drain Configuration (Source Fol- lower) Source-Coupled Pair Large-Signal Behavior

Source Follower’s Gate Voltage Gain Small-Signal Analysis of Differential Ampli- ﬁers Source Follower’s Gate Input Impedance Emitter-Coupled Pair Differential-Mode Half Source Follower’s Output Impedance Circuit

Source Follower’s Complete Frequency Re- Emitter-Coupled Pair Common-Mode Half sponse Circuit Emitter-Coupled Pair Input Resistances Compensated Source Follower Emitter-Coupled Pair Frequency Response Floating-Well Source Follower Emitter-Coupled Pair Input Offset Voltage and Current 6. Multiple-Transistor Gain Stages Dominant-Pole Approximation Emitter-Coupled Pair Input Offset Voltage Source-Coupled Pair Input Offset Voltage Zero-Value Time Constants Unbalanced Resistor Circuit Analysis Zero-Value Time Constant Example Unbalanced gm Circuit Analysis Darlington Configuration Unbalanced Differential Amplifier BJT Cascode Configuration Simplified Analysis for Unbalanced Differen- BJT Cascode Characteristics tial Amplifier

MOST Cascode Configuration 8. Current Mirrors and Active Loads MOST Cascode Low-Frequency Characteris- Simple BJT Current Mirror tics Simple BJT Current Mirror with Beta Helper MOST Cascode Zero-Value Time Constant Simple BJT Current Mirror with Emitter De- Analysis generation MOST Cascode AC Characteristics Matching Consideration in BJT Current Mir- rors Active Cascode Configuration Simple MOST Current Mirror Active Cascode Characteristics Matching Consideration in Simple MOST Super Source Follower Configuration Current Mirror Layout Considerations Self-Biasing MOST VBE and UT Referenced Current Source BJT Cascode Current Mirror Band-Gap References MOST Cascode Current Mirror Kujik Band-Gap References MOST High-Swing Cascode Current Mirror Ahuja Band-gap Reference MOST Sooch Cascode Current Mirror Brokaw Band-Gap References MOST Low-Voltage High-Swing Cascode Widlar Band-Gap Reference Current Mirror Song Band-Gap Reference Säckinger Current Mirror Band-Gap Reference Output Issues Gatti Current Mirror 10. Output Stages BJT Wilson Current Mirror Output Stage Requirements MOST Wilson Current Mirror Output Stage Design Issues Complementary Current Source Load Nonlinearity and Harmonic Distortion Current Mirror Load Class-A BJT Emitter Follower Diode-Connected Load Class-A BJT Emitter Follower Output Power Instantaneous Power Dissipation 9. Voltage and Current References Class-A MOST Source Follower Sensitivity and Temperature Coefficient Distortion in the MOST Source Follower Simple Current Sources Class-A BJT Common-Emitter Stage BJT Widlar Current Source Distortion in Class-A BJT Common-Emitter MOST Widlar Current Source Stage

BJT Peaking Current Source Class-A MOST Common-Source Stage Class-B Push-Pull Emitter Follower MOST Peaking Current Source Output Power of Class-B Push-Pull Emitter BJT VBE Referenced Current Source Follower MOST Vt Referenced Current Source Class-AB Push-Pull Emitter Followers Self-Biasing BJT VBE Reference Class-AB Push-Pull Source Followers

Self-Biasing BJT VBE Reference with Start- Class-AB Push-Pull Common-Source Stage Up Circuit Class-AB Quasi-Complementary Configura- Self-Biasing BJT UT Reference tion An Error Amplifier Example Self-Biasing MOST Vt Referenced Current Source Combined Common-Drain Common-Source Configuration Self-Biasing MOST gm Referenced Current Source Parallel Common-Source Configuration 11. Noise Analysis and Modelling Noise Factor of an FET Common-Source Stage Noise in Time Domain Noise Performance of Other Configurations Probability Density Function Emitter-Coupled Pair Noise Performance Noise in Frequency Domain Effect of Ideal Feedback on Noise Perfor- Filtered Noise mance Noise Summation Effect of Input Series Feedback Feedback on Piecewise Integration of Noise Noise Performance Thermal Noise Effect of Input Shunt Feedback Feedback on Noise Performance Thermal Noise with Loading Effect of Feedback on Noise Performance Shot Noise Effect of Cµ on Noise Performance Flicker Noise (1/f Noise) Single-Stage Amplifier with Local Feedback BJT Noise Model Operational Amplifier Noise Model FET Noise Model A Low-Pass Filter Example Equivalent Input Noise Generators A Current Amplifier Example Noise Factor and Input Noise Generators Noise Generators of a BJT Common-Emitter 12. Feedback and Compensation Stage Feedback Noise Voltage Generator of a BJT Common- Effect of Negative Feedback on Distortion Emitter Stage Series-Shunt Feedback Configuration Noise Current Generator of a BJT Common- Emitter Stage Shunt-Shunt Feedback Configuration BJT Equivalent Input Shot Noise Spectral Shunt-Series Feedback Configuration Density Series-Series Feedback Configuration Total Equivalent Noise Voltage of a BJT Common-Emitter Stage Two-Port Analysis of Feedback Amplifier Noise Generators of a FET Common-Source Loading Approximation Method Stage Two-Port Analysis of a Shunt-Shunt Feedback Noise Voltage Generator of a FET Common- Amplifier Source Stage Return Ratio MOST Equivalent Input Noise Voltage Spec- Closed-Loop Gain Using Return Ratio tral Density Blackman’s Impedance Formula Noise Current Generator of a FET Common- Source Stage A Transresistance Feedback Amplifier Noise Factor of a BJT Common-Emitter Stage Frequency Response of Feedback Amplifiers Single-Pole Model Input Stage Common-Mode Transconduc- tance Nyquist Diagram Input Stage Voltage Gain Nyquist Criterion Simplified Two-Stage Model Phase Margin Pseudo Dominant-Pole Model Frequency Compensation Using Nulling Re- sistor Phase Margin of the Pseudo Dominant-Pole Model Frequency Compensation Using Zero-Nulling Resistor Closed-Loop Response of the Pseudo Dominant-Pole Model Voltage and Current Range Quality Factor (Q) and Phase Margin Slew Rate Dominant-Pole Compensation Settling Time Dominant-Pole Compensation Input Impedance

Miller (Pole-Splitting) Compensation Output Impedance

Feedforward Zero in Miller Compensation Systematic Input Offset Voltage

Miller Compensation With Unity-Gain Buffer Random Input Offset Voltage

Miller Compensation With Common-Gate Input Offset Voltage and Common-Mode Re- Stage jection Ratio Miller Compensation With Nulling Resistor CMRR Due to Systematic and Random Offset Miller Compensation with Feedforward Mismatches and Input Stage Transconduc- Transconductor tance Nested-Miller Compensation Power Supply Rejection Ratio (PSRR) Zeros in the Nested-Miller Compensation Power Supply Rejection Ratio (PSRRSS) Nested-Miller Compensation with Feedfor- ward Transconductors Power Supply Rejection Ratio (PSRRDD) PSRRDD with Common-Gate Miller Com- 13.Basic Two-Stage Operational Amplifier De- pensation sign Supply Capacitance Ideal Operational Amplifier Power-Supply Rejection and Supply Capaci- Basic 2-Stage CMOS Opamp tance Constant gm Bias Generator Device Noise Analysis Input Stage Small-Signal Model Thermal Noise Performance Input Stage Output Impedance Flicker Noise Performance Input Stage Differential-Mode Transconduc- tance 2-Stage Opamp with pMOST Input Stage 14. Operational Amplifiers with Single-Ended Class-AB Operational Amplifier Outputs Fully Differential Operational Amplifiers Two-Stage Operational Amplifier with Cas- code Active-Cascode Telescopic Operational Am- plifier Telescopic-Cascode Operational Amplifier Fully Differential Gain-Enhancement Auxil- Folded-Cascode Operational Amplifier iary Amplifiers Current-Mirror Operational Amplifier Replica-Tail Feedback Rail-to-Rail Complementary Input Stage 16. Operational Amplifiers and Their Basic A Rail-to-Rail Input/Output Opamp Configurations

Low-Voltage Multi-Stage Opamp Ideal Operational Ampliﬁer

Current-Feedback Conﬁguration Operational Ampliﬁer Imperfections (I)

A CMOS Current-Feedback Driver Operational Ampliﬁer Imperfections (II)

A General-Purpose BJT Current-Feedback Operational Ampliﬁer Imperfections (III) Opamps Operational Ampliﬁer Imperfections (IV)

15.Fully Differential Operational Amplifiers Inverting Configuration Fully Balanced Circuit Topology Examples of Inverting Configuration

Small-Signal Models for Differential Loading Inverting Summer Conﬁguration

Small-Signal Models for Differential Signal Noninverting Configuration Sources Switched-Capacitor Applications Common-Mode Feedback (CMFB) Switched-Capacitor Step Response A Fully Differential Two-Stage Operational Amplifier 17. Analog Switches and Sample-and-Hold Cir- cuits CMFB Using Resistive Divider and Error Am- plifier Sample-and-Hold (Track-and-Hold) Circuits CMFB Using Resistive Divider and Direct MOST Switches in Sample Mode Current Injection MOST Switches from Sample to Hold Mode CMFB Using Dual Differential Pairs Switching Errors in Slow-Gating MOST CMFB Using Transistors in the Triode Region Switches Switched-Capacitor CMFB Switching Errors in Fast-Gating MOST Switches Folded-Cascode Operational Amplifier MOST S/H Speed-Precision Tradeoff Current-Mirror Operational Amplifier Aperture Jitter Due to the Finite Falling Time Current-Mirror Push-Pull Operational Ampli- fier Thermal Noise in MOST S/H Charge Compensation for MOST Switches Comparison with Positive-Feedback Regener- ation Differential Sampling Output Offset Storage (OOS) Bottom-Plate Sampling Multistage Output Offset Storage Complementary Analog Switches Input Offset Storage (IOS) A Differential BJT Sampling Switch Multistage Input Offset Storage A Differential BJT Sampling Switch MOST Comparator: Auto-Zeroing Inverter Open-Loop MOST S/H MOST Comparator: Cascaded Auto-Zeroing MOST S/H Using Miller Holding Capacitor Inverters MOST S/H Using Miller Capacitor and MOST Comparator: Preamp + Regenerative Bottom-Plate Sampling Sense Amplifier MOST S/H Using Double Miller Capacitors MOST Comparator: Merged Preamp + Sense A MOST Recycling S/H Amplifier Closed-Loop S/H Offset Canceled Latches: Idea Closed-Loop S/H with Improved tslew Offset Canceled Latches: Simplified Schemat- ic Closed-Loop S/H Using Active Integrator Offset Canceled Latches: MOST Implementa- An RC Closed-Loop S/H tion

A Switched-Capacitor Closed-Loop S/H BJT Latched Comparator

Charge Redistribution Sampled-Data Amplifi- BJT Comparator with High-Level Latch er A Sampled-Data Amplifier with Internal Off- Charge Redistribution Sampled-Data Amplifi- set Cancellation er Operational Amplifier with Offset Compensa- Charge Redistribution Summing Amplifier tion

Sampled-Data Ampliﬁer with CDS The Chopper Stabilization Technique

A Capacitive-Reset Sampled-Data Ampliﬁer A Chopper Operational Ampliﬁer

A Capacitive-Reset CDS Ampliﬁer Residual Offset of Chopper Ampliﬁer

18. Comparators and Offset Cancellation Tech- Chopper Modulation with Guard Time niques 19. Oscillators Comparators The Barkhausen Criteria Comparator Design Considerations Three-Stage Ring Oscillator Comparison with Single-Pole Amplifier Three-Stage CMOS Inverter Ring Oscillator Comparison with Multi-Stage Cascaded Am- plifier Four-Stage Differential Ring Oscillator Differential Delay Stage Second-Order Band-Reject (BR) Filter - Low- Pass Notch (LPN) Delay Variation Using Variable Resistors Second-Order Band-Reject (BR) Filter - High- Delay Variation Using Positive Feedback Pass Notch (HPN) Delay Variation Using Interpolation Second-Order Band-Reject (BR) Filter - Sym- metrical Notch LC-Tuned Delay Stage Second-Order All-Pass (AP) Filter LC-Tuned Ring Oscillators Maximally Flat (Butterworth) Filters Colpitts Oscillator Equi-Ripple (Chebyshev) Filters One-Port Oscillators Elliptic (Cauer) Filters The van der Pol Approximation Comparison of the Classical Filter Responses A CMOS SONY Oscillator Linear-Phase (Bessel-Thomson) Filters Differential CMOS SONY Oscillators All-Pass Filter (Delay Equalizer) Specifica- Single-Transistor Negative Resistance Gener- tions ator Frequency Transformations Piezoelectric Crystals High-Order Filters Crystal Oscillators LC Ladder Filters Relaxation Oscillators (Multivibrators) Sensitivity Constant-Current Charge/Discharge Oscilla- tors Transfer Function Sensitivity Second-Order Filter Sensitivity The Banu Oscillator High-Order Filter Sensitivity A CMOS Relaxation Oscillator

A Emitter-Coupled Multivibrator 21. Active-RC Filters Capacitor Integrators 20. Fundamentals of Analog Filters Filters Active-RC Inverting Integrators Low-Pass Filter Specifications Actively Compensated Inverting Integrator High-Pass Filter Specifications Noninverting Integrator Band-Pass Filter Specifications Phase-Lead Noninverting Integrator Band-Reject Filter Specifications First-Order Filters Second-Order Filter (Biquadratic Function) Single-Amplifier 2nd-Order Filters -Sallen- Second-Order Low-Pass (LP) Filter Key LP Biquad Second-Order High-Pass (HP) Filter State-Variable Second-Order Filters Second-Order Band-Pass (BP) Filter Tow-Thomas (TT) Biquad Ackerberg-Mossberg (AM) Biquad MOST Transconductors with Source Degen- eration Arbitrary Transmission Zeros by Summing BJT Transconductors Arbitrary Transmission Zeros by Voltage Feedforward Multi-Input Transconductors High-Order Filter Using Cascade Topology Transconductor’s Imperfections Cascaded Filter Design Procedures The Effect of Non-Zero go on Gyrators High-Order Filter Using the Follow-the- Leader Feedback Topology The Effect of Phase Shift on Gyrators High-Order Filter LC Ladder Simulation Gm-C First-Order Filters LC Ladder Simulation Gm-C Second-Order Filters An All-Pole Low-Pass Ladder Filter Gm-C First-Oder Filters Using Miller Integra- Signal-Level Scaling in Ladder Filters tors General Ladder Branches Gm-C Second-Oder Filters Using Miller Inte- General Ladder Branches by Active-RC Im- grators plementation Ladder Filter Using Simulated Gyrators Finite Transmission Zeros in the Series Branches Ladder Filter Using Signal-Flow Graph

22. MOST-C and Gm-C Filters Gm-C Simulation of Ladder Branches (I) MOSTs in the Triode Region Gm-C Simulation of Ladder Branches (II) MOST-C Fully-Balanced Integrators Gm-C Resonators Double MOST-C Differential Integrators Gm-C Quadrature Oscillators R-MOST-C Differential Integrators On-Chip Tuning Strategies A MOST-C Tow-Thomas Biquad

Transconductors Separate Frequency and Q Control

Transconductor Basic Circuits Gm Tuning

Gm-C Lossy Integrator Frequency Tuning Using Switched Capacitors Fully-Differential Gm-C Integrators Frequency Tuning Using Response Detection Gm-C Opamp Integrators (Miller Integrators) Frequency Tuning Using Phase-Locked Loop Gyrators Q-Factor Tuning Using MLL Gm-C Simulated Gyrators

MOST Transconductors Q-Factor Tuning Using LMS 23. Switched-Capacitor Filters Time-Staggered SC Stages Switched-Capacitor Equivalent Resistor Capacitor Scaling Switched-Capacitor Integrators Output Capacitor Scaling SC Integrator Analysis Input Capacitor Scaling SC Differential Integrators An All-Pole Low-Pass Ladder Filter Effects of Parasitic Capacitances An All-Pole Low-Pass SC Ladder Filter Parasitics-Insensitive SC Integrators SC Ladder Filter Using Signal-Flow Graph Fully Differential SC Integrators SC Ladder Filters Design Methodology MOST Analog Switches SC Ladder Filters Design Procedures Effects of Opamp’s Finite DC Gain 24. Niquist-Rate Digital-to-Analog Converters Effects of Opamp’s DC Offset A/D and D/A Interfaces An Offset Auto-Zeroing Scheme Continuous-to-Discrete Conversion Effects of Opamp’s Finite Settling Time Discrete-to-Continuous Conversion An SC Integrator with CDS Imperfections in Discrete-to-Continuous Con- Discrete-Time Signal Processing version Continuous-Time Signals D/A Transfer Characteristic Discrete-Time Signals D/A Nonlinearity s-to-z Transformation D/A Performance Metrics - Static Character- istics Bilinear s-to-z Transformation D/A Performance Metrics - Dynamic Charac- Hc(s) to H(z) Design Procedures for Bilinear teristics Transformation Dynamic Range Switched-Capacitor Filter Systems Resistor-String DACs with Digital Decoding Design Constraints Folded R-String DACs with Digital Decoding Periodic Time-Variance in Biphase SC Filters R-String DACs with Binary-Tree Decoding Active Switched-Capacitor Integrators Intermeshed Resistor-String DACs (One- SC First-Order Filters Level Multiplexing) Switch Sharing Intermeshed Resistor-String DACs (Two- Bilinear SC First-Order Filters Level Multiplexing) SC Second-Order Filters Binary-Weighted Current-Steering DACs A Low-Q SC Biquad Binary-Weighted R-2R Networks A High-Q SC Biquad Equally-Weighted Current-Steering DACs The Matrix Floorplan Digital Encoding for the Quantized- Feedforward Architecture A Current Cell Example

Charge-Redistribution DACs A Radix-2 1ff5 Bit SC Pipeline Stage

Segmented DAC Architecture Multi-Bit Switched-Capacitor Pipeline Stage

A 10-Bit Segmented Current-Steering DAC Switched-Capacitor Pipelined ADCs

A Segmented Current-Steering DAC Single-Stage Calibration and Digital Correc- Dynamically-Matched Current Sources tion

A Segmented Charge-Redistribution DAC Multi-Stage Calibration and Digital Correc- tion A Capacitor-Resistor Hybrid DAC Calibration of A Radix-2 1ff5 Bit SC Pipeline 25. Niquist-Rate Analog-to-Digital Converters Stage

A/D and D/A Interfaces A Radix-2 Cyclic ADCs Continuous-to-Discrete Conversion A Radix-2 Switched-Capacitor Cyclic ADC A/D Quantization Characteristic A CMOS Subranging Flash ADC - Dingwall Imperfections in A/D Quantization Character- istic A CMOS Subranging Flash ADC - Brandt Quantization Noise Interpolated Differential Comparator Bank Sampling-Time Uncertainty (Aperture Jitter) A CMOS Subranging Flash ADC - Brandt DFT Nonlinearity Test of ADCs Flash Quantization Architecture Code Density Test of ADCs

Serial (Integrating) Architectures Resistor-String Interpolation

Parallel (Flash) Architectures Folding

Successive Approximation Architectures Interpolation and Folding

Charge-Redistribution ADC Averaging Preampliﬁers C-R ADCs Using Input Offset Storage Tech- nique Effects of Averaging

Self-Calibrating Charge-Redistribution ADCs Bending at the Edges Due to Averaging

Quantized-Feedforward (Subranging) Archi- Cascaded Folding tectures Differential Preampliﬁer Quantized-Feedforward Minimal Design

Over-Range in the Minimal Design A CMOS 10-Bit Folding ADC - Bult

Quantized-Feedforward Redundant Design Time-Interleaved Architectures 26.Oversampling Converters General Mismatch-Shaping DAC - First-Order Example Sampling and Quantization General Mismatch-Shaping DAC - Second- Oversampling Order Example First-Order Ó Modulator Multi-Bit Unit Elements First-Order Ó Modulator Decimation and Interpolation First-Order Ó Modulator with SC Circuit Im- Multi-Stage Rate Conversion plementation sinck Filters Circuit Considerations

Second-Order Ó Modulator 27. Phase-Locked Loops Phase-Locked Loops (PLLs) Integration Range in a Second-Order Ó Mod- ulator Basic Model Integration Range in a Second-Order Ó Mod- Second-Order PLL - Active Lag-Lead Filter ulator Second-Order PLL - Passive Lag-Lead Filter Overloading in a Second-Order Ó Modulator High-Gain Second-Order PLL Frequency Re- Oversampling ADCs sponse General Single-Stage Ó Modulator Step Response of a Two-Pole System

General Single-Stage Error-Feedback Coder Phase Jitter

Single-Stage High-Order Modulators Phase Noise

Stability of Single-Stage High-Order Modula- PLL Noise Response tors Phase Detection Using Analog Multiplier Multi-Stage Cascaded Modulators PLL Tracking Performance - Hold-In Range A Third-Order (1-1-1) Cascaded Modulators PLL Tracking Performance - Pull-Out Range Idle Channel Tones (Pattern Noises) Noisy PLL Tracking Performance Noise-Shaped Dithering for Single-Stage PLL Acquisition Behavior Modulators Phase Acquisition of a First-Order Loop Noise-Shaped Dithering for Multi-Stage Cas- caded Modulators Phase Acquisition of a Second-Order Loop

Multi-Bit Ó Modulator Frequency Acquisition - The Pull-In Process

Multi-Bit DAC - Dynamic Element Matching Aided Frequency Acquisition - Frequency Sweeping Multi-Bit DAC - Data-Weighted Averaging Aided Frequency Acquisition - Loop Filter Multi-Bit DAC - Noise-Shaped Scrambler Switching General Mismatch-Shaping DAC Aided Frequency Acquisition - Dual Loops Digital Phase-Locked Loops (DPLLs) XOR Phase Detector Edge-Triggered Set-Reset Phase Detector Sequential Phase-Frequency Detector (PFD) Charge-Pump Phase-Locked Loops PFD and Charge-Pump Filter PFD with Delayed Reset Third-Order Charge-Pump PLLs Multi-Path Charge-Pump Filter Analog Integrated Circuits

Jieh-Tsorng Wu

July 17, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Copyright c 2001 by Jieh-Tsorng Wu

• Unmodiﬁed reproduction of these lecture notes for class or personal use is permitted.

• For commercial use, permission should be obtained from the author.

Contents 0-2 Analog ICs; Jieh-Tsorng Wu Devices and Technologies

1. Introduction

2. PN Junctions and Bipolar Junction Transistors

3. MOS Transistors

4. Integrated Circuit Technologies

Contents 0-3 Analog ICs; Jieh-Tsorng Wu Basic Circuits and Design Techniques

5. Single-Transistor Gain Stages

6. Multiple-Transistor Gain Stages

7. Diﬀerential Gain Stages

8. Current Mirrors and Active Loads

9. Voltage and Current References

10. Output Stages

11. Noise Analysis and Modelling

12. Feedback and Compensation

Contents 0-4 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁers

13. Basic Two-Stage Operational Ampliﬁer Design

14. Operational Ampliﬁers with Single-Ended Outputs

15. Fully Diﬀerential Operational Ampliﬁers

Contents 0-5 Analog ICs; Jieh-Tsorng Wu Analog Functional Blocks

16. Operational Ampliﬁers and Their Basic Conﬁgurations

17. Analog Switches and Sample-and-Hold Circuits

18. Comparators and Oﬀset Cancellation Techniques

19. Oscillators

Contents 0-6 Analog ICs; Jieh-Tsorng Wu Subsystems

20. Fundamentals of Analog Filters

21. Active-RC Filters

22. MOST-C and Gm-C Filters

23. Switched-Capacitor Filters

24. Niquist-Rate Digital-to-Analog Converters

25. Niquist-Rate Analog-to-Digital Converters

26. Oversampling Converters

27. Phase-Locked Loops

Contents 0-7 Analog ICs; Jieh-Tsorng Wu Introduction

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Analog Integrated Circuits Power Source

Transmission Media Physical Sensors & Actuators Wire Pairs Coax Fiber RF VLSI Digital Imagers & Displays System

Audio I/O Storage Media Disk Tape Analog/Digital Interfaces Bubble

• Usually integrated with digital VLSI circuits monolithically (mixed-signal integrated circuits) for better performance and/or lower cost.

Introduction 1-2 Analog ICs; Jieh-Tsorng Wu Analog Signal Processing

Analog Signals

• Always continuous in amplitude.

• Either continuous in time (s-transform) or discrete in time (z-transform).

Analog circuits provide interfaces between the analog environment of the physical world and a digital environment. Major functions are

• Ampliﬁcation.

• Filtering.

• Analog-to-digital conversion.

• Digital-to-analog conversion.

• Power supply conditioning.

Introduction 1-3 Analog ICs; Jieh-Tsorng Wu Design for Analog Circuits

Signal path

• Small (variational) signals related by linear transfer function in the frequency domain.

• Model with linearized small-signal equivalent circuit.

• Analyze using Laplace transforms.

Biasing Circuit

• Establish operating conditions of devices in signal path.

• Concern with sensitivity to variations in temperature, supply voltage, and fabrication process.

• Analyze using large-signal device models.

Introduction 1-4 Analog ICs; Jieh-Tsorng Wu Performance Considerations

• Small-signal response: gain, bandwidth, noises, . . .

• Large-signal response: settling time, distortion, . . .

• Sensitivity to device variation, temperature variation, external noises, . . .

• Cost: power dissipation, chip area, yield.

Introduction 1-5 Analog ICs; Jieh-Tsorng Wu Design Practices

• Make simplifying assumptions that allow hand analysis.

• Keep in mind potential consequences of the assumptions.

• Use simulations to verify the design.

• Good designs are robust; i.e., insensitive to approximations in the modeling as well as variations in temperature and fabrication process.

Introduction 1-6 Analog ICs; Jieh-Tsorng Wu PN Junctions and Bipolar Junction Transistors

Jieh-Tsorng Wu

September 6, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering PN Junctions

N N Built-in potential = Ψ = U ln A D 0 T 2 ni

kT ◦ U = ≈ 26 mV at 300 K T q ≈ × 10 −3 ◦ ni 1.5 10 cm at 300 K for Si Solving Poisson’s equation,   1/2  2(Ψ + V )  = 0 R W1   qN 1 + NA A ND

  1/2  2(Ψ + V )  = 0 R W2   qN 1 + ND D NA

BJT 2-2 Analog ICs; Jieh-Tsorng Wu Small-Signal Junction Capacitance

= = Depletion layer charge is Qj qNAW1A qNDW2A, where A is the cross-sectional area. Depletion-region capacitance

1/2 dQj q N N 1 Cj0 C = = A A D · = j dV 2Ψ N + N R 0 A D 1 + VR 1 + VR Ψ0 Ψ0

BJT 2-3 Analog ICs; Jieh-Tsorng Wu Small-Signal Junction Capacitance

• Cj can be expressed as

= · = + Cj A xd W1 W2 xd

• In general Cj0 1 1 = ≤ ≤ Cj m m V 3 2 1 + R Ψ0 – m = 1/2 for abrupt junction. – m = 1/3 for graded junction.

• In forward bias, diﬀusion capacitance dominates.

BJT 2-4 Analog ICs; Jieh-Tsorng Wu Large-Signal Junction Capacitance

Depletion layer charge can be rewritten as 1−m Cj0 V Q = · Ψ · 1 + R j − 0 1 m Ψ0 Average capacitance is deﬁned as − Qj (V2) Qj (V1) C = j−av − V2 V1 For an abrupt junction, m = 0.5, + V2 − + V1 1 Ψ 1 Ψ C = 2C Ψ · 0 0 j−av j0 0 − V2 V1 • = = = If V1 0V,V2 5V,andΨ0 0.9V 1 C − = 0.56 · C ≈ C j av j0 2 j0

BJT 2-5 Analog ICs; Jieh-Tsorng Wu PN Junction in Forward Bias

I D Small-Signal Model r V D dCT

1 1 = VD/UT − ≈ VD/UT ≈ + ID IS(e 1) ISe IS A NA ND dI I 1 = D = D = + CT Cd Cj rd dVD UT I τ = · D = T = Cd τT τT Transit Time UT rd

• ≈ For moderate forward-bias currents, Cd Cj , rd CT τT .

• = For Schottky diode, Cd 0.

BJT 2-6 Analog ICs; Jieh-Tsorng Wu PN Junction Avalanche Breakdown

• The maximum electric ﬁeld in the depletion region of an abrupt junction is qN W 2qN N (Ψ + V ) 1/2 |E | = A 1 = A D 0 R max + (NA ND) |E | max increases with both VR and doping density.

• |E |→E As max crit, carriers crossing the depletion region acquire enough energy to create new electron-hole pairs when colliding with silicon atoms. The result is avalanche breakdown.

= = 1 IRA MIR M n − VR 1 BV

BV is the breakdown voltage. And typically 3 ≤ n ≤ 6

•E × 5 6 crit is a function of doping density, which can vary from 3 10 V/cm to 10 V/cm as 15 3 18 3 NA (or ND) varying from 10 atoms/cm to 10 atoms/cm .

BJT 2-7 Analog ICs; Jieh-Tsorng Wu PN Junction Breakdown

Zener Breakdown

• In very heavily doped junctions where the electric ﬁeld becomes large enough to strip electrons always from the valence bonds. This process is called tunneling.

• The Zener breakdown mechanism is important only for breakdown voltages below about 6 V.

Punch Through

• A form of breakdown that occurs when the depletion regions of two neighboring junctions meet.

BJT 2-8 Analog ICs; Jieh-Tsorng Wu Bipolar Junction Transistor (BJT)

BJT 2-9 Analog ICs; Jieh-Tsorng Wu Minority Carrier Current in the Base Region

There is a negligible flow of holes between emitter and collector junctions because neither can supply a significant flow of holes into the base. Thus, in the neutral base region,

dp D dp dp = E − b = ⇒E= p 1 b = kT 1 b Jp qµppb(x) (x) qDp 0 (x) dx µp pb dx q pb dx

• = ⇒E = Note that for uniformly doped region dpb/dx 0 (x) 0

For electrons in the base, dn n dp dn qD dp dn J = qµ n (x)E(x) + qD b = kTµ b b + qD b = n n b + p b n n b n dx np dx n dx p b dx b dx b b qD d(n p ) = n b b pb dx

BJT 2-10 Analog ICs; Jieh-Tsorng Wu Minority Carrier Current in the Base Region

Assuming negligible recombination in the base, so that Jn is constant, WB p (x) WB d(n p ) b = b b = − Jn dx dx nb(0)pb(0) nb(WB)pb(WB) 0 qDn 0 dx

From the Boltzman approximation at the edges of the depletion layers,

= 2 VBE/UT = 2 VBC/UT nb(0)pb(0) ni e nb(WB)pb(WB) ni e

Thus 2 qni J = eVBE/UT − eVBC/UT = J eVBE/UT − eVBC/UT n W S B pb dx 0 Dn where qn2 J ≡ i S W B pb dx 0 Dn

BJT 2-11 Analog ICs; Jieh-Tsorng Wu Gummel Number (G)

Dn is a weak function of x. Then, JS can be expressed as

2 2 qn qn Dn J = i = i S W B pb dx G 0 Dn where WB WB ≡ ≈ G pb(x)dx NA(x)dx 0 0

• The Gummel number, G, is simply the dopant concentration per unit cross-sectional area of the base.

• = = For a uniform base region, NA(x) NA, then G WBNA.

BJT 2-12 Analog ICs; Jieh-Tsorng Wu Base Transport Current

The total minority carrier transport current across the base is

2 qni Dn I = J × A = I eVBE/UT − eVBC/UT where I = J × A = × A T N S S S G The transport current can be separated into forward and reverse components as = VBE/UT − − VBC/UT − = + IT IS e 1 IS e 1 ICF IER

• If VBE > 0 and VBC < 0, the device is biased in the forward-active region,

= VBE/UT IT ISe

• If VBE < 0 and VBC > 0, the device is biased in the inverse-active region,

= VBC/UT IT ISe

• If VBE > 0 and VBC > 0, the device is biased in the saturation region.

BJT 2-13 Analog ICs; Jieh-Tsorng Wu Base Current

In the forward-active region = + IB IBB IBE

• IBB is due to the recombination of holes and electrons in the base.

• IBE is due to the injection of holes from the base into the emitter.

Deﬁne Qe as the minority carrier charge in the base region

2 WB 1 1 ni = = = VBE/UT Qe qA nb(x)dx or Qe qAWBnb(0) qAWB e 0 2 2 NA

IBB is related to Qe by the lifetime of minority carriers in the base, τb

2 Qe 1qAWB ni = = · VBE/UT IBB e τb 2 τb NA

BJT 2-14 Analog ICs; Jieh-Tsorng Wu Base Current

IBE depends on the gradient of minority carriers (holes) in the emitter.

• For a “long-base” emitter (all minority carriers recombine in the quasi-neutral region) ﬀ with a di usion length Lp

2 qADp qADp ni = VBE/UT = VBE/UT = IBE peoe e ND Emitter Doner Density Lp Lp ND

• For a “short-base” emitter (all recombination at the contact) with emitter width WE , WE simply replaces Lp in the expression for IBE .

The total base current in the forward-active region is 2 2 1qAWB ni qADp ni = + VBE/UT IB e 2 τB NA Lp ND

• In modern narrow-base transistors IBE IBB.

BJT 2-15 Analog ICs; Jieh-Tsorng Wu Forward Current Gain

In the forward-active region, the forward current gain is

I ≡ C = 1 βF I W 2 D B B + p WB NA 2τbDn Dn LP ND The emitter current is I I = − + = − + C = − C IE (IC IB) IC βF αF where I β ≡−C = F = 1 = 1 ≈ · αF αT γ + 1 W 2 IE βF 1 1 + B Dp WB NA βF 1 + + 2τbDn Dn LP ND = 1 = 1 αT γ W 2 Dp W N B + B A 1 + 1 D L N 2τBDn n P D • ﬃ αT is called the base transport factor, and γ is called the emitter injection e ciency.

BJT 2-16 Analog ICs; Jieh-Tsorng Wu BJT DC Large-Signal Model in Forward-Active Region

I B I C I B I C B C BC

VBE VBE(on)

I E I E E E

IS = VBE/UT = IB e IC βF IB βF

• The voltage on the emitter junction can be approximated by a constant VBE(on).

• ﬃ − ◦ VBE(on) is usually 0.6 V to 0.8 V, and has a temperature coe cient of 2mV/ C.

BJT 2-17 Analog ICs; Jieh-Tsorng Wu Dependence of βF on Operating Condition

• At high currents, due to high-level injection

→ VBE/(2UT ) IC ISe

• At low currents, due to recombination in the B-E depletion region

→ VBE/(2UT ) IB ISe

BJT 2-18 Analog ICs; Jieh-Tsorng Wu Collector Voltage Eﬀects

In the forward-active region, an increase ∆VCE in VCE results in an increase in the collector depletion layer width, thereby reducing WB by ∆WB, and increasing IC.

2 qni Dn I = I eVBE/UT = A eVBE/UT G = Gummel number C S G

2 ∂IC qni Dn dG IC dG = −A eVBE/UT · = − · 2 ∂VCE G dVCE G dVCE

BJT 2-19 Analog ICs; Jieh-Tsorng Wu Collector Voltage Eﬀects

For a uniform-base transistor ∂I I dW = C = − C · B G WBNA and ∂VCE WB dVCE

• dWB/dVCE is typically a weak function of VCE for a reverse biased collector junction and is often assumed to be constant.

The Early voltage, VA, is given by I = C = − 1 VA WB ∂IC/∂VCE dWB/dVCE

The inﬂuence of changes in VCE on IC can thus be represented as VCE = VBE/UT + IC ISe 1 VA • Typical values of VA are 15–100 V.

BJT 2-20 Analog ICs; Jieh-Tsorng Wu Base Transport Model

IS/βR IC

B IT

I IS/βF E

E = VBE/UT − VBC/UT IT IS e e IS IS I = I − eVBC/UT − 1 I = −I − eVBE/UT − 1 C T β E T β R F IS IS = VBE/UT − + VBC/UT − IB e 1 e 1 βF βR

BJT 2-21 Analog ICs; Jieh-Tsorng Wu Ebers-Moll Model

Recalling = VBE/UT − VBC/UT IT IS e e IS IS = − VBC/UT − = − − VBE/UT − IC IT e 1 IE IT e 1 βR βF SPICE uses the base transport model with the equations rewritten as: 1 IS = VBE/UT − − + VBC/UT − = VBE/UT − − VBC/UT − IC IS e 1 IS 1 e 1 IS e 1 e 1 βR αR 1 IS = − + VBE/UT − − VBC/UT − = − VBE/UT − − VBC/UT − IE IS 1 e 1 IS e 1 e 1 IS e 1 βF αF

• Note that, in the classical Ebers-Moll model, parameters IES and ICS are deﬁned such that = = αF IES αRICS IS

BJT 2-22 Analog ICs; Jieh-Tsorng Wu Leakage Current

In the forward-active region, eVBE/UT 1 and eVBC/UT 1, then

IS IS ≈ VBE/UT + ≈− VBE/UT − IC ISe IE e IS αR αF thus VBE/UT = − − ISe αF IE αF IS and = − + 1 − = − + IC αF IE αF IS αF IE ICO αR where I ≡ − S ICO (1 αF αR) αR

• ICO is the collector-base leakage current with the emitter open.

• ﬀ In practice, because of surface leakage e ects, ICO is several orders of magnitude larger than the value predicted by the above deﬁnition.

BJT 2-23 Analog ICs; Jieh-Tsorng Wu Common-Base Transistor Breakdown

• Avalanche multiplication at the junctions of a BJT limits the voltage that can be sustained.

• BVCBO is the breakdown voltage of C-B = junction with IE 0.

BVEBO is much less than BVCBO.

Neglecting leakage currents

1 = − = IC αF IE M where M n 1 − VCB BVCBO

BJT 2-24 Analog ICs; Jieh-Tsorng Wu Common-Emitter Transistor Breakdown

VCE

BJT 2-25 Analog ICs; Jieh-Tsorng Wu Common-Emitter Transistor Breakdown

In this configuration, holes generated in the avalanche process are swept into the base where they act as a supply of base current. The avalanche current is thus effectively amplified by βF . I Mα I = −(I + I ) = −I + C ⇒ I = F I B C E C C − B MαF 1 MαF where M is as defined above for the common-base case. →∞ → BVCEO is defined as the value of VCE for which IC ; that is, for which MαF 1. ≈ Assume VCB VCE, then

α BV = F = ⇒ CEO = − 1/n = 1 ≈ 1 Mα 1 (1 αF ) BV n BV + 1/n 1/n 1 − CEO CBO (βF 1) β BVCBO F

• Note: Here must use value of BVCBO for intrinsic transistor. Actual BVCBO is lower than this because of sidewall eﬀects.

BJT 2-26 Analog ICs; Jieh-Tsorng Wu Small-Signal Model of Forward-Biased BJT

rµ Ic

Ib Cµ

VCC BC V be vπ rπ Cπ gmvπ ro

In the forward-active region VCE IC = VBE/UT + = IC ISe 1 IB VA βF

Bias and small-signal variables are:

= + = + = + Ib IB ib Ic IC ic Vbe VBE vbe

BJT 2-27 Analog ICs; Jieh-Tsorng Wu Small-Signal Model of Forward-Biased BJT

• = If βF is constant, then βo βF .

UT ∂I qI I • η ≡ . = C = C = C VA gm ∂VBE kT UT − • If I = I ∂I I 1 B BB = C = ∂ C βo ∂IB ∂IC βF ∂I ∂I g g ≈ B C = o or r = β r ∂I 1 1 ∂I g µ µ o o = B = = C = m ∂IC ∂VCE βo gπ ∂VBE rπ βo ∂VBE βo

∂IC IC • g = = = ηg Typically, rµ > 10βoro. o ∂V V m ∼ CE A For lateral pnp, rµ is 2βoro 5βoro. ∂I ∂I ∂I = BB = BB C = 1 gµ • ∂VCB ∂IC ∂VCB rµ Junction capacitances are = + = + Cπ Cb Cje τF gm Cje Cj0 = = = ∼ Cµ Cjc Cj n n 0.2 0.5 1 − V Ψ0

BJT 2-28 Analog ICs; Jieh-Tsorng Wu Charge Storage

In the intrinsic transistor charge is stored in the junction capacitances, Cje and Cjc, and as minority carriers in the base (Qe) and emitter (Qp).

• VBE/UT Both Qe and Qp are proportional to e .

• ﬀ Qe Qp and typically the e ect of Qp is taken into account simply by modifying Qe.

An equivalent forward base transit time, τF , is deﬁned as

Q W 2 ≡ e = B τF τF for uniform-base transistor IC 2Dn

The diﬀusion capacitance is

∂Q ∂I = e = C = Cb τF τF gm ∂VBE ∂VBE

BJT 2-29 Analog ICs; Jieh-Tsorng Wu Complete Small-Signal Model with Extrinsic Components

rµ

r C r b B’ µ c BC

vπ rπ Cπ ro Ccs gmvπ

rex

BJT 2-30 Analog ICs; Jieh-Tsorng Wu Typical values of Extrinsic Components

Ω rb 50–500 Ω rc 20–500 Ω rex 1–8 Ccs 0.2–3 pF

The value of rb varies signiﬁcantly with IC because of current crowding.

BJT 2-31 Analog ICs; Jieh-Tsorng Wu MOS Field-Eﬀect Transistors

Jieh-Tsorng Wu

October 8, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering MOS Transistors

D Drain V D I D nMOST Gate Body G V G V B Source S V S

Source S V S

pMOST Gate Body G V G V B I D Drain V D D

MOST 3-2 Analog ICs; Jieh-Tsorng Wu MOS Transistors

• = − = Lelectrical Lgate 2LD. In SPICE, L Lgate.

• For nMOST, VD >VS >VB.

• For pMOST, VD

• The I − V equations of nMOST are identical to those of pMOST.

• For enhancement-mode device, Vtn > 0 and Vtp < 0.

MOST 3-3 Analog ICs; Jieh-Tsorng Wu Strong Inversion

V S V G V D

n+ n+ V(y)

Depletion y Region 0 L NSUB p- Substrate

V B

The threshold voltage of VGB for strong inversion is = + + + + Vt(y) V (y) 2φf γ V (y) 2φf VFB

N 2q N = kT SUB = si SUB = ox 2φf 2 ln γ Cox q ni Cox tox

MOST 3-4 Analog ICs; Jieh-Tsorng Wu Channel Charge Transfer Characteristics

The induced channel charge per unit area is = − QI(y) Cox VGB Vt(y) when VGB >Vt(y)

The current along the channel is

dV I = W · µQ (y) ·E(y) = W · µQ (y) · ⇒ I dy = WµQ(y)dV D I I dy D I

Integration along the channel from 0 to L gives L VDB = − IDdy WµCox VGB Vt(y) dV 0 VSB VDB W 1 2 2 3/2 I = µC (V − 2φ − V )V (y) − V (y) − γ[V (y) + 2φ ] D ox L GB f FB 2 3 f VSB

MOST 3-5 Analog ICs; Jieh-Tsorng Wu Simpliﬁed Channel Charge Transfer Characteristics

The threshold voltage of VGS for strong inversion is simplﬁed as

+ = + + ⇒ = + Vt (y) VSB V (y) VSB Vt(SB) Vt (y) V (y) Vt

The channel charge becomes = − − QI(y) Cox VGS V (y) Vt

And the drain current is W 1 W 1 I = µC (V − V )V − V 2 = k (V − V )V − V 2 D ox L GS t DS 2 DS L GS t DS 2 DS

• Vt is the threshold voltage of VGS for strong inversion, and depends on VSB.

• = k µCox is called the process transconductance.

MOST 3-6 Analog ICs; Jieh-Tsorng Wu MOST I-V Characteristics ID IDSAT = VDS VDSAT V = 0 V > 0 Triode Saturation (Active) SB SB Region Region

VDS VGS Vt0 Vt W 1 I = µC (V − V )V − V 2 for V ≤ V = V − V D ox L GS t DS 2 DS DS DSAT GS t 1 W I = I @ V = V = µC (V − V )2 DSAT D DS DSAT 2 ox L GS t

MOST 3-7 Analog ICs; Jieh-Tsorng Wu Threshold Voltage = + + − Vt Vt0 γ VSB 2φf 2φf for VSB > 0 = Vt0 is the threshold voltage when VSB 0. N 2q N = + + = kT SUB = si SUB = ox Vt0 2φf γ 2φf VFB φf ln γ Cox q ni Cox tox

The Fermi level φf is temperature dependent, i.e., dφ 1 Eg0 ◦ f = − − φ E = Silicon band gap at T = 0 K dT T 2q f g0

ﬃ The Vt0’s temperature coe cient is dV 1 Eg0 γ t0 = − − φ 2 + dT T 2q f 2φf

• − ◦ − ◦ dVt0/dT is usually in the range between 0.5 mV/ Cto 4 mV/ C.

MOST 3-8 Analog ICs; Jieh-Tsorng Wu Square-Law I-V Characteristics

In triode region, 1st-order long-channel model is W 1 W 1 I = µC (V − V )V − V 2 = k (V − V )V − V 2 D ox L GS t DS 2 DS L GS t DS 2 DS

≥ = − ﬀ When VDS VDSAT VGS Vt, the MOST is in the pinch-o region (or saturation region),

1 W 1 W I = I = I (V = V − V ) = µC (V − V )2 = k V 2 DS DSAT D DS GS t 2 ox L GS t 2 L ov

• = k µCox is called the process transconductance parameter.

• = = W k β µCox L is called the device transconductance parameter.

• = − Vov VGS Vt is called the gate drive or the overdrive.

MOST 3-9 Analog ICs; Jieh-Tsorng Wu Channel-Length Modulation

ID G

S D IDSAT go

Leff

L VDS VDSAT

= 1 W 2 = − = − ID(sat) k Vov Lef f L ∆∆VDS VDS VDSAT 2 Lef f Using one-dimensional abrupt PN junction model, 2 ≈ si − + ∆ VDS VDSAT Ψo qNSUB

MOST 3-10 Analog ICs; Jieh-Tsorng Wu Channel-Length Modulation

The ID variation due to VDS can be written as: ∂I ∂I ∂L I 1 2 1 D = D × ef f = − D ×− si = I · λ ∂V ∂L ∂V L 2 qN − + D DS ef f DS ef f SUB VDS VDSAT Ψo

The drain current in the pinch-oﬀ region can be approximated as V = 1 W 2 + = 1 W 2 + DS ID(sat) k Vov (1 λVDS) k Vov 1 2 L 2 L VA

• λ is inversely proportional to L, i.e., λ ∝ 1/L.

− − • Typical values of λ are in the range 0.05 V 1 to 0.005 V 1.

• The accurate calculation of λ from the device structure is quite diﬃcult. Extraction from experimental data is usually necessary.

MOST 3-11 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Model in Saturation Region

D v G B gs g g m vgs g mb vsb o S

v sb

∂I I = ≡ D = W + = W + = D Transconductance gm k Vov (1 λVDS) 2k ID(1 λVDS) ∂VGS L L Vov /2 ∂I = ≡ D = Output Conductance go λID ∂VDS

MOST 3-12 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Model in Saturation Region

∂I ∂I ∂V γ Body Transconductance = g ≡− D = − D × t = g × mb ∂V ∂V ∂V m + SB t SB 2 VSB 2φf Thus γ g = g × χ where χ ≡ mb m + 2 VSB 2φf

• The factor χ is typically 0.1Ð0.3. • = Since γ 2qsiNSUB/Cox   2 (V + 2φ ) /x C =  si SB f  1 = si dmax = depl χ si/ qNSUB Cox Cox Cox

xdmax: The width of depletion layer under channel. Cdepl: The capacitance/area of depletion layer under channel.

MOST 3-13 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Capacitances in Saturation Region

W Gate Source Drain

C C C ovs ch ovd

C cb Body

C C sb db L L D L D

= × + × = × + × Csb AS CJ (VSB) PS CJSW (VSB) Cdb AD CJ (VDB) PD CJSW (VDB)

= + ≈ × Csb Csb Ccb Ccb WL CJ (VSB)

• AS and AD are the areas of the source/drain junctions.

• PS and PDare the source/drain perimeters excluding the sides adjacent to channel.

MOST 3-14 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Capacitances in Saturation Region

Junction Capacitances:

C C 1 1 = sbo = dbo = ∼ Csb m Cdb m m V V 3 2 1 + SB 1 + DB Ψo Ψo

Overlap Capacitances:

= × = × = × = × Covs W CGSO W (nLDCox) Covd W CGDO W (nLDCox)

1 ≤ n ≤ 2 (Due to friniging)

MOST 3-15 Analog ICs; Jieh-Tsorng Wu Channel Capacitance in Saturation Region

L = − − = − QI(y) Cox[VGS Vt V (y)] Cox[Vov V (y)] G = · ·E = · · dV ID W µQI(y) (y) W µQI(y) S D dy V(y) = 1 W 2 ID µCox Vov y 2 L

I Let V = 0 and D · dy = (V − V ) − V (y) · dV S µC W GS t ox 1 y 1 y Integration from 0 to y ⇒ V 2 = V V − V 2(y) ⇒ V (y) = V 1 − 1 − 2 ov L ov 2 ov L L = = = 2 = 2 − Total Channel Charge QT QI(y)Wdy WLCoxVov WLCox(VGS Vt) 0 3 3 ∂Q = ≡ T = 2 Channel Capacitance Cch WLCox ∂VGS 3

MOST 3-16 Analog ICs; Jieh-Tsorng Wu Complete MOST Small-Signal Model in Saturation Region

C G gd D

C C v g v g v g C gb gsgs m gs mb sb o db

C’ v sb sb

2 C = C C = C + WLC gd ovd gs ovs 3 ox = + = + · × + × Csb Csb Ccb (AS W L) CJ (VSB) PS CJSW (VSB)

MOST 3-17 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Model in Triode Region

C C gs g ds gd S D

C’ C’ sb db

B ∂I = D = W − → gds µCox (VGS Vt)forVDS 0 ∂VDS L 1 1 C = C + WLC C = C + WLC gs ovs 2 ox gd ovd 2 ox 1 1 C = C + WLC (V ) C = C + WLC (V ) sb sb 2 J SB db db 2 J DB

MOST 3-18 Analog ICs; Jieh-Tsorng Wu MOST Small-Signal Model in Cutoﬀ Region

C C gs gd C gb S D

C C sb db

= = Cgs Covs Cgd Covd

• Cgb is highly nonlinear and dependent on the gate voltage.

MOST 3-19 Analog ICs; Jieh-Tsorng Wu Carrier Velocity Saturation

= W vd gm gm k L Vov

vscl gm(max)

E Vov E c ≈E Vov cL µE v = Carrier Drift velocity = E ≈ 1.5 × 106 V/m d + E E c 1 / c

• µ is the low-ﬁeld mobility.

In the triode region µC = · ⇒ = ox · W − − 1 2 ID WQI(y) vd ID (VGS Vt)VDS VDS + 1 VDS L 2 1 E c L

MOST 3-20 Analog ICs; Jieh-Tsorng Wu Carrier Velocity Saturation

= Using ∂ID/∂VDS 0 to ﬁnd VDSAT ,wehave   2V V V = E L  1 + ov − 1 = V 1 − ov + ··· DSAT c E ov E cL 2 cL

And the saturation current is 1 W 1 W V 2 I = µC V 2 = µC V 2 1 − ov + ··· DSAT ox DSAT ox ov E 2 L 2 L 2 cL

The transconductance is + 2Vov − 1 E L 1 g = E c m = 2 gm WµCox c or 2V I + ov D E + 2Vov + 2Vov − 1 E L L 1 E 1 E 1 c c cL cL

MOST 3-21 Analog ICs; Jieh-Tsorng Wu Eﬀects of Carrier Velocity Saturation

• E If Vov cL,

µC V g ≈ 1 ox W 2 ≈ W ov m ≈ 2 IDSAT Vov gm µCox 2 + Vov L L + Vov I V 1 E 1 E D ov cL cL

= 1 1 1 Ð The mobility degradation can be modeled by a resistor R E in series SX c µCox W with the source of an ideal square-law device. ﬀ E Ð Velocity-saturation e ects are insigniﬁcant in hand calculations if Vov < 0.1 cL.

• E If Vov cL,

g ≈ E = ≈ m ≈ 1 IDSAT µCoxWVov c WCoxVov vscl gm WCoxvscl ID Vov

= E Ð vscl µ c is the scattering-limited velocity. Ð IDSAT is a linear function of Vov , and independent of L.

MOST 3-22 Analog ICs; Jieh-Tsorng Wu Hot Carriers

− − = − K2/(VDS VDSAT ) IDB K1(VDS VDSAT )IDe ∂I I K K I g ≡ DB = DB 2 + 1 ≈ 2 DB db − − − 2 ∂VD VD VDSAT VDS VDSAT (VDS VDSAT )

• ∼ −1 = K1 5V and K2 30 V are process-dependent parameters.

MOST 3-23 Analog ICs; Jieh-Tsorng Wu Short-Channel Eﬀects

• Hot Carriers. Ð The drain-to-substrate current can be modeled by a ﬁnite drain-to-substrate resistor.

Ð The punch-through current is an additional cause of lower ro and possibly transistor breakdown. Ð Some charges in the gate current can be trapped in the gate oxide, causing a shift

in Vt. Ð The host-carrier eﬀects are more pronounced for nMOST than for pMOST, because electrons have larger velocities than holes.

• Drain-Induced Barrier Lowering (DIBL) ﬀ Ð For short-channel devices, DIBL e ectively lowers Vt as VDS is increased, thereby further lowering the ro.

• Carrier Velocity Saturation.

MOST 3-24 Analog ICs; Jieh-Tsorng Wu Subthreshold Conduction in MOST

g m / I D

1 Weak Inv. Asymptote n UT Strong Inv. Asymptote

Moderate 0 I D / ( I t W/L) 0.01 0.1 1 10 100 Weak Strong

In the weak inversion region

+ W − Cox Cdepl = Vov /(nUT ) − VDS/UT = = + ≈ ID It e 1 e n 1 χ 1.5 L Cox

• ∝ It Dnnpo depends on process parameters (e.g., 20 nA).

MOST 3-25 Analog ICs; Jieh-Tsorng Wu Subthreshold Conduction in MOST

| | When VDS > 3UT , ID saturates and

∂I I I C g 1 1 C g ≡ D = D = D ox m = = ox m + + ∂VGS nUT UT Cox Cdepl ID nUT UT Cox Cdepl

To ﬁnd Vov for strong inversion, let

g m = 1 = 2 ⇒ = ≈ Vov 2nUT 78 mV ID nUT Vov

• → 2nUT

• In weak inversion, Cgs Cgd 0, and

= × = × + Cgb WL (Cox Cdepl) WL CoxCdepl/(Cox Cdepl)

MOST 3-26 Analog ICs; Jieh-Tsorng Wu Integrated Circuit Technologies

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Integrated-Circuit NPN Transistor

Emitter Diffusion 0.5–2.5 µm, 2–10 Ω/ Base Diffusion 1–3 µm, 100–300 Ω/ Isolation Diffusion 20–40 Ω/ = Epitaxial layer 17 µm(BVCEO 36 V) 1015 atoms/cm3,5Ω-cm Buried layer 20–50 Ω/ P-Substrate 250 µm 1016 atoms/cm3 1–2 Ω-cm

• Junction isolation.

Technologies 4-2 Analog ICs; Jieh-Tsorng Wu Lateral PNP Transistor

• Lightly doped base.

• Slow.

• ↑ Low current gain, especially as IC .

Technologies 4-3 Analog ICs; Jieh-Tsorng Wu Vertical PNP Transistors

• Low base resistance.

• Low emitter-base breakdown voltage.

• Substrate collector (no buried layer).

Technologies 4-4 Analog ICs; Jieh-Tsorng Wu Advanced-Technology NPN Transistor

Emitter 0.1 µm Base 0.1 µm Epitaxial layer 1 µm, 0.5 Ω-cm Buried layer 20–50 Ω/ P-Substrate 250 µm 1016 atoms/cm3 1–2 Ω-cm

• Oxide isolation.

• Polysilicon emitter self-aligned structure.

• High fT (> 10 GHz).

Technologies 4-5 Analog ICs; Jieh-Tsorng Wu Base and Emitter Diﬀused Resistors

Technologies 4-6 Analog ICs; Jieh-Tsorng Wu Base Pinch Resistor

Technologies 4-7 Analog ICs; Jieh-Tsorng Wu Epitaxial Resistor

Technologies 4-8 Analog ICs; Jieh-Tsorng Wu Properties of IC Resistor

Technologies 4-9 Analog ICs; Jieh-Tsorng Wu Capacitors

• PN junctions.

• Metal or poly over thin oxide.

Technologies 4-10 Analog ICs; Jieh-Tsorng Wu Diodes

(a) (b) (c) (d)

• Implementation (a) is usually preferred to avoid forward biasing the C-B junction.

• C-B forward bias injects carriers into the epi, which in turn can be collected in the substrate.

Technologies 4-11 Analog ICs; Jieh-Tsorng Wu CMOS Integrated-Circuit Technologies

0.5 µm CMOS M2 1.20 µm M1 0.60 µm Poly 0.25 µm Field Oxide 0.30 µm Gate Oxide 130 Å n+ Depth 0.20 µm p+ Depth 0.25 µm N-well Depth 2.50 µm

• Additional polysilicon layer may exist to realize poly-to-poly capacitors.

• There are twin-tub processes that have separate and optimized wells for nMOSTs as well as pMOSTs.

• Additional processing steps may be used to fabricate vertical bipolar transistors on the same chip. This is called a BiCMOS technology.

Technologies 4-12 Analog ICs; Jieh-Tsorng Wu MOS Transistors

• ﬀ May have devices with di erent Vt.

• Source/drain can be shared between two series-connected MOSTs of the same type.

• Wide devices usually employ stacked layout.

Technologies 4-13 Analog ICs; Jieh-Tsorng Wu Parasitic BJTs in CMOS Technologies

Vertical PNP Transistor Lateral PNP Transistor

E BC E VDD C1 B C2

p+ n+ p+ p+ p+ n+ p+

N-Well N-Well

P-Substrate P-Substrate C2 VSS C1 VSS

• The collector is usually in ring form surrounding the emitter.

• In the lateral devices, the MOST’s L is the base width.

• The ratio of IC2/IC1 is poorly controlled in practice.

Technologies 4-14 Analog ICs; Jieh-Tsorng Wu Resistors in CMOS Technologies

• n+ and p+ diﬀusion Polysilicon Resistor – 10–30 Ω/

• Polysilicon – 20–80 Ω/

• N (or P) well diﬀusion – 1k–10k Ω/

• Large R variation due to process variation. • MOSTs in the triode region

– Depends on Vov and W/L • Matching properties is ∼1%.

• Small voltage coeﬃcient.

• No parasitic pn junction.

Technologies 4-15 Analog ICs; Jieh-Tsorng Wu Capacitors in CMOS Technologies

• Poly-Poly Poly-Poly Capacitor

• Poly-Metal

• Metal-Metal (MIM)

• Multi-Layer Sandwich.

• Lateral structures.

• • MOSTs in triode region Bottom-plate Cparasitic is 10%–30% of C itself.

• MOS in accumulation • Matching properties is 0.1%–1%. – Large voltage coefficient. • Voltage coefficient is < 50 ppm/V. – Large R in one terminal. ◦ • Temperature coefficient is < 50 ppm/ C.

Technologies 4-16 Analog ICs; Jieh-Tsorng Wu Matching Issues

Mismatches between two supposedly identical devices are due to

• Localized geometric variation. – Resulting from the limited resolution of the photolithographic process itself

• Global material gradient variation. – Variations across wafer resulting from nonuniform conditions during the fabrication processes.

• Temperature gradient variation.

Technologies 4-17 Analog ICs; Jieh-Tsorng Wu Guidelines for Better Device Matching

Device Considerations:

• Match devices of equal nature. – e.g., no JFET-MOST pair or poly-diﬀusion resistor pair.

• Devices to be matched should operate on the same temperature.

• Input oﬀset voltage for a BJT pair is only ∼1/10 that for a MOST pair.

• May consider post-fabrication trimming.

Technologies 4-18 Analog ICs; Jieh-Tsorng Wu Guidelines for Better Device Matching

Local Matching Consideration:

• Increase device size.

• Round devices matches better than square devices.

• Whenever possible, utilize series and/or parallel combination of unit-sized devices to form devices of diﬀerent sizes.

• Use dummy devices to protect matching devices from diﬀerent etch eﬀects.

Technologies 4-19 Analog ICs; Jieh-Tsorng Wu Guidelines for Better Device Matching

Global Matching Consideration:

• Layout devices with the same orientation.

• Decrease device separation distance.

• Try a common-centroid layout for the devices to be matched.

1 1 M1 M2 2 2

1 1 M2 M1 2 2

Technologies 4-20 Analog ICs; Jieh-Tsorng Wu Transistor Pair Layout Example

Technologies 4-21 Analog ICs; Jieh-Tsorng Wu Resistor Pair Layout Example

Technologies 4-22 Analog ICs; Jieh-Tsorng Wu Capacitor Pair Layout Example

Technologies 4-23 Analog ICs; Jieh-Tsorng Wu Capacitor Errors

e y

Assume a rectangular capacitor with dimension x and y. Then

= · · Cideal Cox x y

Due to lithography modiﬁcation ∆e,wehave

= · − · − ≈ · − Ctrue Cox (x 2∆e) (y 2∆e) Cideal (1 r)

x + y Perimeter = 2∆e × = ∆e × r xy Area

Technologies 4-24 Analog ICs; Jieh-Tsorng Wu Capacitor Layout Design

To minimize capacitor ratio error, want

• Capacitors of identical values should have the same shape.

• Capacitors of diﬀerent values should have the same perimeter-to-area ratio.

Let unit-size capacitor Cu have a square layout with xu on each side. Want to realize a new capacitor C with dimension x and y so that

C 1Perimeter 2x x + y = K and = u = C 2 Area 2 x · y u xu We have

2 x · y x + y Kx = = K ⇒ y = x K ± K 2 − K x = u 2 2x u y xu u

• K is usually between 1 and 2.

Technologies 4-25 Analog ICs; Jieh-Tsorng Wu Analog Section Floor Plan Example

Technologies 4-26 Analog ICs; Jieh-Tsorng Wu Noise-Coupling Layout Considerations

• Want to minimize noise from digital circuits coupling into the substrate or analog power supplies.

• Separate power lines for analog and digital circuits.

• Diﬀerent region for analog and digital circuitry, separated by guard rings and wells connected to the power supplies.

• Use metals and wells as shield to protect sensitive nodes. The shields must be connected to clean supply voltages.

• Whenever possible, bypass the power supplies with junction capacitors and/or MOSTs.

Technologies 4-27 Analog ICs; Jieh-Tsorng Wu Latch-Up in CMOS Technologies

VDD

Rn Q2

• Keep Rp and Rn small by having low-impedance paths between the substrate and well to the power supplies.

• Avoid currents ﬂowing in substrate and wells.

• Transistors that conduct large current must be surrounded by guard rings.

Technologies 4-28 Analog ICs; Jieh-Tsorng Wu Single-Transistor Gain Stages

Jieh-Tsorng Wu

October 25, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Unilateral Two-Port Network

Thevenin Output Model Norton Output Model i1 Zo i2 i1 i2 v11Zi Avvvv2 v1 Zi Gm 1 Zo v2

v v = 1 = 2 Zi Zo i i = 1 2 v1 0 v i = 2 = 2 = × Av Gm Av Gm Zo v = v = 1 i2 0 1 v2 0

Single-T Gain Stages 5-2 Analog ICs; Jieh-Tsorng Wu Common-Emitter Conﬁguration

VCC

RL R I + S B VO vo Q1

• DC voltage VI establishes bias of Q1 so that it is on the forward-active region. Typically ≈ want VO VCC/2.

Single-T Gain Stages 5-3 Analog ICs; Jieh-Tsorng Wu Common-Emitter Conﬁguration — Bias Analysis

RS IB IC RL

VI VBE VCC

= VBE/UT = IC ISe βF IB

If Q1 is in the forward-active region, voltage across the emitter junction can be approximated by a constant VBE(on).

V − V R = I BE(on) = − = − = − L − IB VO VCC ICRL VCC βF IBRL VCC βF VI VBE(on) RS RS

• Dependence on βF is a problem with this direct approach to biasing.

Single-T Gain Stages 5-4 Analog ICs; Jieh-Tsorng Wu Common-Emitter Conﬁguration — Small-Signal Analysis

RS rb io ii R L v vi v1 rπ gmv1 ro o

v r ≡ o = − π · · ≡ + A (0) g (r R ) where R R r v v R + r m o L S S b i ω=0 S π v v ≡ i = + ≡ o = = Ri RS rπ Ro ro RL RL i i = i o vi 0

• → →∞ Note that for RS 0 and RL V →− = −1 = − A Av (0) gmro η UT

Single-T Gain Stages 5-5 Analog ICs; Jieh-Tsorng Wu Common-Source Ampliﬁer

VDD

Z L

R v + V S o O M1 v in + V IN -

1 W V = V − I · R = V − µ C (V − V )2 · R o DD d L DD 2 n ox L i tn L

• DC voltage VI is chosen to bias M1 so that M1 is in active (saturation) region and its ≈ drain voltage is near the midpoint of the output swing (VO VDD/2).

Single-T Gain Stages 5-6 Analog ICs; Jieh-Tsorng Wu Common-Source Conﬁguration — Small-Signal Analysis

R ii S io

v v r v in gs o o

g v gs R m L

= − = − = ∞ = = Av (0) gm(ro RL) gmRL Ri Ro ro RL RL

• →∞ → Note that for RL , RL ro, and

− − I L ∂L 1 2L ∂L 1 | | = = D × ef f ef f = ef f ef f Av (0) max gmro Vov /2 ID ∂VDS Vov ∂VDS

Single-T Gain Stages 5-7 Analog ICs; Jieh-Tsorng Wu Common-Emitter Conﬁguration Small-Signal AC Analysis

RS rb Cµ io ii RL v vi v1 rπ Cπ gmv1 ro o

R C i1 1 if f io

⇒ v v 1 C v s 1 o

g v R C m 1 22 (R + r ) r v = v × S b π R = (R + r ) r R = r R s i + 1 S b π 2 o L RS rb = = + = C1 Cπ C2 CL Ccs Cf Cµ

Single-T Gain Stages 5-8 Analog ICs; Jieh-Tsorng Wu Common-Source Conﬁguration Small-Signal AC Analysis

R C S gd

v v gs C r v in gs o o

g v R C m gs L L R C i1 1 if f io

⇒ v v 1 C v s 1 o

g v R C m 1 22

= = = = = = vs vi R1 RS R2 ro RL C1 Cgs C2 CL Cf Cgd

Single-T Gain Stages 5-9 Analog ICs; Jieh-Tsorng Wu Miller Approximation

R C i1 1 if f io

v v 1 C v s 1 o

g v R C m 1 22 = − + 1 = − vo ( gmv1 if ) R2 if (v1 vo)sCf sC2

If R2-C2 is a non-dominant pole, then, at the frequencies of interest

i ≈− ≈ + ⇒ f = + = vo gmR2v1 if (v1 gmR2v1)sCf s(1 gmR2)Cf sCM vi

= + · = + · = CM (1 gmR2) Cf (1 av0) Cf Miller Capacitance

Single-T Gain Stages 5-10 Analog ICs; Jieh-Tsorng Wu Miller Approximation Equivalent Circuit

R i1 1 io

v v 1 C v s t o

g v R C m 1 22

= + = + + Ct C1 CM C1 (1 gmR2)Cf

v 1 A (s) = o = A (0) v v v − − s (1 s/p1)(1 s/p2) = − = 1 = 1 Av (0) gmR2 p1 p2 R1Ct R2C2

Single-T Gain Stages 5-11 Analog ICs; Jieh-Tsorng Wu Short-Circuit Current Gain

C if f io

v ii 1 C 1

R1s g v m 1 R i ≈−g × v = −g × i 1s o m 1 m 1 + + 1 R1s(C1 Cf )s i g R β Short-Circuit Current Gain = β(s) = − o = m 1s = 0 + + + + ii 1 R1s(C1 Cf )s 1 R1s(C1 Cf )s g Transition Frequency = ω ≈ m T + C1 Cf 1 1 g ω −3 dB Frequency = ω = = m = T β + + R1s(C1 Cf ) β0 C1 Cf β0

Single-T Gain Stages 5-12 Analog ICs; Jieh-Tsorng Wu BJT Transition Frequency

For BJTs, we have = = = R1s rπ C1 Cπ Cf Cµ g ω = 2πf = m T T + Cπ Cµ C C C C C C C = 1 = π + µ = b + je + jc = + je + jc τT τF ωT gm gm gm gm gm gm gm

Single-T Gain Stages 5-13 Analog ICs; Jieh-Tsorng Wu MOST Transition Frequency

For MOSTs, we have

2 R = ∞ C = C = C WL C = C 1s 1 gs 3 ox f gd g ω = 2πf = m T T + Cgs Cgd ≈ To calculate intrinsic device speed, let ωT gm/Cgs.

• For square-law device,

W 3 µ g = µC V ⇒ ω = · · V m ox L ov T 2 L2 ov

• For device with carrier velocity saturation,

3 v g = WC v ⇒ ω = · scl m ox scl T 2 L

Single-T Gain Stages 5-14 Analog ICs; Jieh-Tsorng Wu MOST Transition Frequency — Weak Inversion

For MOSTs in the weak inversion region,

g I C CoxCdepl ω = m g = D ox C = WL× T m + gb + Cgb UT Cox Cdepl Cox Cdepl

I 1 I 1 1 I ω = D · = t · · · D T 2 UT WLCdepl UT Cdepl L IM

• = · IM It W/L is the maximum ID for device in weak inversion.

∝ = Since It Dn and Dn µUT ,wehave

D I µ I ω n · D · U · D T 2 2 T L IM L IM

Single-T Gain Stages 5-15 Analog ICs; Jieh-Tsorng Wu Complete AC Analysis of Common-Emitter(Source) Ampliﬁer

R C i1 1 if f io

v v 1 C v s 1 o

g v R C m 1 22

v (s) 1 − s/z A (s) = o = A (0) 1 v v + + 2 vs(s) 1 b1s b2s

= − Av (0) gmR2 g =+m z1 Cf = + + + + b1 R1(C1 Cf ) R2(C2 Cf ) gmR1R2Cf = + + b2 R1R2(C1C2 C1Cf C2Cf )

Single-T Gain Stages 5-16 Analog ICs; Jieh-Tsorng Wu Complete AC Analysis of Common-Emitter(Source) Ampliﬁer

| | | | Using the dominant-pole approximation, let p1 p2

= + + 2 D(s) 1 b1s b2s s s 1 1 s2 s s2 = 1 − 1 − = 1 − s + + ≈ 1 − + p1 p2 p1 p2 p1p2 p1 p1p2

1 1 1 p ≈− = ≈− 1 + + + + + + b1 R1[C1 Cf (1 gmR2)] R2(C2 Cf ) R1[C1 Cf (1 gmR2)] b R (C + C ) + R (C + C ) + g R R C g C p ≈− 1 = 1 1 f 2 2 f m 1 2 f ≈− m f 2 + + + + b2 R1R2(C1C2 C1Cf C2Cf ) C1C2 C1Cf C2Cf

• The Miller approximation is a simpliﬁed dominant pole approximation.

• The Miller approximation results in incorrect estimation for the second pole.

Single-T Gain Stages 5-17 Analog ICs; Jieh-Tsorng Wu Common-Emitter Ampliﬁer with Emitter Degeneration

ii Cµ io vi vo

v r C g v r v 1 π π m 1 o o ve

vi Q1 RE

ii RE Cµ io vi vo gmeqv1 C v1 r πeq πeq roeq

Single-T Gain Stages 5-18 Analog ICs; Jieh-Tsorng Wu Common-Emitter Ampliﬁer with Emitter Degeneration

= To ﬁnd rπeq, Cπeq, and gmeq, let vo 0, then

+ + − = + (gm gπ sCπ)(vi ve) (GE go)ve

= + At frequencies where ω ωT gm/(Cπ Cµ),

v g + g + sC g + g e = m π π ≈ m π + + + + + + + vi gm gπ GE go sCπ gm gπ GE go

− RE −i v v g G − g g 1 β r g = o = g 1 − e −g · e = m E o π = g · o o meq v m v o v + + + m i i i gm gπ GE go 1 + g R 1 + 1 + 1 m E βo gmro

RE i v 1 + i = + − e = + ro (gπ sCπ) 1 (gπ sCπ) vi vi 1 + g R 1 + 1 + 1 m E βo gmro

Single-T Gain Stages 5-19 Analog ICs; Jieh-Tsorng Wu Common-Emitter Ampliﬁer with Emitter Degeneration • If β0 1, ro RE , and gmro 1

g C g ≈ m r ≈ r (1 + g R ) C ≈ π meq + πeq π m E πeq + 1 gmRE 1 gmRE

= To ﬁnd roeq, let vi 0, then

+ + + = − (gm gπ sCπ GE )ve go(vo ve)

v g g e = o ≈ o + + + + + + + vo gm gπ GE go sCπ gm gπ GE go + gmRE i v v g + G 1 β g = o = g 1 − e −g e = g · π E = g · o oeq v o v mv o + + + o o o o gm gπ GE go 1 + g R 1 + 1 + 1 m E βo gmro ≈ + ≈ + roeq ro(1 gmRE )ifgmRE β0 roeq ro(1 β0)ifgmRE β0

Single-T Gain Stages 5-20 Analog ICs; Jieh-Tsorng Wu Common-Source Ampliﬁer with Source Degeneration

i C i i gd o v v i o v v C o gs gs r v o s v i M1 R g v g v S m gs mb s R S i R C i i S gd o v v i o v gs C r gseq oeq

g v meq gs

Single-T Gain Stages 5-21 Analog ICs; Jieh-Tsorng Wu Common-Source Ampliﬁer with Source Degeneration

= To ﬁnd Cgseq and gmeq, let vo 0, then

+ − = + + (gm sCgs)(vi vs) (GS gmb go)vs

= At frequencies where ω ωT gm/Cgs,

v g + sC g s = m gs ≈ m + + + + + + + vi gm gmb GS go sCgs gm gmb GS go −i v v g G g g = o = g 1 − s −(g +g ) s = m S = m meq m mb o + + + R vi vi vi gm gmb GS go 1 + (g + g )R + S m mb S ro + + RS i v 1 gmbRS r i = sC 1 − s = sC · o gs gs R vi vi 1 + (g + g )R + S m mb S ro

Single-T Gain Stages 5-22 Analog ICs; Jieh-Tsorng Wu Common-Source Ampliﬁer with Source Degeneration

• If ro RS, g g g ≈ m = m meq + + + + 1 (gm gmb)RS 1 (1 χ)gmRS 1 + g R 1 + χg R C = C · mb S = C · m S gseq gs + + gs + + 1 (gm gmb)RS 1 (1 χ)gmRS

= To ﬁnd roeq, let vi 0, then

+ + + = − (gm gmb sCgs GS)vs go(vo vs) v g g s = o ≈ o v g + g + G + g + sC g + g + G + g o m mb S o gs m mb S o i v v g G g = o = g 1 − e − (g + g ) e = o S oeq o m mb + + + vo vo vo gm gmb GS go = + + + roeq RS ro[1 (gm gmb)RS]

• roeq can be made arbitrarily large by increasing RS.

Single-T Gain Stages 5-23 Analog ICs; Jieh-Tsorng Wu Common-Base Conﬁguration

VCC vo

R v1 r C g v r L π π m i o R C + L L VO vo Q1 v i ii − II ii

• ﬀ It is a current bu er, i.e., current gain 1, low Rin, and high Rout.

• = − Typically neglect rb, rc, and re, so that v1 vi .

• Combine Cµ, Ccs, and load capacitance into CL.

Single-T Gain Stages 5-24 Analog ICs; Jieh-Tsorng Wu Common-Base Conﬁguration AC Analysis

− To further simplify the analysis, neglect ro; i.e., assume go(vo vi ) gmvi , then

+ + = + = (gπ sCπ)vi gmvi ii (GL sCL)vo gmvi

v (s) g 1 Z (0) ⇒ Z (s) = o = m × = t t + + + − − ii (s) gm gπ sCπ GL sCL 1 s/p1 1 s/p2 g β g + g 1 g 1 Z (0) = m R = o R = α R p = − m π = − m p = − t + L + L o L 1 2 gm gπ βo 1 Cπ αo Cπ RLCL v (s) R 1 α Input Impedance = Z (s) = i = in R = Z (0) = r = o in − in in π g g ii (s) 1 s/p1 m m i (s) g v α Current Gain = o = m i = g Z (s) = o m in − ii (s) ii 1 s/p1

• | | = = + Note that p1 (1/αo)(gm/Cπ) >ωT gm/(Cπ Cµ).

• | | | | Expect p2 < p1 in typical cases.

Single-T Gain Stages 5-25 Analog ICs; Jieh-Tsorng Wu Common-Gate Conﬁguration

VDD C gd v o

V C -g v o gs m in g o Bias v g v v in mb in R C in L t I - i R C IN in L L i C’ in sb

= + = + = + + = + gm gm gmb CL Ct Cgd CL Cdb Cgd Cin Cgs Csb

The nodal equations are

= + − − = + + − iin (gm sCin)vin go(vo vin) gmvin (GL sCL)vo go(vo vin)

Single-T Gain Stages 5-26 Analog ICs; Jieh-Tsorng Wu Common-Gate Conﬁguration AC Analysis

− If the go(vo vin) terms are neglected, then

v R Transimpedance = Z (s) = o = L t − − iin 1 s/p1 1 s/p2

g g 1 p = − m = − m p = − 1 C + 2 in Cgs Csb RLCL v (s) 1/g Input Impedance = Z (s) = in = m in − iin(s) 1 s/p1 i (s) g v 1 Current Gain = o = m in = g Z (s) = m in − iin(s) iin 1 s/p1

• = + Note that p1 ωT gm/(Cgs Cgd).

Single-T Gain Stages 5-27 Analog ICs; Jieh-Tsorng Wu Common-Gate Conﬁguration AC Analysis

If go is considered,

v g + g Voltage Gain = A (s) = o = m o v v + + in go GL sCL

i = = in = + − − Input Impedance Yin(s) gm sCin go(Av 1) vin v A (s) = o = v Zt(s) iin Yin(s)

• → At low frequencies where ω 0, assuming gm go,

g + g g A = m o ≈ m v + + go GL go GL

g g A ⇒ Y = g − m + g ≈ m Z = v ≈ R in m G o R t L 1 + L 1 + L Yin go ro

Single-T Gain Stages 5-28 Analog ICs; Jieh-Tsorng Wu Common-Collector Conﬁguration (Emitter Follower)

RS Cµ VCC ii

RS vi v1 rπ Cπ gmv1 Q1 + vi VO vo v VI IBIAS o RL CL RL CL

= + RS RS rb

• ﬀ It is a voltage bu er, i.e., voltage gain 1, high Zin, and low Zout.

• Neglect Cµ, re, rc, and ro in the following analysis.

Single-T Gain Stages 5-29 Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Voltage Gain

Summing currents at the output, we have

+ = + = + = + + ii v1 gmv1 (GL sCL)vo ii (gπ sCπ)v1 vi RSii v1 vo

We have

g + g + sC 1 − s/z A (s) = m π π = A (0) 1 v + + + + + + v + + 2 gm gπ sCπ (GL sCL)[1 RS(gπ sCπ)] 1 b1s b2s

g + g g /α g R = m π = m o = m L Av (0) + + + + 1 + gmR gm gπ GL(1 RSgπ) gm/αo (1 gmR /βo) + + S RL S g R α + m L o βo 1 g + g g /α = − m π = − m o − z1 ωT Cπ Cπ R [C (1 + R /R ) + C (1 + g R /β )] R R C C b = L π S L L m S o b = L S π L 1 + + 2 + + 1 gm(RL/αo RS/βo) 1 gm(RL/αo RS/βo)

Single-T Gain Stages 5-30 Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Voltage Gain

• = = If CL 0, then b2 0 and 1 − s/z A (s) = A (0) 1 v v − 1 s/p1 1 + g (R /α + R /β ) 1 + g R p = − m L o S o ≈− m L 1 + + (RL RS)Cπ (RL RS)Cπ = Av (0) & z1 are unchanged from case where CL 0.

• = = If RS 0, again b2 0 and

1 − s/z A (s) = A (0) 1 v v − 1 s/p1

g R g R 1 + g R /α g A (0) = m L ≈ m L p = − m L o ≈− m if g R 1 v + + 1 + + m L αo gmRL 1 gmRL RL(Cπ CL) Cπ CL = z1 is unchanged from case where RS 0.

Single-T Gain Stages 5-31 Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Input Impedance

v (s) 1 1 + g /(g + sC ) 1 − s/z Z (s) = i = R + + m π π = R + R 1 in S + + S in − − ii (s) gπ sCπ GL sCL 1 s/p1 1 s/p2

= + + = + + ≈ + Rin (GL gm/αo)/(GL gπ) rπ (βo 1)RL rπ(1 gmRL) g /α + G 1 + g R /α g z = − m o L = − m L o ≈− m if g R 1 1 + + + + + + m L (βo 1)Cπ CL RL[(βo 1)Cπ CL] (βo 1)Cπ CL g ω = − 1 = − m − T = − 1 p1 p2 rπCπ βoCπ βo RLCL

B B’ = If CL 0, then Zin RS + 1 gmRL + + Z (s) = R + + R (1 gmRL)rπ Cπ/(1 gmRL) in S + L gπ sCπ

Single-T Gain Stages 5-32 Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Output Impedance

The output impedance looking into the transistor’s emitter is

1 + R (g + sC ) 1 − s/z Z (s) = S π π = R 1 out + + out − gm gπ sCπ 1 s/p1

1 + R g r + R r + R Z (0) = R = S π = π S = π S Z (∞) = R out out + + + out S gm gπ gmrπ 1 βo 1 1 + R g r + R 1 g /α z = − S π = − π S = − p = − m o −ω 1 R C r R C 1 C T S π π S π (rπ RS)Cπ π

• | | | | If rπ RS >αo/gm (or RS > 1/gm if βo 1), z1 < p1 , which represents inductive behavior.

• In addition, if RS rπ g |p | | |≈ 1 = m ≈ 1 z1 rπCπ βoCπ βo

Single-T Gain Stages 5-33 Analog ICs; Jieh-Tsorng Wu Emitter Follower’s Output Impedance

If βo 1, Zout(s) can be rewritten as: R R 1 + S + S sCπrπ R r + R + sC r R gm βo βo S = π S π π S ≈ Zout(s) β + 1 + sC r R o π π R + sC r S S π π βo

If R2 R1,wehave

(R + sL)R (R + sL)R Z Z (s) = 1 2 ≈ 1 2 out out + + + R1 R2 sL R2 sL R1

R2 Then

L R R = 1 + S = = S R1 R2 RS L Cπrπ gm βo βo

Single-T Gain Stages 5-34 Analog ICs; Jieh-Tsorng Wu Common-Drain Conﬁguration (Source Follower)

C v gd1 gv g mb1 o VDD V g v g v M1 I in g gs1 m1 gs1 o1 V o v I in o R C C SS gs1 I g C’ Bias C o2 L RC L SS M2 Simplified Small-Signal Model Bias i v g g

v I in g v gs1 m1 gs1 Y g v o R C’ C SS gs1 R’ C’ L L

= + = + + + = + + = 1 CS CS Cgd1 CL CL Csb1 Cdb2 Cgd2 GL go1 go2 gmb1 RL

Single-T Gain Stages 5-35 Analog ICs; Jieh-Tsorng Wu Source Follower’s Gate Voltage Gain

Summing the currents at the output node, we have

+ − − + = (gm1 sCgs1)(vg vo) vo(sCL GL) 0

The voltage gain from gate to output is

+ v (s) gm1 sCgs1 1 − s/z A (s) ≡ o = = A (0) 1 vg ( ) + + + vg − vg s gm1 GL s(Cgs1 CL) 1 s/p1

g g Cgs1 A (0) = m1 = m1 A (∞) = vg + g + g + g + g vg + gm1 GL m1 mb1 o1 o2 Cgs1 CL g g + G z = − m1 ≈−ω p = − m1 L 1 C T 1 + gs1 Cgs1 CL

Single-T Gain Stages 5-36 Analog ICs; Jieh-Tsorng Wu Source Follower’s Gate Voltage Gain

Avg For most practical cases 1 |p1| > |z1| Avg (0)

g + g g + g = g (1 + χ) (C ’ = 0) o1 o2 m1 mb1 m1 L ω p1

g ≈ m1 Avg Avg(0) + gm1 gmb1 |p1| = |z1| Avg (0) ≈ 1 + 1 χ1 ω g (1 + χ ) p ≈−m1 1 1 + Cgs1 CL   Avg  1  ≈ + |p1| < |z1| Avg (0) (1 χ )   z 1 C 1 1 + L Cgs1 ω p1 z1

Single-T Gain Stages 5-37 Analog ICs; Jieh-Tsorng Wu Source Follower’s Gate Input Impedance

The input admittance looking into the gate is

+ ig sCgs1(GL sCL) Y (s) = = sC [1 − A (s)] = g v gs1 vg + + + g gm1 GL s(Cgs1 CL)

Deﬁne the capacitance looking into the gate as

= Yg(s) sCg(s)

C = − g Cg(jω) Cgs1[1 Avg(jω)] C (0) = C [1 − A (0)] g gs1 vg C (∞) g C C ∞ = − ∞ = gs1 L Cg( ) Cgs1[1 Avg( )] C + C Cg(0) gs1 L ω

|p1| |z1|

Single-T Gain Stages 5-38 Analog ICs; Jieh-Tsorng Wu Source Follower’s Output Impedance

1 g < |Zo| v i g m1 R g S 1/g m1 C v gs1 g v R gs1 m1 gs1 S R ω v S o 1 i o C R gs1 S 1 Equivalent Circuit g > |Zo| m1 R S Rs Zo 1/g m1 L ω R2 R1 g 1 m1 C R C gs1 S gs1

= − + − + − = io (gm1 sCgs1)(vg vo) GSvg sCgs1(vg vo) 0

Single-T Gain Stages 5-39 Analog ICs; Jieh-Tsorng Wu Source Follower’s Output Impedance

The output admittance is

+ 1 i GS(gm1 sCgs1) G (g − G ) 1 Y (s) = ≡ o = = G + S m1 S = G + o + S + S sC R Zo(s) vo GS sCgs1 GS sCgs1 1 + gs1 S − − gm1 GS gm1 GS

• Note that = 1 ∞ = Zo(0) Zo( ) RS gm1

• The equivalent circuit is

1 RSCgs1 R = R = R L = 1 − 2 S − gm1 GS gm1 GS

Single-T Gain Stages 5-40 Analog ICs; Jieh-Tsorng Wu Source Follower’s Complete Frequency Response

v A (s) g + sC 1 − s/z = o = vg = m1 gs1 = 1 A(s) A(0) + + + + 2 s s2 iin GS sC Yg b b s b s + + S 0 1 2 1 ω Q 2 o ωo where g g R g A(0) = R · m1 = R · m1 L z = − m1 −ω S + S + 1 C T gm1 GL 1 gm1RL gs1 = + b0 GS(gm1 GL) = + + + + b1 GS(Cgs1 CL) (gm1 GL)CS GLCgs1 = + + b2 Cgs1CL CS(Cgs1 CL) and + GS(gm1 G ) ω = L o + + Cgs1CL CS(Cgs1 CL) + + + GS(gm1 GL)[Cgs1CL CS(Cgs1 CL)] Q = + + + GSCL (gm1 GL)CS GLCgs1

Single-T Gain Stages 5-41 Analog ICs; Jieh-Tsorng Wu Source Follower’s Complete Frequency Response • ωo is the pole frequency and Q is the Q-factor.

• The bandwidth can be estimated by + 1 gm1 G BW ≈ ω ≈ × L if C C o + L S RS(CS Cgs1) CL √ • If Q<1/ 2 ≈ 0.707, no peaking in |A(jω)|.

• If Q>0.5, the poles are√ complex, and overshoot appears in the step response. − 2− % Overshoot = 100e π/ 4Q 1

• If gm1 GL and CL CS G C g C G C 1 ≈ S L + m1 S + L gs1 Q g (C + C ) + + m1 gs1 S GSCL(Cgs1/CS 1) GS(gm1/GL)(1 CS/Cgs1)

Single-T Gain Stages 5-42 Analog ICs; Jieh-Tsorng Wu Compensated Source Follower

Y Y g VDD g V g M1 V o I in C1 C1 C2 I Bias C RC R L R in in 1 1 M2 Bias

= 1 + Yg sC2 −R − 1 1 sC1

+ 2 + 2 (Cgs1 CL) (Cgs1 CL) R = ≈ 1 − Cgs1(gm1CL GLCgs1) gm1Cgs1CL − Cgs1(gm1CL GLCgs1) gm1Cgs1CL Cgs1CL C = ≈ C = 1 + + + + 2 + (gm1 GL)(Cgs1 CL) (gm1 GL)(Cgs1 CL) Cgs1 CL

Single-T Gain Stages 5-43 Analog ICs; Jieh-Tsorng Wu Compensated Source Follower

• Adding R1 and C1 to the input port can eliminate the complex poles.

• For the compensated source follower, we have

+ Cgs1 g R 1 s g A(s) = [G + s(C + C )] · A = R m1 L × m1 S S 2 vg S + − − 1 gm1RL 1 s/p1 1 s/p2

where

G G = − S ≈− S p if C C 1 C C + L gs1 gs1 L C Cgs1 C + S S C +C gs1 L g + G g + G p = − m1 L ≈− m1 L if C C 2 + L gs1 Cgs1 CL CL

Single-T Gain Stages 5-44 Analog ICs; Jieh-Tsorng Wu Floating-Well Source Follower

VDD V in V o

Bias M2

p+ p+ n+ V o M1

N-Well V in M1 P-Substrate = The follower is in an isolated well tied to the M1 source. Thus, VSB(M1) 0, and g = m1 Avg(0) + + gm1 go1 go2

• The junction capacitance at the M1’s source is now replaced by the well-substrate junction capacitor.

• p+ guard-ring surrounding the n-well may be required.

Single-T Gain Stages 5-45 Analog ICs; Jieh-Tsorng Wu Multiple-Transistor Gain Stages

Jieh-Tsorng Wu

October 24, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Dominant-Pole Approximation

The response of an ampliﬁer has the form of

N(s) 1 + a s + a s2 + ···+ a sm A(0) A(s) = A(0) = A(0) 1 2 m ≈ + + 2 + ···+ n D(s) 1 b1s b2s bns 1 − s 1 − s ··· 1 − s p1 p2 pn

| || | | | ··· | | If p1 p2 , p3 , , pn , then p1 is a dominant pole. We have = − 1 − 1 −···− 1 ≈−1 = 1 b1 p1 p2 pn p1 p1

A(0) A(0) | | = ≈ A(jω) 2 2 2 2 ω ω ω + ω 1 + 1 + ··· 1 + 1 p p1 p2 pn 1

− = ≈| |≈ 1 3 dB Bandwidth ω−3dB p1 b1

Multiple-T Gain Stages 6-2 Analog ICs; Jieh-Tsorng Wu Zero-Value Time Constants

v η v i1 1 C1 C3 3 i3

• η is a linear active network without energy storage.

• The b1 in the denominator of the system function can be expressed as = = + + + ··· b1 T0 R10C1 R20C2 R30C3

Ri0 is the driving point resistance seen by Ci with all capacitors equal to zero.

Multiple-T Gain Stages 6-3 Analog ICs; Jieh-Tsorng Wu Zero-Value Time Constant Example

if R1

C R = R v v f v 10 1 s 1 C o = 1 R20 R2

g v R C m 1 22

To determine Rf 0, replace Cf with a current source if , then

= = − + v1 if R1 vo (if gmv1)R2 v − v R = 1 o = + + = + + 2 Rf 0 R1 R2 gmR1R2 R1 1 gmR2 if R1 We have = = + + + + b1 T0 R1C1 R2C2 (R1 R2 gmR1R2)Cf

Multiple-T Gain Stages 6-4 Analog ICs; Jieh-Tsorng Wu Darlington Conﬁguration

VCC VCC

ccccc c B Q1 C B M1 C B C c c Q2 Q2 v1 Ri Ro Ec EEc c c Gm v1 VEE VEE

For the BJT-BJT Darlington conﬁguration,

g c = + c = + + c = m2 c = β βo2(βo1 1) R rπ1 (βo1 1)rπ2 Gm Ro ro2 i + rπ1 1 + (βo1 1)rπ2

• Use to boost the eﬀective current gain of BJTs.

• No signiﬁcant application in pure-MOS circuits.

Multiple-T Gain Stages 6-5 Analog ICs; Jieh-Tsorng Wu BJT Cascode Conﬁguration

VCC

RL + VO vo R i2 gmv2 io S vo VBIAS Q2 gmv1 R S vi v1 v2 Vi Q1 rπ1 Ct1 rπ2 Ct2 CL RL

Rin2 = + + = + CL Cµ2 Ccs2 Capacitive Load Ct2 Cπ2 Ccs1 r + r α r 1 C = C + C (1 + g R ) R = π2 b2 = o2 + b2 ≈ t1 π1 µ1 m1 in2 in2 + + βo2 1 gm2 βo2 1 gm2

• ≈ ≈ ≈ + Usually IC2 IC1, then gm2 gm1 and Ct1 Cπ1 2Cµ1. • ≈ + If RL is large compared to ro2, then Rin2 (1/gm2) 1 RL/ro2 .

Multiple-T Gain Stages 6-6 Analog ICs; Jieh-Tsorng Wu BJT Cascode Characteristics

We can express voltage gain Av (s)as v (s) v i i v r α R = o = 1 2 o o = π1 1 × − × o2 × L Av (s) s ( gm1) s s v (s) vi v1 i2 i R + r 1 − 1 − 1 − i o S π1 p1 p2 p3

A (0) ⇒ A (s) = v v − − − (1 s/p1)(1 s/p2)(1 s/p3) r 1 1 g 1 A (0) = −α g R π1 p = − p = − m2 p = − v o2 m1 LR + r 1 2 α C 3 R C S π1 (RS rπ1)Ct1 o2 t2 L L The output resistance of the cascode stage is   1 + g r 1 + 1 + 1 m2 o1 β g r 1 + g r = · o2 m2 o2 =  + m2 o1 ≈ Rout ro2 ro2 1 βo2ro2 1 + gm2ro1 1 + gm2ro1 βo2 βo2

Multiple-T Gain Stages 6-7 Analog ICs; Jieh-Tsorng Wu MOST Cascode Conﬁguration

VDD VDD Telescopic Cascode Folded Cascode I 1 V V o 1 M2 Bias Bias V M2 in M1 V V R o 1 S V M1 I in R C 2 R L L S v o g’ v R C m2 s2 L L C R gd1 r RC’ S o2 L L v in v g1 v C r s2 gs1 o1 g v C m1 g1 x

= + = + + = + + gm2 gm2 gmb2 Cx Cdb1 Csb2 Cgs2 CL CL Cdb2 Cgd2

Multiple-T Gain Stages 6-8 Analog ICs; Jieh-Tsorng Wu MOST Cascode Low-Frequency Characteristics

The output impedance looking into M2’s drain is

= + + ≈ Rot2 ro1 (gm2ro1 1)ro2 gm2ro1ro2

The input admittance looking into M2’s source is

g G ≈ m2 in2 + go2/GL 1

The overall voltage gain is

v g g g r r R A = o ≈− m1 × m2 = g × m2 o1 o2 L ≈ g × (R R ) v v g + G g + G m1 + + m1 ot2 L in o1 in2 o2 L ro2 gm2ro1ro2 RL

• = = = = = = 2 Let gm gm1 gm2, ro ro1 ro2, and gm go.IfRL Rot2 gmro, then g g g g 1 g 2 G ≈ m ≈ m ≈ g A ≈− m m ≈− m in2 + + o v + goRL 1 gmro 1 2go go GL 2 go

Multiple-T Gain Stages 6-9 Analog ICs; Jieh-Tsorng Wu MOST Cascode Zero-Value Time Constant Analysis

Using the zero-value time constant method, we have

= = + + Rgs10 RS Rgd10 RS Rx0 gm1RSRx0 R = r R ≈ r (1/g )(g /G + 1) R = R R ≈ R g r r x0 o1 in2 o1 m2 o2 L L0 L ot2 L m2 o1 o2 = + + + = T0 Rgs10Cgs1 Rgd10Cgd1 Rx0Cx RL0CL ω−3dB 1/ T0

• = = = = = = 2 = Let gm gm1 gm2, ro ro1 ro2, gm go.IfRL Rot2 gmro and RS ro, then

r g r2 r g r R g r2 R ≈ r R = o R ≈ m o R ≈ R + o + m o S ≈ m o in2 o x0 2 L0 2 gd10 S 2 2 2

g r2 r g r2 ⇒ T = R C + m o C + oC + m o C 0 S gs1 2 gd1 2 x 2 L • RL0CL usually is the dominant term, unless RS is very large.

Multiple-T Gain Stages 6-10 Analog ICs; Jieh-Tsorng Wu MOST Cascode AC Characteristics

= = Let RL Rot2 gm2ro1ro2, then

g g G ≈ m2 ≈ m2 ≈ g in2 g R + 1 + o1 o2 L gm2ro1 1

The dc gain is g g 1 g g A (0) ≈− m1 × m2 ≈− · m1 · m2 v + + go1 Gin2 go2 GL 2 go1 go2 The dominant pole is 1 2 p = − ≈− 1 R C L0 L gm2ro1ro2CL | | | | At frequencies where p1 ω p2 ,

A (0) A (0) g ω g A (s) = v ≈ v ≈− m1 = − u ω = A (0) · p = m1 v 1 − s − s sC s u v 1 C p1 p1 L L

Multiple-T Gain Stages 6-11 Analog ICs; Jieh-Tsorng Wu MOST Cascode AC Characteristics

The second pole is approximately at

g + Y = − o1 in2 p2 Cx

Yin2 is the resistance looking into the M2’s source at high frequencies. v = − o − Yin2 gm2 go2 1 vs2

• + At frequencies ω (go2 GL)/CL,

v g + g g g o = m2 o2 ≈ m2 ⇒ Y ≈ g 1 − o2 + g ≈ g + + in2 m2 o2 m2 vs2 go2 GL sCL sCL sCL

g g ω ≈− m2 ≈− m2 ≈− T p2 Cx KCgs2 K where K is between 1 and 2 (usually closer to 1).

Multiple-T Gain Stages 6-12 Analog ICs; Jieh-Tsorng Wu Active Cascode Conﬁguration

v V o o V o -g v m2 (A+1) 2 I i o gv o V bias mb2 2 AM2 M2 g o2 M3 v 2 V i M1 g v C g V in M1 m1 i 2 o1

= + + + C2 (A 1)(Cgs2 Cgd3) Cgs3 = + + The M2’s transconductance is boosted as gm2 gm2(A 1) gmb2, thus

= + + ≈ + + Rot2 ro1 ro2 gm2ro1ro2 [gm2(A 1) gmb2]ro1ro2

g (A + 1) + g G ≈ m2 mb2 G = g (A + 1) + g + g if R = 0 in2 + in2 m2 mb2 o2 L go2/GL 1

Multiple-T Gain Stages 6-13 Analog ICs; Jieh-Tsorng Wu Active Cascode Characteristics

The equivalent transconductance is i G = o = × in2 = − 1 Gm gm1 gm1 1 v = g + G + + + + i vo 0 o1 in2 1 [gm2(A 1) gmb2]ro1 ro1/ro2

• = − ≈− = ·| | If A(s) has a dominant pole, i.e, A(s) ao/(1 s/p1) ωu/s, ωu ao p1 . The transfer function Vo/Vi has an additional zero and pole at

= − = − − 1 ≈− = z ωu p ωu ωu CL Capacitor at Vo gm2ro1ro2CL

• The non-dominant pole at the M2’s source is

g g (A + 1) + g g p ≈ m2 = m2 mb2 ≈ m2 2 + + + + C2 (A 1)(Cgs2 Cgd3) Cgs3 Cgs2 Cgd3

p2 is degraded slightly by the addition of ampliﬁer A.

Multiple-T Gain Stages 6-14 Analog ICs; Jieh-Tsorng Wu Super Source Follower Conﬁguration

VDD

g v o I2 C mb1 R C gd1 2 2 v V 2 M2 i v2 v g v V i M1 g gs1 m1 gs1 o1 I o V o v o C gs1 i o g v R R C I1 R C m2 2 1 L L L L

v r + R = o = o1 2 ≈ 1 1 Ro R1 i = [1 + (g + g )r ](1 + g R ) g + g g r o vi 0 m1 mb1 o1 m2 2 m1 mb1 m2 o1 v g r g r A (0) = o = m1 o1 ≈ m1 o1 v R +r 1 v = + + + 2 o1 + + + i io 0 1 (g g )r + 1 (gm1 gmb1)ro1 g r m1 mb1 o1 R1(1 gm2R2) m2 o2

Multiple-T Gain Stages 6-15 Analog ICs; Jieh-Tsorng Wu Diﬀerential Gain Stages

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Emitter-Coupled Pair

VCC Assume • = RC1 RC2 Q1 Q2. Vo1 Vo2 Ic1 Ic2 • = ≡ RC1 RC2 RC.

Vi1 Q1 Q2 Vi2 • Q1 and Q2 don’t saturate.

IEE • Neglect r , r , and r . REE b o µ • →∞ VEE Neglect REE, i.e, REE . ≡ − ≡ − Vid Vi1 Vi2 Icd Ic1 Ic2 = − = − = − = − − = − Vo1 VCC Ic1RC Vo2 VCC Ic2RC Vod Vo1 Vo2 (Ic1 Ic2)RC Icd RC Ic1 − ≈ VBE1/UT ≈ VBE2/UT = ⇒ = (VBE1 VBE2)/UT = Vid/UT Ic1 IS1e Ic2 IS2e IS1 IS2 e e Ic2

Diﬀerential Gain Stages 7-2 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Large-Signal Behavior

= ≡ Summing currents at the common emitter node with αF 1 αF 2 αF − αF IEE αF IEE α I = I + I = I 1 + e Vid/UT ⇒ I = I = F EE c1 c2 c1 c1 − c2 + 1 + e Vid/UT 1 + e Vid/UT 1 1 V I = I − I = α I − = α I tanh id cd c1 c2 F EE − + F EE 1 + e Vid/UT 1 + e Vid/UT 2UT V −V = − = − = − id = id Vod Vo1 Vo2 Icd RC αF IEERC tanh αF IEERC tanh 2UT 2UT

Diﬀerential Gain Stages 7-3 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair with Emitter Degeneration

• Series feedback used to exchange gain for linearity.

• Linear input range increased by approximately same factor gain is reduced.

• Doesn’t increase linear output range.

Diﬀerential Gain Stages 7-4 Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair

VDD I dd Assume R R D1 D2 I SS • M1=M2.

V o1 V o2 V • = ≡ IM V id RD1 RD2 RD. II d1 d2 V IM V i1 M1 M2 V i2 • Neglect ro.

I SS I • R →∞. SS SS VSS

≡ − ≡ − ≡ − = − Vid Vi1 Vi2 Idd Id1 Id2 Vod Vo1 Vo2 IddRD Assume M1 and M2 are in the saturation region,

1 1 W I = k(V − V )2 I = k(V − V )2 k = µC d1 2 gs1 t d2 2 gs2 t ox L

Diﬀerential Gain Stages 7-5 Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair Large-Signal Behavior

Summing currents at the common source node, we have

I I I I I + I = I ⇒ I = SS + dd I = SS − dd d1 d2 SS d1 2 2 d2 2 2 The gate voltages can be written as 2I 2I V = V + d1 V = V + d2 gs1 t K gs2 t K

The diﬀerential input voltage is 2I 2I 2 V = V − V = d1 − d2 = I − I id gs1 gs2 k k k d1 d2

Squaring 2 2 V 2 = I + I − 2 I I = I − I2 − I2 id k d1 d2 d1 d2 k SS SS dd

Diﬀerential Gain Stages 7-6 Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair Large-Signal Behavior

Rearrange, then we have k 4I I I I I I = V SS − V 2 and I = SS + dd I = SS − dd dd 2 id k id d1 2 2 d2 2 2

ff ff Define VIM as the di erential input voltage at which one of the MOST is turned o , i.e., k 4ISS 2 2ISS I = V − V ⇒ V = = 2(V )| = = 2(V )| = SS 2 IM k IM IM k ov1 Vid 0 ov2 Vid 0

Differential Gain Stages 7-7 Analog ICs; Jieh-Tsorng Wu Small-Signal Analysis of Differential Amplifiers

v v o1 o1 v v o2 o2 v v v v i1 i2 id id 2 2

v ic

The diﬀerential and common-mode signals are deﬁned as

v + v v + v v ≡ v − v v ≡ i1 i2 v ≡ v − v v ≡ o1 o2 id i1 i2 ic 2 od o1 o2 oc 2

= + 1 = − 1 = + 1 = − 1 vi1 vic vid vi2 vic vid vo1 voc vod vo2 voc vod 2 2 2 2 vo1 = A11 A12 vi1 vod = Adm Acdm vid vo2 A21 A22 vi2 voc Adcm Acm vic

Differential Gain Stages 7-8 Analog ICs; Jieh-Tsorng Wu Small-Signal Analysis of Differential Amplifiers

The voltage gain are deﬁned as v v v v = o1 = o1 = o2 = o2 A11 A12 A21 A22 v = v = v = v = i1 vi2 0 i2 vi1 0 i1 vi2 0 i2 vi1 0

The differential and common-mode gains are v A − A − A + A ff = = od = 11 12 21 22 Di erential-Mode Gain Adm v = 2 id vic 0 v A + A + A + A = = oc = 11 12 21 22 Common-Mode Gain Acm vic = 2 vid 0 v A − A + A − A ff = = oc = 11 12 21 22 Di erential-Mode-to-Common-Mode Gain Adcm vid = 4 vic 0 v ff = = od = + − − Common-Mode-to-Di erential-Mode Gain Acdm A11 A12 A21 A22 v = ic vid 0

Differential Gain Stages 7-9 Analog ICs; Jieh-Tsorng Wu Small-Signal Analysis of Differential Amplifiers

• Usually want to sense vid while rejecting vic, thus want Adm Acm,Acdm,Adcm.

• The common-mode-rejection ratio is deﬁned as Adm CMRR ≡ Acm

• = = In a perfectly balanced circuit, Acmd Adcm 0. However, in practice, these transfer functions are not zero because of component imbalances.

• The ratio Adm/A cdm is important because it indicates the extent to which a common- mode input corrupts the diﬀerential output.

Diﬀerential Gain Stages 7-10 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Diﬀerential-Mode Half Circuit

VCC VCC

RC RC RC +vod −vod +vod 2 2 2

Q1 Q2 Q1 E R RS S RS +vid −vid +vid 2 iEE 2 2 REE

VEE v v /2 r v = 0 ⇒ A = od = od = −g π (r R ) e dm v m + o C id vid/2 rπ RS

Diﬀerential Gain Stages 7-11 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Common-Mode Half Circuit

VCC VCC

RC RC RC voc voc voc

Q1 Q2 Q1 ix R RS S RS

vic vic vic 2REE 2REE 2REE

VEE VEE v g R R i = 0 ⇒ A = oc = − m C ≈− C x cm 2g R vic 1 + m EE 2REE αo

Diﬀerential Gain Stages 7-12 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Input Resistances

Rid Rid Rid 2 2 vi1 vi1 vi1 vi1 Ric Ric Ric 2

= = = = − ≡ Assume RS 0 and rb 0. When vic 0, ib1 ib2 ibd , v ﬀ = ≡ id = Di erential-Mode Input Resistance Rid 2rπ i = bd vic 0 = = ≡ When vid 0, ib1 ib2 ibc, v = ≡ ic = + + ≈ Common-Mode Input Resistance Ric rπ 2REE(βo 1) 2βoREE i = bc vid 0

In general v v v v =+ id + ic = − id + ic ib1 ib2 Rid Ric Rid Ric

Diﬀerential Gain Stages 7-13 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Frequency Response

| | Adm

Differential-Mode Common-Mode VCC VCC

| | Acm RC RC vod 2 voc ω zE p1

| | = Adm Q1 Q1 CMRR | | Acm

RS RS v id C 2 vic E 2REE 2

Diﬀerential Gain Stages 7-14 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Frequency Response

• Using the Miller approximation, the diﬀerential Response can be written as

v A (0) A (s) = od ≈ dm dm v − id 1 s/p1 r 1 A (0) = −g R π p = − C = C + C (1 + g R ) dm m C + + 1 + t π µ m C RS rb rπ Ct[(RS rb) rπ] • Because REE is usually large, the common-mode response is typically dominated by the time constant at the tail node of the pair.

v R 1 2R A (s) = oc ≈− C ≈ A (0) 1 − s/z Z (s) = = EE cm cm E E C + vic ZE (s) 1 + s E 1 sCE REE 2REE 2

R = − C = − 1 Acm(0) zE 2REE REECE

Diﬀerential Gain Stages 7-15 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Input Oﬀset Voltage and Current

VCC VCC

RC1 RC2 RC RC

V o V o V OS Q1 Q2 Q1 Q2 V i V i

I OS I I EE 2 EE VEE VEE Circuit with No Mismatches

• = − = − VOS and IOS is equal to the value of VID VI1 VI2 and IBD IB1 IB2 that must be = applied to the input to drive VOD 0.

Diﬀerential Gain Stages 7-16 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Input Oﬀset Voltage

For BJTs in the forward-active region,

2 IC qni Dn = VBE/UT = = IC ISe VBE UT ln IS A IS G(VCB)

The output condition is

I R = − − = ⇒ C1 = C2 VOD (IC1RC1 IC2RC2) 0 IC2 RC1

= = − Since VOS VID VBE1 VBE2,wehave I I I I R A G (V ) = C1 − C2 = C1 S2 = C2 · 2 · 1 CB1 VOS UT ln UT ln UT ln UT ln IS1 IS2 IC2 IS1 RC1 A1 G2(VCB2)

Diﬀerential Gain Stages 7-17 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Input Oﬀset Voltage

To describe the mismatch in the components, using

X + X ∆X ∆X ∆X = X − X X = 1 2 ⇒ X = X + X = X − 1 2 2 1 2 2 2

Then     1 ∆R R − ∆RC A − ∆A G + ∆G 1 − C 1 − 1 ∆A 1 + 1 ∆G =  C 2 · 2 · 2 · =  2 RC · 2 A · 2 G  VOS UT ln UT ln + ∆RC + ∆A − ∆G + 1 ∆RC + 1 ∆A − 1 ∆G R A 2 G 2 1 1 2 A 1 2 G C 2 2 RC

2 3 + = − y + y −···≈ From Taylor series, if y 1, ln(1 y) y 2 3 y.Wehave ∆R ∆R ∆I ≈ − C − ∆A + ∆G = − C − S VOS UT or VOS UT RC A G RC IS

Diﬀerential Gain Stages 7-18 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Input Oﬀset Voltage

• The oﬀset voltage drift due to temperature variation is dV ∆R ∆I ∆R ∆I V OS = d kT − C − S = k − C − S = OS dT dT q RC IS q RC IS T

• Nulling VOS usually doesn’t null dVOS/dT because of how it is accomplished. • ◦ VOS drifts in the 1 µV/ C range can be obtained with careful design.

Rx Rx

VCC VCC

RC2 RC2 RC1 RC1

Q1 Q2 Q1 Q2

Diﬀerential Gain Stages 7-19 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Input Oﬀset Current

The input oﬀset current is deﬁned as

IC1 IC2 I ≡ I | = = I − I = − OS BD VOD 0 B1 B2 βF 1 βF 2

As before, the formula can be arranged as

+ ∆IC − ∆IC IC IC I ∆I ∆β I = 2 − 2 ≈ C C − F OS ∆β ∆β + F − F βF IC βF βF 2 βF 2

= Since VOD 0, we have ∆I ∆R I ∆R ∆β = ⇒ C = − C ⇒ ≈− C C + F IC1RC1 IC2RC2 IOS IC RC βF RC βF

• A typical βF mismatch distribution displays a deviation of about 10%.

Diﬀerential Gain Stages 7-20 Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair Input Oﬀset Voltage

VDD VDD

RD1 RD2 RD RD

V o V o V OS M1 M2 M1 M2 V i V i

I SS I SS VSS VSS Circuit with No Mismatches

2I = − = + D = VOS VGS1 VGS2 VGS Vt k µCox k (W/L)

Diﬀerential Gain Stages 7-21 Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair Input Oﬀset Voltage

= Since VOD 0, we have ∆I ∆R = ⇒ D = − D ID1RD1 ID2RD2 ID RD The oﬀset voltage is   + 1 ∆ID − 1 ∆ID 2I  1 2 I 1 2 I  V = V − V = ∆V + D ×  D − D  OS GS1 GS2 t k (W/L) 1 + 1 ∆(W/L) 1 − 1 ∆(W/L) 2 (W/L) 2 (W/L)

Using Taylor series, V − V ∆I ∆(W/L) V − V ∆R ∆(W/L) ≈ + GS t D − ≈ + GS t − D − VOS ∆Vt ∆Vt 2 ID (W/L) 2 RD (W/L) 2I 2[(I + I )/2] I − ≡ D = = D1 D2 = SS VGS Vt Vov k (W/L) k (W/L) k (W/L)

Diﬀerential Gain Stages 7-22 Analog ICs; Jieh-Tsorng Wu Source-Coupled Pair Input Oﬀset Voltage

• ∆Vt can be minimized by careful layout. Large-geometry structures can achieve a ∆Vt with standard deviations on the order of 2 mV in modern MOS process.

• − ﬀ Due to the VGS Vt term, o set in MOST pairs is typically 10 times larger than that of BJT pairs.

• ﬀ Both Vt and Vov have a strong temperature dependence, a ecting VGS in opposite directions.

• dVOS/dT in MOST pairs is not well correlated with VOS, unlike BJT pairs.

Diﬀerential Gain Stages 7-23 Analog ICs; Jieh-Tsorng Wu Unbalanced Resistor Circuit Analysis

id ic 2 i1 i2 ∆R id ∆R R1 v1 R2 v2 v ic d 2 2 2 vc 2 R R

Differential HC Common-Mode HC i ∆R i ∆R v = v − v = i R − i R = i + d R + − i − d R − = i R + i (∆R) d 1 2 1 1 2 2 c 2 2 c 2 2 d c

i + id R + ∆R + i − id R − ∆R v + v c 2 2 c 2 2 ∆R v = 1 2 = = i R + i c 2 2 c d 4

Diﬀerential Gain Stages 7-24 Analog ICs; Jieh-Tsorng Wu Unbalanced gm Circuit Analysis

id ic 2 i1 i2

gm1vg 1 m2v 2

v g g v g d ∆ m g v ∆ m d m vc m c 2 2 2 2 Differential HC Common-Mode HC ∆g v ∆g v i = i − i = g + m v + d − g − m v − d = g v + ∆g v d 1 2 m 2 c 2 m 2 c 2 m d m c

g + ∆gm v + vd − g − ∆gm v − vd i + i m 2 c 2 m 2 c 2 ∆g v i = 1 2 = = g v + m d c 2 2 m c 4

Differential Gain Stages 7-25 Analog ICs; Jieh-Tsorng Wu Unbalanced Differential Amplifier

id id ∆R ∆R ic i R R R R c 2 2 2 1 2 2 vod voc 2 vo1 vo1 vic v 1 gm1v gm1 vi1 gm2 vi2 vs ∆gm vid v g 2RSS g id ∆ m 2 2 RSS m v1 2 2

Differential HC Common-Mode HC

= = If ∆R 0 and ∆gm 0, we have

g R A = −g RA = − m A = 0 A = 0 dm m cm + cdm dcm 1 2gmRSS

Differential Gain Stages 7-26 Analog ICs; Jieh-Tsorng Wu Unbalanced Differential Amplifier

Including mismatches, the voltage gains are vod = Adm Acdm vid voc Adcm Acm vic where ∆gm − ∆gm ∆R v ∆gmRSS R A = od = −g R + 2 2 2 dm m + vid = 1 2g R vic 0 m SS v g ∆R + ∆g R = od = − m m Acdm v = 1 + 2g R  ic vid 0 m SS  2 − ∆gm  ∆gmR gm∆R 2gmRSS  v  2gm  = oc = −1 + Adcm gm∆R  v = 4  1 + 2g R  id vid 0 m SS

∆g v g R + m ∆R = oc = − m 2 2 Acm v = 1 + 2g R ic vid 0 m SS

Differential Gain Stages 7-27 Analog ICs; Jieh-Tsorng Wu Simplified Analysis for Unbalanced Differential Amplifier

ˆ ˆ First assume no mismatches, and find Adm, Acm, vôd , id , vôc, ic, and vˆ1,

g R A = −g RA = − m vˆ = A v = −g Rv iˆ = g v dm m cm + od dm id m id d m id 1 2gmRSS

g Rv v g v vˆ = A v = − m ic vˆ = ic iˆ = m ic oc c ic + 1 + c + 1 2gmRSS 1 2gmRSS 1 2gmRSS Then consider only the mismatch terms, ∆R ∆g v v g ∆R + ∆g R −iˆ − R mvˆ = od ⇒ A = od = − m m c 2 2 1 2 cdm v 1 + 2g R ic = m SS vid 0

iˆ ∆g v v ∆g R − d ∆R − m id = ⇒ = oc = −1 + m R voc Adcm gm∆R 2 2 2(1 + 2g R ) 2 v = 4 1 + 2g R m SS id vic 0 m SS

Diﬀerential Gain Stages 7-28 Analog ICs; Jieh-Tsorng Wu Current Mirrors and Active Loads

Jieh-Tsorng Wu

November 7, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Simple BJT Current Mirror

VCC = = IC2 βF 1 βF 2 βF I V V = V = V IN o A1 A2 A VCE1 I = I eVBE/UT 1 + C1 S1 V IC1 IC2 A Q1 Q2 VCE2 = VBE/UT + Vo IC2 IS2e 1 IB1 IB2 VA V I I CE(sat) = + + = + C1 + C2 IIN IC1 IB1 IB2 IC1 βF βF

− + VCE2 VCE1 I V − V I 1 V +V I = I S2 1 + CE2 CE1 = I · S2 · A CE1 C2 C1 + IN − IS1 VA VCE1 IS1 + 1 + 1 IS2 + VCE2 VCE1 1 β β I 1 V +V F F S1 A CE1 I V − V I = · S2 · + = ≈ CE2 CE1 − 1 + S2 IC2 IIN (1 ) Systematic Gain Error 1 IS1 VA βF IS1 = = = Ro2 ro2 Vo(min) VCE2(sat) VCC(min) VBE1(on)

Current Mirrors 8-2 Analog ICs; Jieh-Tsorng Wu Simple BJT Current Mirror with Beta Helper

VCC • Ignore Early eﬀect. For Q1 and Q2, let

I I β = β = β C3 = S3 IIN Vo F 1 F 3 F IC1 IS1 Q2 I I C1 C3 • From KCL, Q1 Q3 I I B1 B3 I + I 1 I = I + B1 B3 = I + (I +I ) IN C1 + C1 + C1 C3 βF 2 1 βF (βF 2 1) I I I = S3 = · S3 · 1 = · S3 · + IC3 IC1 IIN IIN (1 ) IS1 IS1 + 1 + IS3 IS1 1 + 1 I βF (βF 2 1) S1 1 I ≈− 1 + S3 + βF (βF 2 1) IS1 = = = + Ro3 ro3 Vo(min) VCE3(sat) VCC(min) VBE1(on) VBE2(on)

Current Mirrors 8-3 Analog ICs; Jieh-Tsorng Wu Simple BJT Current Mirror with Emitter Degeneration

VCC I I V = I R + U ln C1 = I R + U ln C3 B C1 1 T I C3 3 T I S1 S3 IIN I 3 I 4 I I I I C C C3 S1 − = C1 S3 IC1R1 1 UT ln Q2 IC1 IS3 IC3 IS1 Q3 I R I I If S3 = 1 then C3 = S3 Q1 Q4 IS1 R3 IC1 IS1 • The BJT should be scaled with corresponding VB emitter resistor. R1 R3 R4

I R V − V V − V ≈ + = + C3 3 | = CE3 CE1 = CE3 CE1 Ro3 ro3(1 gm3R3) ro3 1 =∞ βF + I R UT VA(1 gm3RE ) V 1 + C3 3 A UT = + = + + Vo(min) VCE3(sat) IC3R3 VCC(min) VBE1(on) VBE2(on) IC1R1

Current Mirrors 8-4 Analog ICs; Jieh-Tsorng Wu Matching Consideration in BJT Current Mirrors

Assume Q3Q4, and let

≡ − ≡ − ≡ − ≡ − ∆IC IC3 IC4 ∆IS IS3 IS4 ∆αF αF 3 αF 4 ∆R R3 R4

I + I I + I α + α R + R I ≡ C3 C4 I ≡ S3 S4 α ≡ F 3 F 4 R ≡ 3 4 C 2 S 2 F 2 2 To calculate mismatch between IC3 and IC4,

I I I I = + = + = C3 + C3 = C4 + C4 VB VBE3 IE3R3 VBE4 IE4R4 UT ln R3 UT ln R4 IS3 αF 3 IS4 αF 4

I I I I U ln C3 − U ln S3 + C3 R − C4 R = 0 T I T I α 3 α 4    C4  S4 F 3 F 4 ∆IC ∆R ∆IC ∆R ∆IC ∆IS + + − − I + I + IC 2 R 2 IC 2 R 2  C 2  −  S 2  + − = UT ln UT ln 0 I − ∆IC I − ∆IS α + ∆αF α − ∆αF C 2 S 2 F 2 F 2 ∆I ∆I I R ∆I ∆α I R ∆I ∆α C − S + C + C + ∆R − F − C − C − ∆R + F = UT UT 1 1 0 IC IS αF 2IC 2R 2αF αF 2IC 2R 2αF

Current Mirrors 8-5 Analog ICs; Jieh-Tsorng Wu Matching Consideration in BJT Current Mirrors

With above approximations, we obtain   gmR ∆I ∆I ∆α C ≈  1  S + αF −∆R + F g R g R IC 1 + m IS 1 + m R αF αF αF

For a typical bipolar process

∆I ∆α ∆R S ±1% −±10% F ±0.1%(npn) ± 1%(pnp) ±0.1% −±2% IS αF R

• If gmR 1, the IC mismatch is determined by IS mismatch.

• If gmR 1, the IC mismatch is determined by R and αF mismatches.

Current Mirrors 8-6 Analog ICs; Jieh-Tsorng Wu Simple MOST Current Mirror

IIN V V D2 D3 k = µ C n ox IID2 D3 1 W VD1 I = k (V − V )2(1 + λ V ) IN 2 L R t1 1 D1 1 M1 M3 1 W VR M2 I = k (V − V )2(1 + λ V ) D2 2 L R t2 2 D2 2 = 1 W − 2 + ID3 k (VR Vt3) (1 λ3VD3) 2 L 3 = = = = Let Vt1 Vt2 Vt and λ1 λ2 λ, then

(W/L) 1 + λV (W/L) V − V I = I · 2 · D2 = I · 2 · (1 + ) ≈ λ(V − V ) = D2 D1 D2 IN 1 + IN D2 D1 (W/L)1 λVD1 (W/L)1 VA

1 2I R = r = V = V ≈ V ≈ IN V = V = V + V o2 o2 o2(min) ov2 ov1 DD(min) GS1 t ov1 λ2ID2 k (W/L)1

Current Mirrors 8-7 Analog ICs; Jieh-Tsorng Wu Matching Consideration in Simple MOST Current Mirror

Ignore λ eﬀects. Assume M2M3, and let

≡ − ≡ − ≡ − ∆ID ID2 ID3 ∆(W/L) (W/L)2 (W/L)3 ∆Vt Vt2 Vt3

I + I (W/L) + (W/L) V + V ≡ D2 D3 ≡ 2 3 ≡ t2 t3 ID (W/L) Vt 2 2 2 2I 2I V = V + V = V + V = V + D2 = V + D3 R t2 ov2 t3 ov3 t2 t3 k (W/L)2 k (W/L)3 Neglecting all second order terms, we obtain

∆I ∆(W/L) ∆V 2I D = − t V = D ov ID (W/L) Vov /2 k (W/L)

• To maximize output swing, want a small Vov . But then ∆ID/ID increases as Vov decreases for a given ∆Vt.

Current Mirrors 8-8 Analog ICs; Jieh-Tsorng Wu Layout Considerations

VDD

Vg VSS Vs V’s V’’s VSS

Voltage Routing Current Routing

Current Mirrors 8-9 Analog ICs; Jieh-Tsorng Wu BJT Cascode Current Mirror

V o vo vo IIN io io I o v v Q4 Q2 g 2 rπ2 ro2 2 rπ2 ro2 m2 gm2v2 gm2v2

Q3 Q1 v g 1 r ro1 rex ro1 m1 π1 gm1v1

1 1 g g 1 g = g ⇒ ≈ g m1 ≈ m2 ≈ ⇒ R = r r ≈ r m1 m2 r m1 + 1 + 1 β + 2 r E o1 ex π2 ex rπ2 o2 π2  gm2 gm1 g R β r β r R ≈ r 1 + m2 E  ≈ r 1 + o2 π2 ≈ o2 o2 o o2 g R o2 + 1 + m2 E rπ2 rπ2 2 βo2 = + ≈ + = + Vo(min) VCE1 VCE2(sat) VBE3(on) VCE2(sat) VCC(min) VBE3(on) VBE4(on)

Current Mirrors 8-10 Analog ICs; Jieh-Tsorng Wu BJT Cascode Current Mirror

Neglect Early eﬀect. Let Q1=Q3,

β β I = I I = I F = I F C3 C1 C2 C1 + C3 + βF 1 βF 1

From KCL,

I I I I = I + I + I = I + I + I + I = I + C3 + C3 + C3 IN C4 B4 B2 C3 B3 B1 B2 C3 + βF βF βF 1

Thus

β β 1 4β + 2 I = I F = I · F · = I · 1 − F C2 C3 + IN + + 2 + 1 IN 2 βF 1 βF 1 1 + β + 4β + 2 βF βF 1 F F

4β + 2 4 I = I (1 + ) ⇒ = − F ≈− C2 IN 2 + + β + 4 βF 4βF 2 F

Current Mirrors 8-11 Analog ICs; Jieh-Tsorng Wu MOST Cascode Current Mirror

V IIN o i -g v g v o I m2 2 mb2 2 V o v 1 o g M4 M2 o2 V v 2 2 M3 M1 g V o1 3

= + + + ≈ + Ro ro1ro2(gm2 gmb2 go1 go2) ro1ro2gm2(1 χ2) = + = + + Vo(min) VDS1 VDSAT2 Vt3 Vov3 Vov2 = + = + + + VDD(min) VGS3 VGS4 Vt3 Vt4 Vov3 Vov4 0

Current Mirrors 8-12 Analog ICs; Jieh-Tsorng Wu MOST High-Swing Cascode Current Mirror

1 VDD VDD (W/L) = (W/L) 4 4 I V o I V o ⇒ = + IN IN VGS4 Vt 2Vov V I 2 I o o V W t M5 4L M4 M2 M4 V = + 3 M2 V1 Vt Vov Vov V V = + 1 4 V2 2Vt 3Vov M3 M1 M3 M1 = + M6 V3 Vt 2Vov = V4 Vov

= + = = + = + Vo(min) VDS1 VDSAT2 2Vov VDD(min) VGS3 VGS4 2Vt 3Vov V − V V − (V + V ) V ≈ DS1 DS3 ≈ ov t ov = − t VA VA VA

• ﬀ In practice, select (W/L)4 < (1/4)(W/L) due to body e ect and design margin.

Current Mirrors 8-13 Analog ICs; Jieh-Tsorng Wu MOST Sooch Cascode Current Mirror

VDD VDD 1 1W I I I = k (V − V )2 IN IN IN 2 4 L B t VB V 2 = 1W − − 2 W k (VB Vt)VA 2VA MB M6 3 L L VA V ⇒ = + = WWo VB Vt 2Vov VA Vov MA M5 3L 3L I V o 1 = + V1 Vt Vov M4 M2 V V = 2V + 3V 3 2 t ov V V 5 4 = + V3 Vt 2Vov M1 M3 = V4 Vov = V5 Vov

= + = = = + = Vo(min) VDS1 VDSAT2 2Vov VDD(min) V2 2Vt 3Vov 0

Current Mirrors 8-14 Analog ICs; Jieh-Tsorng Wu MOST Low-Voltage High-Swing Cascode Current Mirror

= + VDD V1 Vt Vov = + V2 Vt 2Vov I I V o IN IN = V3 Vov I = o V4 Vov W M2 4L V M4 M5 2 V V 4 3 = + = Vo(min) VDS1 VDSAT2 2Vov M3 M1 V = = + 1 VDD(min) V2 Vt 2Vov = 0

• ﬀ In practice, select (W/L)5 < (1/4)(W/L) due to body e ect and design margin.

• − ⇒ To bias M2 and M4 in the active region, want V2 V1

Current Mirrors 8-15 Analog ICs; Jieh-Tsorng Wu Sackinger¨ Current Mirror

VDD V o 1 If A = g r VDD VDD m5 o5 I in I o 2 1 I B2 I B1 ⇒ R ≈ g g r r r o 2 m1 m5 o1 o3 o5 M2 M1

M6 M5 = + = + + Vo(min) VGS5 VDSAT1 Vov1 Vov5 Vt VSS M4 M3 VSS = + VDD(min) VGS5 VVGS1 = + + VSS Vov1 Vov5 2Vt

• It may be necessary to add local compensation capacitors to the enhancement loops to prevent ringing during transients.

• The scheme can substantially slow down the settling times for large-signal transients. A typical settling-time might be increased by 50%.

Current Mirrors 8-16 Analog ICs; Jieh-Tsorng Wu Gatti Current Mirror

VDD V o VDD VDD I I in o = + + VGS5 Vov3 Vov7 Vt I 4 I 4 I I B B B B ⇒ = VDS3 Vov3 M2 M1

M8 M6M5 M7 = + VSS VSS Vo(min) VDS3 VDSAT1 = + Vov1 Vov3 M4A M3A = M4 M3 VDD(min) VGS5 = + + VSS Vov3 Vov7 Vt

• = × If (W/L)1,2,3,4 n (W/L)5,6,7,8,3A,4A, keep Iin

• M2 can be a ﬁxed-bias cascode. The resulting circuit is less prone to instability.

Current Mirrors 8-17 Analog ICs; Jieh-Tsorng Wu BJT Wilson Current Mirror

V o vo IIN io I o β r ≈ o2 o2 Ro v 2 Q2 2 rπ2 ro2 gm2v2 = + Vo(min) VBE1(on) VCE2(sat) = + VDD(min) VBE1(on) VBE2(on) Q3 Q1 Rin v1 g gm3v1 m1 2 V ≈− − + BE2 2 + + V βF 2βF 2 A = = = Assume Q1 Q2 Q3, then IC1 IC3, and I I β 2 β I = I + C2 = I + C2 I = −I F = I 1 + F IN C3 β C1 β C2 E2 β + 1 C1 β β + 1 F F F F F 2 I I = I = I 1 − = IN O C2 IN 2 + + + 2 β 2β 2 1 + F F βF (βF 2)

Current Mirrors 8-18 Analog ICs; Jieh-Tsorng Wu MOST Wilson Current Mirror

IIN Vo R I in i V o gv g (-vv )g v o 1 mb4 3 m2 1 2 mb2 2 v v 1 o M4 M2 g g g o2 V o4 m4 3 v v 3 2 M3 M1 V 2

ggggv o3m3 2 m1 o1   g g g ≈  + m2 + + m2 · m3  Ro ro2 1 (1 χ2) + g g + · Gin gm4 m1 m1 G g + in o3 gm4(1 χ4) ≈ = + = + 0 Vo(min) VGS1 VDSAT2 VDD(min) VGS1 VGS2

Current Mirrors 8-19 Analog ICs; Jieh-Tsorng Wu Complementary Current Source Load

VDD

C R gd1 o2 M2 V v v o i o C C’ gs1 L Vi M1 C L g v g m1 i o1

= + = + GL go1 Go2 CL CL Co2

• − The Vo range in normal operation is between VDSAT1 and VDD Vo2(min).

Current Mirrors 8-20 Analog ICs; Jieh-Tsorng Wu Current Mirror Load

VDD C i v gd2 o v 1 o V R i M0 L Vo i i M1 M2 C L g v g g g C g v g R C m0 i o0 m1 o1 t1 m2 1 o2 L t2

= + + = + + + + ···= G1 gm1 go1 go0 Ct1 Cgs1 Cgs2 Cdb0 Cdb1 KCgs1 = + = + + ··· GL go2 GL Ct2 CL Cdb2

i g A (0) ⇒ ≡ o = m2 = I Neglect Cgd2 AI(s) i = G + sC − i vo 0 1 t1 1 s/p1 g g G g ω = m2 = m2 · 1 = 1 ≈ m1 = T 1 AI(0) p1 go1 go0 G1 gm1 1 + + Ct1 KCgs1 K gm1 gm1

Current Mirrors 8-21 Analog ICs; Jieh-Tsorng Wu Diode-Connected Load

-g v g v VDD o Vo M1 Off m2 o mb2

VDD Vt2 C g gd1 o2 M2 M1 Sat’d V v v o i o C C’ gs1 L Vi M1 C M1 Linear L V g v g i o1 Vt1 m1 i

= + + + = + + + GL gm2 gmb2 go1 go2 CL CL Cdb1 Cgs2 Csb2 g g g = − m1 = − m1 ≈− m1 Av(0) + + + + G gm2 gmb2 go1 go2 gm2 gmb2 L g 1 2k I 1 (W/L) 1 A (0) ≈− m1 = − 1 D1 = − 1 v g 1 + 2 1 + 1 + m2 χ2 k2ID2 χ2 (W/L)2 χ2

Current Mirrors 8-22 Analog ICs; Jieh-Tsorng Wu Voltage and Current References

Jieh-Tsorng Wu

November 13, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Sensitivity and Temperature Coeﬃcient

• The sensitivity of a parameter y to a second one x is deﬁned as ∆y y x ∂y Sy ≡ = · x ∆x y ∂x x

• The variation of a parameter y that results from changes in temperature is usually characterized by its fractional temperature coeﬃcient, which is deﬁned as the fractional change per degree centigrade change in temperature. ∆y y 1 ∂y TC ≡ = · y ∆T y ∂T

Voltage and Current References 9-2 Analog ICs; Jieh-Tsorng Wu Simple Current Sources

VCC VDD

R R VC2 VD2

IC2 ID2

Q1 Q2 M1 M2

− VCC VBE1(on) V I ≈ I ≈ ≈ CC C2 C1 R R I V ∂I V ∂ V 1 S C2 = CC · C2 = CC · CC = R · = 1 VCC I ∂V ∂V R R C2 CC VCC/R CC ∂I 1 ∂V V ∂R 1 ∂V 1 ∂R C2 = CC − CC = I CC − ⇒ TC = TC − TC 2 C2 IC2 VCC R ∂T R ∂T R ∂T VCC ∂T R ∂T

Voltage and Current References 9-3 Analog ICs; Jieh-Tsorng Wu BJT Widlar Current Source

VCC →∞ →∞ Let βF and VA ,

I R V − V V IN 1 ≈ CC BE1 ≈ CC IIN ≈ IO IIN S 1 R R VCC 1 1 I I I I Q1 Q2 IN = O + ⇒ IN · S2 = UT ln UT ln IOR2 UT ln IOR2 IS1 IS2 IO IS1 R2 I = ⇒ IN = If IS1 IS2 UT ln IOR2 IO ﬀ Di erentiating both sides of the above equation with respect to VCC,   I 1 ∂I I ∂I ∂I ∂I 1 I ∂I U O IN − IN O = R O ⇒ O =   O IN T 2 2 I R IIN IO ∂VCC I ∂VCC ∂VCC ∂VCC + O 2 IIN ∂VCC O 1 U     T

I V ∂I 1 V ∂I 1 I 1 S O = CC O =   CC IN =   S IN ≈ VCC I R I R VCC I R IO ∂VCC 1 + O 2 IIN ∂VCC 1 + O 2 1 + O 2 UT UT UT

Voltage and Current References 9-4 Analog ICs; Jieh-Tsorng Wu MOST Widlar Current Source

Let V →∞and γ → 0, VDD A IIN R1 V − V − V 1 W 2I I = DD ov1 t = k V 2 V = IN IO IN ov1 ov1 R1 2 L 1 k (W/L) 1 M1 M2 2I V = V + I R ⇒ I R + O − V = 0 ov1 ov2 O 2 O 2 ov1 k (W/L)2 R2 1 2 2 I = − + + 4R V O 2 2 ov1 R2 k (W/L)2 k (W/L)2

1 ∂I 1 1 ∂V ∂V 2 1 ∂I O = 4R ov1 ov1 = IN 2 2 I ∂VDD 4R2 2 + ∂VDD ∂VDD k (W/L) 2 I ∂VDD O 4R2Vov1 1 IN k (W/L)2 V V 1 IO = ov1 IIN ≈ ov1 IIN = IIN SV SV SV SV DD 2 + DD 2 DD 2 DD Vov2 4IOR2Vov1 4Vov1

Voltage and Current References 9-5 Analog ICs; Jieh-Tsorng Wu BJT Peaking Current Source

VCC Since IIN

− = VBE1 IINR VBE2 R I I I IN − = O O UT ln IINR UT ln IS1 IS2 Q1 Q2 We have I I IN · S2 = UT ln IINR IO IS1

If Q1=Q2, then

− UT IIN = IINR/UT = IO IINe R ln IIN IO

Voltage and Current References 9-6 Analog ICs; Jieh-Tsorng Wu MOST Peaking Current Source

VDD For M1 and M2 in strong inversion

IIN = 1 W 2 = 1 W − 2 IO k Vov2 k (Vo1 IINR) 2 L 2 2 L 2 R 2I IO V = IN ov1 k (W/L)1 M1 M2 For M1 and M2 in weak inversion region, I − = IN − VGS2 Vt nUT ln IINR (W/L)1It

If M1=M2, W − − ≈ (VGS2 Vt)/(nUT ) ≈ IINR/(nUT ) IO It e IINe L 2

Voltage and Current References 9-7 Analog ICs; Jieh-Tsorng Wu BJT VBE Referenced Current Source

VCC

I V − V − V IIN R1 O = CC BE1 BE2 IIN R1 Q2 I = IN VBE1 UT ln Q1 IS1 V U I = BE1 = T IN R2 IO ln R2 R2 IS1

∂I U I ∂I I ∂I U ∂I O = T S1 1 IN − IN S1 = T 1 IN 2 ∂VCC R2 IIN IS1 ∂VCC I ∂VCC R2 IIN ∂VCC S1 I V ∂I V U 1 ∂I U I U I S O = CC O = CC T IN = T S IN = T S IN VCC VCC VCC IO ∂VCC IO R2 IIN ∂VCC IOR2 VBE1(on)

Voltage and Current References 9-8 Analog ICs; Jieh-Tsorng Wu MOST Vt Referenced Current Source

VDD V − V − V V − V − V − V − V I R1 DD GS1 GS2 DD ov1 ov2 t1 t2 IN IO I = = IN R R 1 1 M2 2I 2I V = IN V = O ov1 ov2 M1 k (W/L) k (W/L) 1 2 R2 + 2IIN Vt1 V V + V k (W/L)1 = GS1 = t1 ov1 = IO R2 R2 R2

I V I V I S O = ov1 S IN = ov1 S IN VDD VDD VDD 2IOR2 2VGS1

Voltage and Current References 9-9 Analog ICs; Jieh-Tsorng Wu Self-Biasing BJT VBE Reference

VCC

Q4 IO Q3 Q6 I I ≈ I · S3 IN O I IO1 S4 IIN IO V U I ≈ BE1 = T IN IO ln Q2 A IO2 R R IS1

Q1 Q5 R IIN = − TCI TCV TCR B O BE1 VEE

• Two possible operating states, A and B. State A is stable and desirable.

• State B, where only leakage currents ﬂow, would normally be unstable. However, it may become stable due to low loop gain under low-current condition.

• There may exist hidden states when the supply is ramping from 0 V.

Voltage and Current References 9-10 Analog ICs; Jieh-Tsorng Wu Self-Biasing BJT VBE Reference with Start-Up Circuit

VCC • ≈ Q4 When in zero-current state (B), Vx 0, Q3 Q6 and D5 is forward biased, forcing a current Rs ﬂowing into the self-basing loop. IO1 D5 IIN 4V BE(on) IO • Choose Rx so that, in State A, Rx V x D4 Q2 = ≥ I Vx IINRx 2VBE(on) D3 O2

D2 Q1 Q5 Thus, D5 is reversed biased and the start- D1 R up circuit won’t disturb the self-biasing loop when in State A. VEE

• The start-up circuit may also introduce additional bias points.

Voltage and Current References 9-11 Analog ICs; Jieh-Tsorng Wu Self-Biasing BJT UT Reference

VCC

Q4 IO Q3 Q6 I I ≈ I · S3 IN O I IO2 S4 I IN IO I I U ln IN = U ln O + I R A T T O IO1 IS1 IS2 Q2 Q1 Q5 I IN R V = − BE TCI TCU TCR B O T VEE I I I I ∆V = − = IN · S2 = S3 · S2 = BE ∆VBE VBE1 VBE2 UT ln UT ln IO IO IS1 IS4 IS1 R

• The UT reference is a proportional-to-absolute-temperature (PTAT) circuit.

• A start-up circuit is required to avoid the “zero-current” state.

Voltage and Current References 9-12 Analog ICs; Jieh-Tsorng Wu Self-Biasing MOST Vt Referenced Current Source

VDD

M4 M12 M3 M6 IO1 2IIN I I V = IN O ov1 k (W/L)1 M2 IO2 2I M13 M5 = O Vov2 M11 M1 k(W/L) R 2

Start-Up + 2IIN Vt1 I (W/L) V V + V k (W/L)1 V IN = 3 = GS1 = t1 ov1 = ≈ t1 IO IO (W/L)4 R R R R

Voltage and Current References 9-13 Analog ICs; Jieh-Tsorng Wu Self-Biasing MOST gm Referenced Current Source

VDD VDD = M4 M4 k µnCox M3 M6 M3 M6 I I (W/L) O1 O1 α ≡ 2 > 1 IIN IO IIN IO (W/L)1 ∆V = I · R IO2 R M2 V M1 M5 M2 IO2 Let M3=M4, then V R M1 M5 = = IIN IO I

√ 1 W 1 W α = 2 = − 2 ⇒ = √ · I k Vov1 k (Vov1 ∆V ) Vov1 ∆V 2 L 1 2 L 2 α − 1 √ √ √ ∆V 2( α − 1)2 1 2I ∆V 2( α − 1) 2 α − 1 I = = g = = · √ = √ α 2 m1 R k (W/L)1R Vov1 R α∆V R α

Voltage and Current References 9-14 Analog ICs; Jieh-Tsorng Wu Self-Biasing MOST VBE and UT Referenced Current Source

V Reference U Reference VDD BE VDD T

M4 M4 M3 M6 M3 M6

IIN IO IIN IO

M1 M2M1 M2

Q1 V R V R

Q1 Q2

I (W/L) = = S2 · 3 ∆V VBE1 ∆V UT ln IS1 (W/L)4

Voltage and Current References 9-15 Analog ICs; Jieh-Tsorng Wu Band-Gap References

VBE

= + VO VBE KUT · PTAT K UT Generator

◦ ◦ • = = = = = UT kT/q 26 mV at T 300 K. ∂UT /∂T k/q 0.087 mV/ C.

◦ ◦ • = = ≈− VBE 600 mV at T 300 K. ∂VBE /∂T 2mV/ C.

◦ • = = ≈ Want K 23 so that ∂Vo/∂T 0 at 300 K and VO 1.2V.

Voltage and Current References 9-16 Analog ICs; Jieh-Tsorng Wu Band-Gap References

For a BJT biased in the forward-active region, we have T J = − T + T + 0 + C = kT VBE VG0 1 VBE0 mUT ln UT ln UT T0 T0 T JC0 q

◦ ≈ VG0 Bandgap voltage of Si extrapolated to 0 K( 1.206 V) k Boltzmann’s constant m Constant (≈ 2.3)

T0 Reference temperature = JC Collector current density ( IC/A E ) JC0 Collector current density at T0 Let J α = + C = T VO VBE KUT and JC0 T0 We have T = + T − + − 0 + · VO VG0 (VBE0 VG0) (m α)UT ln K UT T0 T

Voltage and Current References 9-17 Analog ICs; Jieh-Tsorng Wu Band-Gap References

Then ∂V T O = 1 − + − k 0 − + · k (VBE0 VG0) (m α) ln 1 K ∂T T0 q T q = = Set ∂VO/∂T 0atT T0, we obtain

1 kT K = · V + (m − α)U − V U = 0 U G0 T 0 BE0 T 0 q T 0 T ∂V k T V = V + U (m − α) 1 + ln 0 O = (m − α)ln 0 O G0 T T ∂T q T

• = At T T0, ∂V V = V + U (m − α) O = 0 O G0 T 0 ∂T ◦ • = = If T0 300 K and α 1, then, 1.24 − V K = BE0 and V = 1.24 V at T = T 0.0258 O 0

Voltage and Current References 9-18 Analog ICs; Jieh-Tsorng Wu Kujik Band-Gap References

VCC

R1 R2 R1 R2 VO I1 I2 I1 I2

∆VBE R3∆VBE R3 VO

Q1 Q2 Q1 Q2

VEE VEE I R R I I R I 1 = 2 V = 2∆V ∆V = U ln 1 · S2 = U ln 2 · S2 I R R2 R BE BE T I I T R I 2 1 3 2 S1 1 S1 R R R I = | | + = | | + 2 = | | + × 2 2 · S2 VO VBE1 VR2 VBE1 ∆VBE VBE1 UT ln R3 R3 R1 IS1

Voltage and Current References 9-19 Analog ICs; Jieh-Tsorng Wu Kujik Band-Gap References

• Both IC1 and IC2 are proportional to T .

• In n-well CMOS technologies, use vertical pnp BJTs with with collectors tied to VSS.

• Reference: Kujik, JSSC 6/73, pp. 222Ð226.

ﬀ Let VOS be the opamp’s input o set voltage.

R1 R2 = | |−| | + = + V VR3 VBE1 VBE2 VOS ∆VBE VOS I1 I2 OS R R = 2 = 2 + VR2 VR3 (∆VBE VOS) R3 R3 V = |V | + V + V O BE1 OS R2 R3 V R R O = | | + 2 + + 2 VBE1 ∆VBE 1 VOS Q1 Q2 R3 R3

• ∼ VEE The ratio R2/R3 is typically 5 10.

Voltage and Current References 9-20 Analog ICs; Jieh-Tsorng Wu Ahuja Band-gap Reference

VDD

M1 M2 M3 M4 M5 M6 M12

M7 M8 M9 M10 M11

Cc R2

R3 VO

Q1 Q6 V Q2 BE Q5 Q3 Q4

VSS

Voltage and Current References 9-21 Analog ICs; Jieh-Tsorng Wu Ahuja Band-gap Reference

R R = | | + 2 + + 2 VO 3 VBE 3 ∆VBE 1 VOS R3 R3

• Increase number of VBE to suppress the contribution from VOS.

• Opamp doesn’t need to drive resistive load.

• Cc provides a feedforward path for negative feedback to ensure stability.

• Cascode current sources for better current matching.

• M12 is added for auto start-up to avoid the zero-current state.

• Reference: Ahuja, JSSC 12/84, pp. 892Ð899.

Voltage and Current References 9-22 Analog ICs; Jieh-Tsorng Wu Brokaw Band-Gap References

VCC VCC

Q3 Q4 R1 R2 I1 I2 1 I I 1 2 V o2 V o1 R11 Rx VEE Q1 Q1 VEE Q2 Q2 R12 R3 R3 ∆VBE ∆VBE VEE

R4 R4 VEE VEE I R ∆V I I →∞ ⇒ 1 = 2 = BE = 1 · S2 βF I2 ∆VBE UT ln I2 R1 R3 I2 IS1

Voltage and Current References 9-23 Analog ICs; Jieh-Tsorng Wu Brokaw Band-Gap References

The output voltages are ∆V I V = V + (I + I )R = V + BE 1 + 1 R O1 BE1 1 2 4 BE1 R I 4 3 2 R R R I = + × 4 2 + 2 · S2 VBE1 UT 1 ln R3 R1 R1 IS1

R R I I I = + 11 + 4 1 + 1 · S2 VO2 1 VBE1 UT 1 ln R12 R3 I2 I2 IS1

• Both I1 and I2 are proportional to T . • The resistor R = R3 R R is added to cancel the eﬀects of the ﬁnite base x R4 11 12 currents going through R11.

• Reference: Brokaw, JSSC 12/74, pp. 388Ð393.

Voltage and Current References 9-24 Analog ICs; Jieh-Tsorng Wu Widlar Band-Gap Reference

VCC I I →∞ 1 = 3 = βF VBE1 VBE3 I3 IS1 IS3

Q4 I R I I R I 1 = 2 = 1 S2 = 2 S2 ∆VBE UT ln UT ln I I I2 R1 I2 IS1 R1 IS1 2 R2 1 R1 Vo

VEE Q3 Q2 Q1 R = + 2 VO VBE1 ∆VBE R3 ∆V BE R3 R R I = + × 2 2 · S2 VBE1 UT ln VEE R3 R1 IS1

• Both I1 and I2 are proportional to T . I3 can be mirrored from a separate PTAT source.

• In the simplest form, I3 can be implemented with a resistor.

Voltage and Current References 9-25 Analog ICs; Jieh-Tsorng Wu Song Band-Gap Reference

VDD

M3 M5 M4

M6 M8 M6 I o V M9 M10 o M11

M1 M2

R = y R V y R R x Q1 Q2 Q3

VSS

Voltage and Current References 9-26 Analog ICs; Jieh-Tsorng Wu Song Band-Gap Reference

= = = = Let Q2 Q3, IS2/IS1 n, and M3 M4 M5, then

= ∆V UT ln(n)

The output voltage, VO, and current, IO, are thus

V = + · = O VO VBE3 UT y ln(n) and IO Rx • A PTAT current from M8 develops a UT -dependent voltage across resistor Ry .A proper choice of the ratio y can give a band-gap voltage at VO.

• All currents are proportional to T .

• If desired, a temperature-independent output current can be realized by choosing y

to give an appropriate TC to VO to cancel the TC of resistor R2.

• Reference: Song, et al., JSSC 12/83, pp. 634Ð643.

Voltage and Current References 9-27 Analog ICs; Jieh-Tsorng Wu Band-Gap Reference Output Issues

V Reference O Generator C L

V Reference O RG RG Generator V’O

RG VO VO Reference R Generator RG RG

Voltage and Current References 9-28 Analog ICs; Jieh-Tsorng Wu Band-Gap Reference Output Issues

• Feedback is employed in the reference generator. Loop stability must be ensured.

• The stability can be tested by observing the output step response.

• Capacitive loading at the output of reference generator has to be either extremely large (i.e., oﬀ-chip capacitors, undesirable because of extra pin, lead inductance, ...) or very small (not easy to accomplish).

• Can use buﬀers to reduce the output loading. But additional oﬀset and drift are introduced.

• One possible scheme is using separate generators for diﬀerent parts of system so as to isolate more sensitive circuits from other ones. However, mismatch among generators, area, power, and trimming cost must be considered.

Voltage and Current References 9-29 Analog ICs; Jieh-Tsorng Wu Output Stages

Jieh-Tsorng Wu

December 5, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Output Stage Requirements

Io Io Vo Vo Vi Output Vi Output Stage Stage RL CL RL CL

• Deliver large output current to low-impedance loads (resistive and/or capacitive).

• ﬀ Usually is a voltage bu er, i.e., low voltage gain, high Zin, and low Zo.

• High Zin is to maintain voltage gain and bandwidth of previous stage.

• Wide bandwidth if in the feedback loop,

• May need protection against load shorts.

Output Stages 10-2 Analog ICs; Jieh-Tsorng Wu Output Stage Design Issues

• Frequency response.

• Output impedance.

• Output current.

• Output voltage range.

• Power eﬃciency.

• Distortion.

Output Stages 10-3 Analog ICs; Jieh-Tsorng Wu Nonlinearity and Harmonic Distortion

For a nonlinear system with input x, the output y can be expressed as:

= + + 2 + 3 + ··· y a0 a1x a2x a3x

With a pure sinusoidal input x = vˆ cos ωt,

= + + 2 2 + 3 3 + ··· y a0 a1vˆ cos ωt a2vˆ cos ωt a3vˆ sin ωt a vˆ2 a vˆ3 = a + a vˆ cos ωt + 2 (1 + cos 2ωt) + 3 (3 cos ωt + cos 3ωt) + ··· 0 1 2 4 = + + + + ··· b0 b1 cos ωt b2 cos 2ωt b3 cos 3ωt where 1 3 b = a + a vˆ2 + ··· b = a vˆ + a vˆ3 + ··· 0 0 2 2 1 1 4 3 1 1 b = a vˆ2 + ··· b = a vˆ3 + ··· 2 2 2 3 4 3

Output Stages 10-4 Analog ICs; Jieh-Tsorng Wu Nonlinearity and Harmonic Distortion

The harmonic distortion factors are b2 1a2 HD ≡ ≈ · vˆ 2 b 2a 1 1 b a ≡ 3 ≈ 1 3 · 2 HD3 vˆ b1 4a1

The total harmonic distortion (THD) is 2 + 2 + ··· b2 b3 THD = b1

The SINAD is the ratio of signal plus noise plus distortion powers to noise and distortion powers, i.e, S + N + D SINAD = N + D

Output Stages 10-5 Analog ICs; Jieh-Tsorng Wu Class-A BJT Emitter Follower

VCC

Vi Q1 Io Vo IQ R3 RL Q2

R1 R2

VCC I V I + V /R = c1 = + o ⇒ = + = + Q o L Vbe1 UT ln Ic1 IQ Vi Vo Vbe1 Vo UT ln IS1 RL IS1

Output Stages 10-6 Analog ICs; Jieh-Tsorng Wu Class-A BJT Emitter Follower Output Power

= − − Vce1 VCC (Ic1 IQ)RL ˆ ˆ For a sinusoidal Vo with amplitudes Vo and Io,

1 Average Output Power = P = Vˆ Iˆ L 2 o o = = Average Supply Power Psupply 2VCCIQ

Maximum output swing and output power are

ˆ = − = · ˆ = Vom VCC VCE(sat) IQ RL Iom IQ 1 1 P = Vˆ Iˆ = V − V I L(max) 2 om om 2 CC CE(sat) Q P V ﬃ = = L = 1 − CE(sat) ≤ 1 Power Conversion E ciency ηC ηC(max) 1 Psupply 4 VCC 4

Output Stages 10-7 Analog ICs; Jieh-Tsorng Wu Instantaneous Power Dissipation

Q1 Instantaneous Power Dissipation is

= Pc1 Vce1Ic1

At maximum ηC,

= + × − Pc1 VCC(1 sin ωt) IQ(1 sin ωt) V I = CC Q (1 + cos 2ωt) 2

• The maximum Pc1 occurs at the midpoint of any load line.

Output Stages 10-8 Analog ICs; Jieh-Tsorng Wu Class-A MOST Source Follower

VDD

Vi M1 Io Vo IQ RL M2

VDD

V I = I + o V = V + V = V + V + V d1 Q R i o gs1 o t1 ov1 L + 2 IQ Vo/RL ⇒ V = V + V + γ 2φ + V + V − 2φ + i o t0 f o DD f k (W/L)1

Output Stages 10-9 Analog ICs; Jieh-Tsorng Wu Distortion in the MOST Source Follower

= Since Vi f (Vo), we have

∞ ∞ 1 V = V + v = b (v )n v = V − V b = f (n)(V ) ⇒ v = b (v )n i I i n o o o O n n! O i n o n=0 n=1

To ﬁnd

∞ = n vo an(vi ) n=1 use ∞ ∞ ∞ n = n = m vi bn(vo) bn am(vi ) n=1 n=1 m=1 = + + 2 2 + + + 3 3 + ··· b1a1vi (b1a2 b2a1)vi (b1a3 2b2a1a2 b3a1)vi

Output Stages 10-10 Analog ICs; Jieh-Tsorng Wu Distortion in the MOST Source Follower

Matching coeﬃcients, we obtain

2 1 b 2b b a = a = − 2 a = 2 − 3 1 b 2 3 3 5 4 1 b1 b1 b1

• →∞ = + + = Assume RL , and let VM VO VDD 2φf , vi vˆi sin ωt, then

−3 2 −5 2 γ V / γ V / = 1 = 8 M = − 16 M a1 a2 a3 −1 2 3 5 1 + γ V / + γ −1/2 + γ −1/2 2 M 1 2VM 1 2VM

−3/2 a V = 1 2 · = γ M · HD2 vˆi vˆi 2a 16 − 2 1 + γ 1/2 1 2VM

−5/2 a V = 1 3 · 2 = − γ M · 2 HD3 vˆ vˆ 4a i 64 − 4 i 1 + γ 1/2 1 2VM

Output Stages 10-11 Analog ICs; Jieh-Tsorng Wu Class-A BJT Common-Emitter Stage VCC

R1 R2

R3 IQ Io Vo

RL V i Q1 = − ⇒ = = − Vi /UT Io IQ Ic1 Vo IoRL IQ ISe RL VCC

Same output power, ηC, and Pc1 as the class-A emitter followers, since

= − − Vce1 VCC (Ic1 IQ)RL

Output Stages 10-12 Analog ICs; Jieh-Tsorng Wu Distortion in Class-A BJT Common-Emitter Stage

Assume the input is = + = VBE1/UT Vi VBE1 vi IQ ISe Then, the output voltage is + = − (VBE1 vi )/UT − = − vi /UT − Vo RL ISe IQ RLIQ e 1 v v 2 v 3 = − i + 1 i + 1 i + ··· = + 2 + 3 + ··· RLIQ a1vi a2vi a3vi UT 2 UT 6 UT

= Let vi vˆi sin ωt, then the harmonic distortion factors are

a vˆ = 1 2 · = 1 i HD2 vˆi 2a1 4UT 1a 1 vˆ 2 = 3 · ˆ 2 = i HD3 vi 4a1 24 UT

Output Stages 10-13 Analog ICs; Jieh-Tsorng Wu Class-A MOST Common-Source Stage

= = − VDD Vo IoRL (IQ Id1) RL = 1 W − 2 = 1 − 2 Id1 µCox (Vi Vt) k(Vi Vt) M2 2 L 2 IQ = + = + = 2 Let Vi VI vi , VI Vov Vt and IQ (1/2)kVov Io 1 Vo V = R (I − I ) = R I − k(V + v )2 o L Q d L Q 2 ov i V i M1 RL v v 2 = − i + i RLIQ 2 VDD Vov Vov

= Let vi vˆi sin ωt, then the harmonic distortion factors are a v = 1 2 · = 1 i = HD2 vˆi HD3 0 2a1 4 Vov

Output Stages 10-14 Analog ICs; Jieh-Tsorng Wu Class-B Push-Pull Emitter Follower

VCC

Q1 Io Vi Vo

RL Q2

VCC

Output Stages 10-15 Analog ICs; Jieh-Tsorng Wu Output Power of Class-B Push-Pull Emitter Follower

For a sinusoidal output

= ˆ = = ˆ Vo Vo sin ωt Io Vo/RL Io sin ωt

We have

Vˆ 2 = 1 ˆ ˆ = 1 o PL VoIo 2 2RL T/2 Vˆ = 1 = 2 o = 2 ˆ Isupply Ic1(t)dt Io T/2 0 π RL π 2 V P = V I = CC · Vˆ = − supply CC supply π R o Vce1 VCC Ic1RL L

Vˆ ﬃ = = π o ≤ π Power Conversion E ciency ηC 4 VCC 4

Output Stages 10-16 Analog ICs; Jieh-Tsorng Wu Class-AB Push-Pull Emitter Followers

VCC VCC

VCC IB1 IB1

Q1 Q1 Q1

VB1 Q3 Q3

V1 IQ Vo V1 IQ1 Vo Q4 IQ2 Vo

VB2 Q4 R1

Q2 Q2 Q2

VEE Vi Q5 Vi Q5

VEE VEE I I I I + | | = + | |⇒ = S1 S2 = S1 S2 VBE1 VBE2 VBE3 VBE4 IQ1 IB1 IQ2 IC3IC4 IS3IS4 IS3IS4

Output Stages 10-17 Analog ICs; Jieh-Tsorng Wu Class-AB Push-Pull Source Followers

VDD VDD

IB1 Vi M5 M6 M1

M3 M3 M1

V I V 1 Q1 o V V 1 IQ2 o M4 Q2 M2 Q4 V i M5 IB1

VSS VSS

 2 + 1/ kn(W/L)3 1/ kp(W/L)4  + | | = + | |⇒ = VGS1 VGS2 VGS3 VGS4 IQ1 IB1   + 1/ kn(W/L)1 1/ kp(W/L)2

Output Stages 10-18 Analog ICs; Jieh-Tsorng Wu Class-AB Push-Pull Common-Source Stage

VDD

VDD 2IB1 M11 IB3

IB M12

V2 M1 V 2 M1

M3 V bop R1 IQ Vo IQ V o M4 V bon

V1 M2 V1 M2

Vi M5 M14

VSS Vi M5 IB2 M13

VSS

Output Stages 10-19 Analog ICs; Jieh-Tsorng Wu Class-AB Push-Pull Common-Source Stage

= = Let IB1 IB2 IB3, and 1 W = W W = W 1 W = W W = W K L 1 L 11 L 3 L 12 K L 2 L 13 L 4 L 14

= = = = Then, VGS1 VGS11, VGS3 VGS12, VGS2 VGS13, VGS4 VGS14, and

= = = · IQ ID1 ID2 K IB1

• M3 and M4 form a ﬂoating resistor.

• Large output impedance. The pole at Vo can be signiﬁcant.

• Large distortion. Usually this output stage is included in the feedback loop.

Output Stages 10-20 Analog ICs; Jieh-Tsorng Wu Class-AB Quasi-Complementary Conﬁguration

VDD gm1v gs1 EP EP M1 vgs1 g o1 Io io Vi Vo Vi vo

RL g v o2 ENM2 EN gs2 gm2vgs2 VSS

i = − o = + + + Go gm1AEP gm2AEN go1 go2 v = o vi 0

• The distortion and output resistance are reduced by AEP and AEN.

• Need to control IQ.

Output Stages 10-21 Analog ICs; Jieh-Tsorng Wu Class-AB Quasi-Complementary Conﬁguration

= = VDD AEP AEN A = − = EP M1 Vtn Vtp Vt VOSP W W W Io k = k = k p L n L L Vi Vo 1 2 1 W 2 RL I = − k (V + V ) d1 2 L gs1 t VOSN EN M2 = 1 W − 2 Id2 k (Vgs2 Vt) VSS 2 L = = = If Vi 0 and VOSP VOSN 0, let 2I − = = = Q = − − = + ID1 ID2 IQ Vov Vgs1 Vt Vov Vgs2 Vt Vov k(W/L)

Output Stages 10-22 Analog ICs; Jieh-Tsorng Wu Class-AB Quasi-Complementary Conﬁguration

We have

= − − + − − = + + − − Vgs1 Vt Vov A[Vo (Vi VOSP )] Vgs2 Vt Vov A[Vo (Vi VOSP )] + − VOSP VOSN V Vi I = o I + I + I = 0 ⇒ V = 2 o R o d1 d2 o + 1 L 1 − − k (W/L)A[2Vov A(VOSP VOSN)]RL • = = If VOSP VOSN 0,

V V W V = i = i g = k V o 1 1 m ov 1 + 1 + L k (W/L)A2Vov RL 2AgmRL

• − If A(VOSP VOSN) 2Vov and 2AgmRL 1,

+ + − VOSP VOSN − VOSP VOSN Vi Vi V + V V = 2 = 2 ≈ V − OSP OSN o 1 1 i 1 + 1 + 2 k (W/L)A2VovRL 2AgmRL

Output Stages 10-23 Analog ICs; Jieh-Tsorng Wu Class-AB Quasi-Complementary Conﬁguration

= To ﬁnd IQ when VOSP and VOSN exist, let Vi 0 and

V − V V − V V + V ≈ OSP OSN V + V ≈− OSP OSN o OSP 2 o OSN 2 1 W V − V 2 I = k V − A OSP OSN Q 2 L ov 2

= = = = − Deﬁne IQ0 IQ when VOSP VOSN 0, and ∆IQ IQ0 IQ, 1 W V − V ∆I = k A(V − V ) V − A OSP OSN Q 2 L OSP OSN ov 4 ∆I V − V V − V V − V Q = A OSP OSN 1 − A OSP OSN ≈ A OSP OSN IQ0 Vov 4Vov Vov

• Must keep A small to reduce IQ variation.

Output Stages 10-24 Analog ICs; Jieh-Tsorng Wu An Error Ampliﬁer Example

VDD Let

M17 M15 M16 (W/L) = (W/L) = (W/L) A 15 16 17 M1 = (W/L)13 (W/L)14 M14 M13 (W/L) ⇒ I = I × 1 VSS VSS Q(M1) SS I SS C1 (W/L)17 VSS = = − ID13 ID14 ISS IBB/2 Vi Vo M11 M12 Voltage gain is IBB g EP VSS = m11 AEP + gm14 gmb14

• Want large swing at node A to provide strong gate drive for M1.

• Reference: Khorramabadi, JSSC 4/92, pp. 539–544.

Output Stages 10-25 Analog ICs; Jieh-Tsorng Wu Combined Common-Drain Common-Source Conﬁguration

VDD

IB1 IB2 VOS M1 VDD

M3 EP M11

V1 Io Vo

M4 RL

M2 EN M12

Vi M5 Vi M6 VSS VOS

VSS

Output Stages 10-26 Analog ICs; Jieh-Tsorng Wu Combined Common-Drain Common-Source Conﬁguration

• ﬀ VOS can be introduced by intentionally mismatching the input di erential pair in each error ampliﬁer.

• = = ﬀ The circuit can be designed so that, when Vo V1 0, the introduction of VOS turn o M11 and M12.

• − − | | M11 is turned on only when V1 Vo VOS > Vtp /A EP .

• Error ampliﬁers, AEP and AEN, can have high gain, and are often designed as one- ≈ stage ampliﬁer with gain gmro.

• The wide bandwidth of M1 and M2 source followers simplify the design required to guarantee stability.

• The V1 voltage range, limited by Vgs3 and Vgs4, can be increased by adding the M6 common-source stage.

Output Stages 10-27 Analog ICs; Jieh-Tsorng Wu Parallel Common-Source Conﬁguration

EP1 VDD VDD VOS V3 V EP2 M1 2 M11 Io Vi Vo

RL M2 EN2 M12 V OS EN1 VSS VSS VDD VDD

IB2 M5 M6 IB2 V2 M21 M22

V2 V3 V2 V2

V1 M3 M4 V1 VB M23 M24 VB

M25 M26 IB1 EP1 Amplifier EP2 Amplifier VSS VSS

Output Stages 10-28 Analog ICs; Jieh-Tsorng Wu Parallel Common-Source Conﬁguration

• ﬀ ≈ = Want turn o M11 and M12 when Vo Vi 0, so that AEP2 and AEN2 have high gain, and AEP1 and AEN1 have low gain.

• ≈ = VOS of EP1 is introduced by making (W/L)3 0.8(W/L)4. When Vo Vi 0,

(W/L) (W/L) = · 3 = − · 1 ID3 IB1 ID1 (ID3 IB2) (W/L) + (W/L) (W/L) 3 4 3 g 3 k (W/L)3 I 3 A = m = n · · D A ≈ g r EP1 g − EP2 m22 o22 m5 kp (W/L)5 ID3 IB2

• | | When Vi is small, and M11 and M12 are not turned on, the output is

V V = i o + 1 1/(A1gm1RL)

Output Stages 10-29 Analog ICs; Jieh-Tsorng Wu Parallel Common-Source Conﬁguration

• When Vi is large, M11 can be turned on, and the output becomes

≈ − →∞ Vo Vi VOS if AEP2

• = = + + = + When V2+ V2− at EP2, deﬁne V3 Vov25 Vt25 VSS VK VSS. Then

= − − + + V3 [Vo (Vi VOS)]AEP1AEP2 VK VSS

= −| | Deﬁne Vi(min) as the minimum input to turn on M11. Let V3 VDD Vtp11 ,wehave

(V − V − V −|V |)(1 + A g R ) = + − DD SS K tp11 EP1 m1 L Vi(min) VOS(1 AEP1gm1RL) AEP1AEP2 = + →∞ Vi(min) VOS(1 AEP1gm1RL)ifAEP2

M11 and M12 remain oﬀ for only a small range of input voltages.

Output Stages 10-30 Analog ICs; Jieh-Tsorng Wu Noise Analysis and Modeling

Jieh-Tsorng Wu

December 5, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Noise in Time Domain

n(t) PDF

0 t

n 0

1 T 1 T Mean = n = n(t)dt = 0 Noise Power = n2 = n2(t)dt T 0 T 0 1/2 = = 2 Root Mean Square nrms n

• T is a suitable averaging time interval. Typically, a longer T gives a more accurate measurement.

Noise 11-2 Analog ICs; Jieh-Tsorng Wu Probability Density Function

• The probability that the noise lies between values n and n + dn at any time is given by P (n)dn. P (n) is the probability density function (PDF).

• The PDF of a random noise is usually Gaussian, i.e.,

2 1 − n P (n) = √ e 2σ2 2πσ

We have

+∞ PDF(n)dn = 1 −∞

and

+∞ Variance = n2 · PDF(n)dn = n2 = σ2 −∞

Noise 11-3 Analog ICs; Jieh-Tsorng Wu Noise in Frequency Domain

BPF n One-sided power spectral density f 2 Power n (f ) f = Meter SD(f ) lim ∆f →0 ∆f Spectral Density One-sided root spectral density V2 Hz RD(f ) = (SD)1/2 log f The total noise power is Root Spectral Density √V ∞ Hz = 2 SDn(f )df n 0

log f

Noise 11-4 Analog ICs; Jieh-Tsorng Wu Filtered Noise

n i H(s) n o SD (f ) = SD (f ) ×|H(j2πf )|2 no ni

If SD (f ) = N is a constant (white noise), then ni

∞ ∞ n2 = SD (f ) ·|H(j2πf )|2df = N · |H(j2πf )|2df = N · B o ni n 0 0

• Bn is called the noise bandwidth of the ﬁlter.

• = 1 For a single-pole ﬁlter H(s) + , 1 s/ωo

∞ ∞ 1 π B = |H(j2πf )|2df = df = · f n 2 2 o 0 0 1 + f fo

Noise 11-5 Analog ICs; Jieh-Tsorng Wu Noise Summation

n i1 H1 (s)

n i1 n n o1 i2 H2 (s) n o2

n i2 n i3 H3 (s)

· = If two noises, ni and nj , are uncorrelated then, i.e., ni nj 0. Then

2 = + 2 = 2 + 2 + · = 2 + 2 no1 (ni1 ni2) ni1 ni2 2 ni1ni2 ni1 ni2

SD (f ) = |H (j2πf )|2SD + |H (j2πf )|2SD + |H (j2πf )|2SD no2 1 ni1 2 ni2 3 ni3

Noise 11-6 Analog ICs; Jieh-Tsorng Wu Piecewise Integration of Noise

2 200

2 2 (nV) 20 Hz ∝ 1 f 2 2 f 0 1 2 3 4567 10 10 10 10 10 10 10 10

N1 N2 N3 N4

The noise power in each frequency region is

102 2 200 2 P = df = 2002 ln(f )|10 = 1.84 × 105 (nV)2 N1 100 100 f

3 10 3 P = 202df = 202 f |10 = 3.6 × 105 (nV)2 N2 102 102

Noise 11-7 Analog ICs; Jieh-Tsorng Wu Piecewise Integration of Noise

4 4 10 20 2 20 2 1 10 P = f 2df = f 3 = 1.33 × 108 (nV)2 N3 3 3 103 10 10 3 103

4 ∞ 2002 ∞ 2002 10 P = = df − 2002df N4 4 2 2 10 1 + f 0 1 + f 0 105 105 π = 2002 105 − 2002 · 104 = 5.88 × 109 (nV)2 2

Total rms of the noise is

1/2 n = P + P + P + P = 77.5 µVrms rms N1 N2 N3 N4

• 1/f noise tangent principle: Lower a 1/f line until it touches the spectral density curve; the total noise can be approximated by the noise in the vicinity of the 1/f line.

Noise 11-8 Analog ICs; Jieh-Tsorng Wu Thermal Noise

R R R i 2 v 2

v 2 i 2 1 = 4kTR = 4kT f = 0 ∼∞ ∆f ∆f R

T = Absolute Temperature in Kelvins k = 1.38 × 10−23 watt/K-Hz (Boltzmann’s Constant) ∆f = Bandwidth per Hertz

• Thermal noise is a white noise, i.e., its power spectral density v2/∆f is independent of frequency, and its amplitude distribution is Gaussian.

◦ √ • Fora1kΩ resistor at 300 K, v 2/∆f ≈ (4 nV/ Hz)2.

Noise 11-9 Analog ICs; Jieh-Tsorng Wu Thermal Noise with Loading

2 vo P n R R C R v 2 L v 2

• = The RL load receives the maximum power if RL R. Thus the available noise power for RL is 1 P = · v 2 · B = kTB B = Noise Bandwidth n 4R n n n • For the RC low-pass network

π 1 1 1 kT B = · = v 2 = 4kTR · = n 2 2πRC 4RC o 4RC C

◦ = = 2 = 2 If C 1pFandT 300 K, vo (64 µV)

Noise 11-10 Analog ICs; Jieh-Tsorng Wu Shot Noise

ID r d i 2

2 = kT i = = ∼∞ rd 2qID f 0 qID ∆f

q = 1.6 × 10−19 C (Electronic Charge) = ≈ = ◦ kT/q UT 26 mV at T 300 K

• Shot noise is also a white noise.

• The shot noise from a diode with 50 µA bias current is the same as the thermal noise from a 1 kΩ resistor at room temperature.

Noise 11-11 Analog ICs; Jieh-Tsorng Wu Flicker Noise (1/f Noise)

• Flicker noise, which is always associated with a ﬂow of direct current, displays a spectral density of the form

i 2 Ia = K f = 0 ∼∞ ∆f 1f b ≈ ∼ ≈ = a 0.5 2 b 1 K1 a constant for a particular device

• The ﬂicker noise’s power spectral density is frequency dependent, and its amplitude distribution is non-Gaussian.

• Flicker noise is caused mainly by traps associated with contamination and crystal

defects. The constant K1 can varies widely even for devices from the same wafer.

Noise 11-12 Analog ICs; Jieh-Tsorng Wu BJT Noise Model 2 vb r Cµ r B b B c C

C 2 cs i v 2 b 1 r C r i π π gmv1 o c

v 2 i 2 i 2 Ia b = 4kTr c = 2qI b = 2qI + K B ∆f b ∆f C ∆f B 1 f

• All noise sources are independent of each other.

• The thermal noise of rc is neglected.

• Avalanche noise is found to be negligible if VCE is kept at least 5 V below BVCEO.

• Cµ can be neglected in noise calculation.

Noise 11-13 Analog ICs; Jieh-Tsorng Wu FET Noise Model

Cgd G D

2 v1 C 2 ig gs r i gmv1 o d

2 2 a ig 16 i I = 2qI + kTω2C2 d = 4kT (γg ) + K D ∆f G 15 gs ∆f d0 1 f

• Since the channel material is resistive, it exhibits thermal noise. γ is a constant, gd0 = is the channel conductance at VDS 0.

2 γ ≈ g ≈ g 3 d0 m

Noise 11-14 Analog ICs; Jieh-Tsorng Wu FET Noise Model

• For short-channel device (L<1 µm), the thermal noise is 2 to 5 times larger than

4kT(2/3)gm.

• 2 2 The gate-current noise, (16/15)kTω Cgs, is usually insigniﬁcant at low frequencies. Its correlation with the thermal noise is 0.39.

• IG is the gate leakage current.

• Cgd can be neglected in noise calculation.

• The 1/f noise in the surface devices, such as MESFETs and MOSFETs, is usually larger than that of BJTs.

• pMOSTs have less 1/f noise than nMOSTs, since holes are less likely to be trapped.

Noise 11-15 Analog ICs; Jieh-Tsorng Wu Equivalent Input Noise Generators

2 vi

Noisy Noiseless R R 2 S NetworkS ii Network

• 2 The noise in network is lumped and represented by a noise voltage generator vi and 2 a noise current generator ii . This representation is valid for any source impedance, if correlation between the noise generators is considered.

• And the total input equivalent noise can be found by

= + + 2 = 2 + 2 + 2 2 viN vs vi ii RS and viN vs vi ii RS

Noise 11-16 Analog ICs; Jieh-Tsorng Wu Equivalent Input Noise Generators

• In most practical circuits, the correlation between vi and ii is small and may be 2 2 neglected. If either vi or ii dominates, the correlation may be neglected in any case.

• 2 The value of vi can be found by shorting the input ports and equating the output noise in each case.

• 2 The value of ii can be found by opening the input ports and equating the output noise in each case.

Noise 11-17 Analog ICs; Jieh-Tsorng Wu Noise Factor and Input Noise Generators

2 2 vs vi

Noiseless R 2 S ii Network

2 vs is the thermal noise of RS, i.e.,

2 = vs 4kTRS∆f

2 2 Assume no correlation between vi and ii ,wehave

2 N v 2 + i 2R a = i i S Ni 2 vs

Noise 11-18 Analog ICs; Jieh-Tsorng Wu Noise Factor and Input Noise Generators

Thus, the noise factor for the two-port network is

2 2 SNR S /N N v i RS F = in = i i = 1 + a = 1 + i + i · · + 4 4 SNRout (G Si )/[G (Ni Na)] Ni kTRS∆f kT∆f

• 2 2 For small RS, vi dominates, whereas for large RS, ii dominates.

• There exits an optimal RS for minimum F :

v 2 i 2R 2 = i = + i S RS,opt and Fopt 1 2 2kT∆f ii

This is one reason for the widespread use of transformers at the input of low-noise tuned ampliﬁers.

Noise 11-19 Analog ICs; Jieh-Tsorng Wu Noise Generators of a BJT Common-Emitter Stage

2 vb rb

2 i 2 i b v1 r C i o π π gmv1 c

2 vi rb

2 i i v1 r C o i π π gmv1

v 2 i 2 Ia i 2 b = 4kTr b = 2qI + K B c = 2qI ∆f b ∆f B 1 f ∆f C

Noise 11-20 Analog ICs; Jieh-Tsorng Wu Noise Voltage Generator of a BJT Common-Emitter Stage

By shorting the input ports, we obtain

= + = io gmvb ic gmvi

2 Since rb is small, ib is neglected. We have

i i 2 v = v + c v 2 = v 2 + c i b g i b 2 m gm

2 v 2qI I /U 1 i = 4kTr + C = 4kT r + C T = 4kT r + = 4kTR ∆f b 2 b 2 b 2g eq gm 2gm m = = + 1 Req Equivalent Input Noise Resistance rb 2gm

Noise 11-21 Analog ICs; Jieh-Tsorng Wu Noise Current Generator of a BJT Common-Emitter Stage

By opening the input ports, we obtain

i i 2 i = β(jω)i + i = β(jω)i ⇒ i = i + c i 2 = i 2 + c o b c i i b β(jω) i b |β(jω)|2

Thus

i 2 Ia I K i = 2q I + K B + C = 2qI K = 1 ∆f B 1 f |β(jω)|2 eq 1 2q Ia I I = Equivalent Input Shot Noise Current = I + K B + C eq B 1 f |β(jω)|2 β β β = o = o = o β(jω) ω + 1 + j 1 + j f β Cπ Cµ ωβ f o 1 + β jω T o gm

Noise 11-22 Analog ICs; Jieh-Tsorng Wu BJT Equivalent Input Shot Noise Spectral Density

i2 f 2 i 1/f log ∆f

log f f a f b

At high frequencies I I f 2 f 2 C = C 1 + β2 ≈ I | |2 2 2 o C 2 β(jω) βo f f T T f 2 I f Let I = I b ⇒ f = f B = T B C 2 b T I fT C βF

Noise 11-23 Analog ICs; Jieh-Tsorng Wu Total Equivalent Noise Voltage of a BJT Common-Emitter Stage

The total equivalent noise voltage with a source resistance RS can be found as

v 2 v 2 v 2 i 2 iN = s + i + i 2 RS ∆f ∆f ∆f ∆f a 1 I I = 4kT R + r + + R2 · 2q I + K B + C S b S B 1 2 2gm f |β(jω)| 2 a 1 R I I = 4kT R + r + + S I + K B + C S b B 1 2 2gm 2UT f |β(jω)| a 2U 1 I I = 2qR2 T R + r + + I + K B + C S 2 S b 2g B 1 f |β(jω)|2 RS m

Noise 11-24 Analog ICs; Jieh-Tsorng Wu Noise Generators of a FET Common-Source Stage

v 2 1 C 2 io ig gs r i gmv1 o d

2 vi

2 v1 i i Cgs r o i gmv1 o

2 2 a ig 16 i I = 2qI + kTω2C2 d = 4kT (γg ) + K D ∆f G 15 gs ∆f d0 1 f

Noise 11-25 Analog ICs; Jieh-Tsorng Wu Noise Voltage Generator of a FET Common-Source Stage

By shorting the input ports, we obtain

i 2 i = i = g v ⇒ v 2 = d o d m i i 2 gm

v 2 g Ia K i = 4kTγ d0 + K D = 4kTR K = 1 ∆f 2 1 2 eq 1 4kT gm gmf a a g I 2 1 I R = Equivalent Input Noise Resistance = γ d0 + K D ≈ + K D eq 2 1 2 3g 1 2 gm gmf m gmf

• For MOST, its voltage generator for ﬂicker noise is approximately independent of bias current and voltage and is inversely proportional to the gate-oxide capacitance, i.e.,

v 2 K i ≈ 2 1 + f · 1 ∼ × −24 2 4kT Kf 3 10 V -F ∆f 3gm WLCox f

Noise 11-26 Analog ICs; Jieh-Tsorng Wu MOST Equivalent Input Noise Voltage Spectral Density

v2 i log ∆f 1/f

log f f a

• At frequencies above the ﬂicker noise region, the Req of a FET is signiﬁcantly higher than that of a BJT at a comparable bias current.

• For a MOST, it is not uncommon for the fa to extend well into the MHz region.

Noise 11-27 Analog ICs; Jieh-Tsorng Wu Noise Current Generator of a FET Common-Source Stage

By opening the input ports, we obtain

2 2 g g jωCgs ω Cgs i = i m + i = i m ⇒ i = i + i i 2 = i 2 + i 2 o g jωC d i jωC i g g d i g 2 d gs gs m gm 2 2 2 a i 16 ω Cgs I i = 2qI + kTω2C2 + 4kTγg + K D = 2qI + ω2C2 (4kTR ) ∆f G 15 gs 2 d0 1 f G gs eq gm a a g K I 4 2 1 K I 4 R = γ d0 + 1 · D + ≈ + 1 · D + eq 2 2 f 15 3g 2 f 15 gm 4kTgm m gm

• 2 When the source impedance is large, ii dominates. Since Ig is very small, FETs have noise performance much superior to that of BJTs. However, for low source 2 impedances where vi dominates, BJTs often have noise performance superior to that of FETs.

Noise 11-28 Analog ICs; Jieh-Tsorng Wu Noise Factor of a BJT Common-Emitter Stage

Neglecting ﬂicker noise,

2 2 v 1 i I I I i = 4kT r + i = 2q I + C = 2q C + C b B 2 2 ∆f 2gm ∆f |β(jω)| βF |β(jω)|

The noise factor is

v 2 i 2 F = 1 + i + i 4kTR ∆f 1 S 4kT R ∆f S 1 1 g g = 1 + r + + R m + m b S 2 RS 2gm 2βF 2|β(jω)| 1 1 g g ω 2 = 1 + r + + R m + m 1 + β2 R b 2g S 2β 2 o ω S m F 2βo T

Noise 11-29 Analog ICs; Jieh-Tsorng Wu Noise Factor of a BJT Common-Emitter Stage

For high-frequency circuits, if ω/ωT 1/βo and ω/ωT 1/βF , g 2 ≈ + 1 · + 1 + · m · ω F 1 rb RS RS 2gm 2 ωT

• For ﬁxed RS and ωT ,

ω r = 1 · T = + b + ω gm,opt Fopt 1 RS ω Rs ωT

• For ﬁxed gm and ωT ,

2r 1 ω ω R = b + · T F = 1 + 2r g + 1 · S,opt g 2 ω opt b m ω m gm T

Noise 11-30 Analog ICs; Jieh-Tsorng Wu Noise Factor of a BJT Common-Emitter Stage

For low-frequency circuits, if ω/ωT 1/βo and ω/ωT 1/βF , 1 1 g 1 1 F ≈ 1 + · r + + R · m · + b S 2 RS 2gm 2 βF β o g ≈ + 1 · + 1 + · m · 1 1 rb RS RS 2gm 2 βF • For ﬁxed RS and βF ,

1 r 1 g = · β F = 1 + b + m,opt R F opt R S s βF

• For ﬁxed gm and βF ,

2r 1 1 R = b + · β F = 1 + 2r g + 1 · S,opt g 2 F opt b m m gm βF

Noise 11-31 Analog ICs; Jieh-Tsorng Wu Noise Factor of an FET Common-Source Stage

Neglecting ﬂicker noise, IG, and gate-current noise,

2 2 v 1 i 1 i = 4kTγg · i = ω2C2 · 4kTγg · ∆f d0 2 ∆f gs d0 2 gm gm

The noise factor is

v 2 i 2 F = 1 + i + i 1 4kTRS∆f 4kT ∆f RS 1 γg γg = 1 + · d0 + R · ω2C2 · d0 R 2 S gs 2 S gm gm

Noise 11-32 Analog ICs; Jieh-Tsorng Wu Noise Factor of an FET Common-Source Stage

For low-frequency circuits, ωCgs 1/RS,

1 γg F ≈ 1 + · d0 R 2 S gm

• →∞ → For ﬁxed RS, gm,opt and Fopt 1

• →∞ → For ﬁxed gm, RS,opt and Fopt 1

• Ω For RS of the order of M or higher, the FET usually has signiﬁcantly lower noise ﬁgure than a BJT.

For high-frequency circuits, ωCgs 1/RS, γg ω 2 F ≈ 1 + R · ω2C2 · d0 ≈ 1 + R · γg · S gs 2 S d0 ω gm T

Noise 11-33 Analog ICs; Jieh-Tsorng Wu Noise Performance of Other Conﬁgurations

Common−Base Stage 2 vi

2 2 i 2 v i ii i

Emitter Follower 2 2 vi vi

2 2 ii ii zL zL

Noise 11-34 Analog ICs; Jieh-Tsorng Wu Noise Performance of Other Conﬁgurations

• The equivalent input noise generators of a common-base stage or emitter follower are the same as those of a common-emitter stage.

• For the common-base conﬁguration, since its current gain ≈ 1, any noise current at the output is referred directly back to the input without reduction.

• For the emitter follower, since its voltage gain ≈ 1, any noise voltage at the output,

including noise due to zL, is transformed unchanged to the input.

• In most low-noise designs, common-emitter connection is used for the input stage.

Noise 11-35 Analog ICs; Jieh-Tsorng Wu Emitter-Coupled Pair Noise Performance

VCC VCC

RL RL RL RL 2 v 2 2 v 2 vi1 o vi2 vi1 o vi2

Q1 Q2 Q1 Q2

2 2 2 2 ii1 ii2 ii1 ii2 IEE REE IEE REE

VEE VEE

• If the circuit is balanced, the current-source noise represents a common-mode signal and will produce no diﬀerential output.

Noise 11-36 Analog ICs; Jieh-Tsorng Wu Eﬀect of Ideal Feedback on Noise Performance

2 2 vi vi

v1 vo v1 vo 2 a 2 a ii ii

× × f vo f vo

• For ideal feedback systems, the equivalent input noise generators can be moved unchanged outside the feedback loop and the feedback has no eﬀect on the circuit noise performance.

Noise 11-37 Analog ICs; Jieh-Tsorng Wu Eﬀect of Input Series Feedback Feedback on Noise Performance

2 2 via vi

v1 vo v1 vo 2 a 2 a iia ii

R R R F 2 R F E vf E 2 ve

2 = 2 = = vf 4kTRF ∆f ve 4kTRE ∆f R RF RE R v R v v = v + i R + F e + E f i ≈ i i ia ia + + i ia RF RE RF RE ⇒ 2 = 2 + 2 2 + 2 ≈ 2 vi via iiaR 4kTR∆f ii iia

Noise 11-38 Analog ICs; Jieh-Tsorng Wu Eﬀect of Input Shunt Feedback Feedback on Noise Performance

2 if

2 2 RF RF via vi

v1 vo v1 vo 2 a 2 a iia ii

2 = 1 if 4kT ∆f RF v ≈ = + ia + vi via ii iia if RF

2 v 1 ⇒ v 2 ≈ v 2 i 2 = i 2 + ia + 4kT ∆f i ia i ia 2 R RF F

Noise 11-39 Analog ICs; Jieh-Tsorng Wu Eﬀect of Feedback on Noise Performance

To analyze the noise performance of a practical feedback system, first use the loading approximation according to its feedback configuration to find the loading for the input port due to the feedback network.

For series feedback at the input

2 = 2 + 2 | |2 + 2 ≈ 2 vi via iia Zfb 4kTRfb∆f ii iia

For shunt feedback at the input

2 v 1 v 2 ≈ v 2 i 2 = i 2 + ia + 4kT ∆f i ia i ia | |2 Zfb Rfb where Zfb is the loading of the feedback network for the input port, and Rfb represents the resistive part (thermal noise) of the loading.

Noise 11-40 Analog ICs; Jieh-Tsorng Wu ﬀ E ect of Cµ on Noise Performance

2 vb r Cµ r B b B c C

C 2 cs i v 2 b 1 r C r i π π gmv1 o c

• Note that the collector-base capacitor Cµ represents single-stage shunt feedback, and thus does not significantly affect the equivalent input noise generators of a transistor, even if Miller effect is dominant. The capacitor itself contributes no noise. Also, in 2 2 | |2 | | = | | calculating ii , the term via/ Zfb can be neglected, since Zfb 1/ ωCµ is quite large at frequencies of interest.

Noise 11-41 Analog ICs; Jieh-Tsorng Wu Single-Stage Ampliﬁer with Local Feedback

2 2 if if

V o R 2 R 2 R 2 R F vi1 F vi2 F vi F

V i

R i 2 R i 2 R E i 2 i2 E i E i1 RE

2 ve

v 2 v 2 v 2 i1 ≈ + 1 i2 ≈ + 1 + i ≈ + 1 + 4kT rb 4kT rb RE 4kT rb RE ∆f 2gm ∆f 2gm ∆f 2gm i 2 i 2 i 2 i1 ≈ i2 ≈ i ≈ + 4kT 2qIB 2qIB 2qIB ∆f ∆f ∆f RF

Noise 11-42 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁer Noise Model

2 iia−

v 2 ia 2 iia+

• With FET input stage, the current noises can often be ignored at low frequencies since their values are small.

Noise 11-43 Analog ICs; Jieh-Tsorng Wu A Low-Pass Filter Example

Cf 2 2 i if 1 2 iia− Rf Rf V i V o V o R1 R1

R2 R2 2 via 2 iia+ 2 v2

2 R 2 R /R v 2 = i 2 + i 2 + i 2 f v 2 = v 2 + i 2 R2 + v 2 1 + f 1 o1 a− 1 f + o2 ia a+ 2 2 + 1 j2πf Rf Cf 1 j2πf Rf Cf

2 = 2 + 2 voT vo1 vo2

Noise 11-44 Analog ICs; Jieh-Tsorng Wu A Current Ampliﬁer Example

Q1 20 k

is 500

5 k io

2 Q2 via Q1 20 k

i 2 2 f iia

5.5 k 5k || 500

Noise 11-45 Analog ICs; Jieh-Tsorng Wu A Current Ampliﬁer Example

• Neglect ﬂicker noise and assume

= = = = Ω = = IC1 0.5mA IC2 1mA rb1 rb2 100 β1 β2 100 = = fT 1 300 MHz fT 2 500 MHz

• For both ﬁrst and second stages, the driving signals are high-impedance current sources, thus we need to consider only equivalent noise current generators.

• The equivalent noise current from the 2nd stage is approximately

1 2qI + 4kT = 2q(10 µA + 2.6 µA) B2 20 kΩ

= × which can be neglected when compared to 2qIC1 2q 500 µA.

Noise 11-46 Analog ICs; Jieh-Tsorng Wu A Current Ampliﬁer Example

• The equivalent input noise current for the ampliﬁer is

i 2 i 2 v 2 i = ia + ia + 4kT ∆f ∆f (5.5kΩ)2∆f 5.5kΩ I 4kT 1 4kT = 2q I + C + r + + B |β |2 (5.5kΩ)2 b1 2g 5.5kΩ 1 m1 500 µA = 2q 5 µA + + 2q × 0.2 µA + 2q × 9.1 µA |β |2 1 500 = 2q 14.3 + × 10−6 A2/Hz | |2 β1

• We know that 2 2 β 1 1 β f β(jf) = o ⇒ = 1 + o1 βof | |2 2 2 1 + j β1(jf) β f fT 1 o1 T 1

Noise 11-47 Analog ICs; Jieh-Tsorng Wu A Current Ampliﬁer Example

• ≈ = = The current gain of the ampliﬁer is AI 11 and is constant up to B 100 MHz fT 1/3. The total output noise is

2 B i B 500 i 2 = A2 i df = A2 × 2q 14.3 + × 10−6df oT I I | |2 0 ∆f 0 β1

B 500 500f 3 = A2 × 2q × 10−6 14.3f + f + I 2 2 3 βo1 fT 1 0 = 2 × × −6 × + = 2 × × −15 2 AI 2q 10 (14.3B 18.6B) AI 1.05 10 A

• The equivalent input noise current is

i 2 i 2 = oT ⇒ i = 32.4nArms iT 2 iT AI

Noise 11-48 Analog ICs; Jieh-Tsorng Wu Feedback and Frequency Compensation

Jieh-Tsorng Wu

December 5, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Feedback

Se Si a So

Sfb f

= · = · = − So a Se Sfb f So Se Si Sfb

S a a 1 Closed-Loop Gain = A ≡ o = = ≈ if T 1 Si 1 + af 1 + T f δA 1 δa Gain Sensitivity = = · A 1 + T a Loop Gain = T ≡ a × f

Feedback 12-2 Analog ICs; Jieh-Tsorng Wu Eﬀect of Negative Feedback on Distortion

If a is a nonlinear ampliﬁer

= + 2 + 3 + ··· = So a1Se a2Se a3Se T a1f

• For constant input level, the harmonic distortions are

2a2f − 2 1 + 1 a3(1 T ) HD = · HD | = HD = · HD | = 2 (1 + T )2 2 T 0 3 (1 + T )3 3 T 0

• For constant output level, the harmonic distortions are

2a2f − 2 1 + 1 a3(1 T ) HD = · HD | = HD = · HD | = 2 (1 + T ) 2 T 0 3 (1 + T ) 3 T 0

Feedback 12-3 Analog ICs; Jieh-Tsorng Wu Series-Shunt Feedback Conﬁguration

Basic Amplifier ii io

zo × v a v vo zi

× f vo

Feedback Network v a z T = a × f o = Z = z × (1 + T ) Z = o + i i o + vi 1 T 1 T

Feedback 12-4 Analog ICs; Jieh-Tsorng Wu Shunt-Shunt Feedback Conﬁguration

Basic Amplifier ii i io

zo × v vi a i o zi

× f vo

Feedback Network v a z z T = a × f o = Z = i Z = o + i + o + ii 1 T 1 T 1 T

Feedback 12-5 Analog ICs; Jieh-Tsorng Wu Shunt-Series Feedback Conﬁguration

Basic Amplifier ii i io

× vi a i zi zo

× f io

Feedback Network

i a z T = a × f o = Z = i Z = z × (1 + T ) + i + o o ii 1 T 1 T

Feedback 12-6 Analog ICs; Jieh-Tsorng Wu Series-Series Feedback Conﬁguration

Basic Amplifier ii io

v × a i zi zo

vi vo

× f io

Feedback Network

i a T = a × f o = Z = z × (1 + T ) Z = z × (1 + T ) + i i o o vi 1 T

Feedback 12-7 Analog ICs; Jieh-Tsorng Wu Two-Port Analysis of Feedback Ampliﬁer

Topology Series-Shunt Series-Series Shunt-Series Shunt-Shunt

Sfb V V I I So V I I V = = = = For Li set vo 0 io 0 io 0 vo 0 = = = = For Lo set ii 0 ii 0 vi 0 vi 0 Source Thevenin Thevenin Norton Norton = = Sfb Feedback signal; So Sampled Signal = = Li Input loop loading; Lo Output loop loading Fundamental Assumptions:

1. The input signal is transmitted to the output through the ampliﬁer a and not through the f feedback network.

2. The feedback signal is transmitted from the output to the input through the f block, and not through the ampliﬁer.

3. The feedback factor f is independent of the load and the source impedances.

Feedback 12-8 Analog ICs; Jieh-Tsorng Wu Two-Port Analysis of Feedback Ampliﬁer

1. Identify the topology.

2. Draw the basic ampliﬁer circuit without feedback using the loading approximation method.

3. Use a Thevenin’s source if Sfb is a voltage and a Norton’s source if Sfb is a current.

= 4. Indicate Sfb and So on the “open-loop” circuit. Evaluate f Sfb/So.

= 5. Evaluate forward gain a So/Si from the open-loop circuit.

6. Calculate closed-loop characteristics.

Feedback 12-9 Analog ICs; Jieh-Tsorng Wu Loading Approximation Method

To ﬁnd the input network:

= 1. Set vo 0 for shunt sampling; i.e., short the output node.

= 2. Set io 0 for series sampling; i.e., open the output loop.

To ﬁnd the output network:

= 1. Set vi 0 for shunt comparison; i.e., short the input node.

= 2. Set ii 0 for series comparison; i.e., open the input loop.

Feedback 12-10 Analog ICs; Jieh-Tsorng Wu Two-Port Analysis of a Shunt-Shunt Feedback Ampliﬁer

ro io vi R vo R v F S i i vo s r −a v RS RF i v i RF RL vs v RL = s is vo Zi Zo RS i = − fb RF

v R R i = o = − F L = fb = − 1 a (RS RF ri )( av ) f i = + ( ) v R s ifb 0 ro RF RL o F R T = a × f ≈ a × S v R + R S F v a 1 v R o = ≈ ≈−R ⇒ o ≈− F + F is closed loop 1 af f vs RS v R R r R v R R r r i = Z R = S F i ≈ F o = Z R = F L o ≈ o i S + o L + + is 1 T av io 1 T 1 T

Feedback 12-11 Analog ICs; Jieh-Tsorng Wu Return Ratio

RF RF r RS v vi v o i r v vo o v s r − v RS i avvi t RL RL

v v v v Return Ratio = R≡− r = o · i ·− r vt vt vo vi R [R + (R r )] R r = L F S i · S i · a + + + v ro RL [RF (RS ri )] RF (RS ri )

• The loop gain T = a · f in the two-port analysis is an approximation of R.

Feedback 12-12 Analog ICs; Jieh-Tsorng Wu Closed-Loop Gain Using Return Ratio

sin sic ksic sr soc sout

Rest of Circuit

s B −H s s ic = 1 in s = ks R≡− r = kH s dB s oc ic s out 2 oc oc s s s s = ic = out = − ic = out B1 B2 H d s = s = s = s = in soc 0 oc sin 0 oc sin 0 in soc 0

Feedback 12-13 Analog ICs; Jieh-Tsorng Wu Closed-Loop Gain Using Return Ratio

We have

s B kB g A = out = 1 2 + d = + dg= B kB s 1 + kH 1 + R 1 2 in g + R g + d(1 + R) R d d R 1 g A = = + = A∞ · + d · A∞ = + d 1 + R 1 + R 1 + R 1 + R 1 + R R

• d is the transfer function from the input to the output with k = 0.

• →∞ The value of A∞ can be found readily by letting k and sic is virtually “0”.

• Typically, A∞ is determined by a passive feedback network and is equal to 1/f from two-port analysis.

Feedback 12-14 Analog ICs; Jieh-Tsorng Wu Closed-Loop Gain Using Return Ratio

The A∞R term can be rewritten as g dH A∞ ·R= + d ·R= B kB + dR = B + · k · B R 1 2 1 B 2 2 sic sout = × k × s = s = in sout 0 oc sin 0

Feedback 12-15 Analog ICs; Jieh-Tsorng Wu Blackman’s Impedance Formula

Port X

ix vx sic ksic sr soc

Rest of Circuit

v a a i vx x = 1 2 x s = ks ⇒ Z (k = 0) = = a s a a s oc ic X i 1 ic 3 4 oc x k=0 a a R(port X open) = −ka R(port X shorted) = −k a − 2 3 4 4 a 1 1 − k a − a2a3 v 4 a1 1 + R(port X shorted) Z = x = a · = Z (k = 0) · X 1 − X + R ix 1 ka4 1 (port X open)

Feedback 12-16 Analog ICs; Jieh-Tsorng Wu A Transresistance Feedback Ampliﬁer

VCC RF

RC i RF r vo vo

vbe

iin iin rπ gm vbe it ro RC

i r R R = − r = o C · r · g i r R + R + r π m t o C F π v v r = o = − = o = π · A∞ RF d (ro RC) i =∞ i = r + R + r R in gm in gm 0 π F o C s v s v ic = be = out = o = − + rπ RF [ro RC (RF rπ)] s = i = s = i = in sout 0 in vo 0 oc sin 0 oc iin 0

Feedback 12-17 Analog ICs; Jieh-Tsorng Wu A Transresistance Feedback Ampliﬁer

The closed-loop gain is R d sic sout 1 d A = A∞ + = · k · · + 1 + R 1 + R s = s = 1 + R 1 + R in sout 0 oc sin 0

The output resistance is

1 + R(port X shorted) 1 + R(output shorted) R = R (k = 0) · = R (g = 0) · o X 1 + R(port X open) o m 1 + R(output open) = = + Ro(gm 0) ro RC (RF rπ) R(output shorted) = 0 R(output open) = R

Feedback 12-18 Analog ICs; Jieh-Tsorng Wu Frequency Response of Feedback Ampliﬁers

S Si a(s) So

Sfb f

S a(s) A(s) = o = + × Si 1 a(s) f

Feedback 12-19 Analog ICs; Jieh-Tsorng Wu Single-Pole Model

jω ao a(s) = T = a · f T = 0 s-plane − o o o 1 s/p1 a 1 A(s) = o × σ + − s 1 aof 1 + (1 + T ) p p (1 aof )p1 o 1 1 a = o × 1 + − s 1 To 1 + (1 To)p1

| | For ω p1 ,

a ω ω 1 1 a(s) ≈ o ≈ u A(s) ≈ u = × − s · + + s/p1 f ωu s f 1 s/(fωu) ≡ ×| | = ωu ao p1 Unity-Gain Frequency

Feedback 12-20 Analog ICs; Jieh-Tsorng Wu Nyquist Diagram Im ω<0

T o Re -1 ω = 0 T (jω) ω = ∞

ω>0

Nyquist diagram is the polar plot of a feedback ampliﬁer’s loop gain T (jω) = af for −∞ <ω<∞.

Feedback 12-21 Analog ICs; Jieh-Tsorng Wu Nyquist Criterion

• If the Nyquist plot encircles the point (−1, 0), the ampliﬁer is unstable.

• The number of encirclements of the point (−1, 0) gives the number of right-half-plane poles.

jω

s-plane

Nyquist Diagram encircles (-1, 0) Nyquist Diagram passes through (-1, 0)

◦ • If |T (jω)| > 1 at the frequency where ∠T (jω) = −180 , then the ampliﬁer is unstable.

Feedback 12-22 Analog ICs; Jieh-Tsorng Wu Phase Margin

dB T o T = 1 |a(jω)| 1 / f The phase margin is deﬁned as

PM = 180◦ + ∠T (jω ) p t 3 log ω p p 1 2 | | = ωt is the frequency where T (jωt) 1 Deg • A typical lower allowable limit for the ∠a(jω) ◦ ωt phase margin is 45 , with a value of log ω ◦ 60 being more common.

180 Phase Margin 270

Feedback 12-23 Analog ICs; Jieh-Tsorng Wu Pseudo Dominant-Pole Model

a a(s) = o + + (1 s/ω1)(1 s/ω2)

• = − ω1 p1 is the dominant pole frequency.

• If other poles and zero are on the real axis at much higher frequencies, then

m m 1 ≈ 1 − 1 ω −p −z 2 i=2 i i=1 i

• In practice, ω2 can be found from simulation. ω2 is the frequency at which

∠ = − ◦ a(jω2) 135

Feedback 12-24 Analog ICs; Jieh-Tsorng Wu Phase Margin of the Pseudo Dominant-Pole Model

At frequencies ω ω1 a ω a(s) ≈ o = u ω = a × ω + + u o 1 (s/ω1)(1 s/ω2) s(1 s/ω2) The loop gain becomes f · ω T (s) = a(s) · f = u + s(1 s/ω2) ∠ = − ◦ − −1 Since T (jω) 90 tan ω/ω2 ω ω = ◦ + ∠ = ◦ − −1 t t = ◦ − PM 180 T (jωt) 90 tan tan(90 PM) ω2 ω2 • ωt is the unity-gain frequency of T , i.e., | | = T (jωt) 1

• ωt is independent of the feedback factor f .

Feedback 12-25 Analog ICs; Jieh-Tsorng Wu Closed-Loop Response of the Pseudo Dominant-Pole Model

Since a a(s) = o + + (1 s/ω1)(1 s/ω2) The closed-loop gain is

a(s) A A A(s) = = o = o + × + 2 2 1 a(s) f + s(1/ω1 1/ω2) + s + s + s 1 + 1 ω Q 2 1 aof (1+a f )(ω ω ) o ω o 1 2 o + a (1 aof )/(ω1ω2) A = o ω = (1 + a f )(ω ω ) Q = o 1 + o o 1 2 + aof 1/ω1 1/ω2 √ • If Q = 1/ 2 = 0.707, |A(jω)| has the widest passband without peaking. It −3dB

frequency is ωo.

• If Q>0.5, the percentage overshoot of the step response is √ 2 % overshoot = 100e−π/ 4Q −1

Feedback 12-26 Analog ICs; Jieh-Tsorng Wu Quality Factor (Q) and Phase Margin

If aof 1 and ω2 ω1, then fa ω ω ≈ 1 ≈ ≈ o 1 ≈ u Ao ωo fωuω2 Q f f ω2 ω2

| | = Since T (jωt) 1, we have fω ω ω 2 |T (jω )| = u = 1 ⇒ f u = 1 + t t + ω ω jωt(1 jωt/ω2) t 2 ω ω ω 2 Q2 = f u = t 1 + t ω2 ω2 ω2

• For a given phase margin, ωt/ω2 is known. Then Q can be found using the above equation.

Feedback 12-27 Analog ICs; Jieh-Tsorng Wu Quality Factor (Q) and Phase Margin

PM ωt/ω2 f (ωu/ω2) Q Overshoot ◦ 45 1.000 1.414 1.189 36.8% ◦ 55 0.700 0.854 0.924 13.3% ◦ 60 0.577 0.666 0.816 8.7% ◦ 65 0.466 0.514 0.717 4.7% ◦ 70 0.364 0.387 0.622 1.4% ◦ 75 0.268 0.277 0.527 0.008%

• ≡ ≡ ≈ ◦ Deﬁne αt ωt/ω2 and αp f (ωu/ω2). Note that αt αp for PM > 65 .

◦ • Design with PM > 65 for no peaking in frequency response.

◦ • Design with PM > 80 for no overshoot in step response.

Feedback 12-28 Analog ICs; Jieh-Tsorng Wu Dominant-Pole Compensation

f s-plane jω Cc > 0 f = 0

V i gm1g m2 V o σ p p p’ 2 1 1 R1 C1 Cc R2 C2

The original poles of a(s) are

− − g = 1 = 1 = | |·| | = ·| | = m1 · p1 p2 ωu Av (0) p1 gm1R1gm2R2 p1 gm2R2 R1C1 R2C2 C1

By adding compensation capacitor Cc

−1 g p = ω = m1 · g R 1 + u + m2 2 R1(C1 Cc) (C1 Cc)

Feedback 12-29 Analog ICs; Jieh-Tsorng Wu Dominant-Pole Compensation

• The −3 dB bandwidth of the closed loop gain is approximately

· = ·| | ≈ = ·| | f ωu αp p2 ω−3dB ωt αt p2

where αt and αp are determined by the required phase margin.

• Cc usually is quite large (typically > 1000 pF) and cannot be realized on a monolithic chip.

• For a general-purpose opamp where 0

Feedback 12-30 Analog ICs; Jieh-Tsorng Wu Miller (Pole-Splitting) Compensation

f s-plane jω Cc f = 0 ic v1 v2 V i gm1 gm2 V o σ p’ p p p’ 2 2 11 R1 C1 R2 C2

Let f = 0, the nodal equations are + + − − G1 s(C1 Cc) sCc v1 = gm1vi − + + gm2 sCc G2 s(C2 Cc) v2 0

Feedback 12-31 Analog ICs; Jieh-Tsorng Wu Miller (Pole-Splitting) Compensation

The open-loop forward gain a(s) can be solved as

v 1 − s/z 1 − s/z a(s) ≡ 2 = a × 1 = a × 1 0 + + 2 0 vi 1 b1s b2s D(s) = a0 gm1gm2R1R2 g =+ m2 z1 Cc = + + + + = + + b1 R1(C1 Cc) R2(C2 Cc) gm2R1R2Cc b2 R1R2(C1C2 C1Cc C2Cc)

| | | | Using dominant-pole approximation, i.e., p1 p2 ,

1 1 p ≈− = − 1 + + + + b1 R1(C1 Cc) R2(C2 Cc) gm2R1R2Cc b R (C + C ) + R (C + C ) + g R R C p ≈− 1 = − 1 1 c 2 2 c m2 1 2 c 2 + + b2 R1R2(C1C2 C1Cc C2Cc)

Feedback 12-32 Analog ICs; Jieh-Tsorng Wu Miller (Pole-Splitting) Compensation

∼ ∼ ∼ Further, if gm2R2 1, R1 R2, and C1 C2 Cc, then

g ≈− 1 = − m1 × 1 p1 gm2R1R2Cc Cc a0 g C g p ≈− m2 c ≈− m2 2 + + + C1C2 C1Cc C2Cc C1 C2

The dominant-pole unity-gain frequency is

g = | |×| | = m1 ωu ao p1 Cc

• = Note that if Cc 0 = − 1 = − 1 p1 p2 R1C1 R2C2

• Cc acts as a pole splitting capacitor that separate p1 and p2.

Feedback 12-33 Analog ICs; Jieh-Tsorng Wu Miller (Pole-Splitting) Compensation

For a given phase margin, we have

· = ·| | ≈ = ·| | f ωu αp p2 ω−3dB ωt αt p2

Thus |p | g C 2 = f = m2 × c + ωu αp gm1 C1 C2

And Cc can be determined by

g = f × m1 × + Cc (C1 C2) αp gm2

• For compensation of a general-purpose opamp, let f = 1, then

g = ·| | = 1 × m1 × + ωu αp p2 Cc (C1 C2) αp gm2

Feedback 12-34 Analog ICs; Jieh-Tsorng Wu Feedforward Zero in Miller Compensation

• dB Because z1 is in the right half-plane (RHP), it will degrade the ampliﬁer phase margin | | a · as it approaches f ωu.

• z1 is caused by the feedforward path of Cc. log ω i = sC (v − v ) = sC v − sC v p’ z’ p’ c c 2 1 c 2 c 1 121 Deg

• To avoid degrading of phase margin by z , ∠ 1 a log ω want

z g z f · ω ⇒ 1 ≈ m2 f 90 1 u ωu gm1

180 • Otherwise, additional circuitry must be

added to move z1.

Feedback 12-35 Analog ICs; Jieh-Tsorng Wu Miller Compensation With Unity-Gain Buﬀer

VDD

Cc Mc

ic Assume the voltage gain of the Mc source follower is 1. Then Fbk VSS = − v1 v2 ic sCc(v2 v1) V g g V i m1 m2 o − = + gm2v1 v2(G2 sC2)

R12C1 RC2

g g R R a(s) = m1 m2 1 2 + + + + + 2 + 1 s[R1(C1 Cc) R2C2 gm2R2R1Cc] s R1R2C2(C1 Cc) 1 g p ≈− p ≈− m2 1 2 + gm2R1R2Cc C1 C2

Feedback 12-36 Analog ICs; Jieh-Tsorng Wu Miller Compensation With Common-Gate Stage

VDD

Cc Assume the input impedance of the Mc common-gate stage is 0. VB Mc Fbk Then ic v v 1 2 i = sC · v V i gm1 gm2 V o c c 2 − = + + gm2v1 v2(G2 sC2 sCc) R1 C1 R2 C2

g g R R a(s) = m1 m2 1 2 + + + + + 2 + 1 s[R1C1 R2(C2 Cc) gm2R2R1Cc] s R1R2C1(C2 Cc) 1 g C p ≈− p ≈− m2 · c 1 2 + gm2R1R2Cc C2 Cc C1

Feedback 12-37 Analog ICs; Jieh-Tsorng Wu Miller Compensation With Nulling Resistor

RZ Cc

Fbk

v1 v2 V i gm1 gm2 V o

R1 C1 R2 C2

− − 1 sCc 1/gm2 RZ a(s) = g g R R · m1 m2 1 2 + + 2 + 3 1 b1s b2s b3s

= + + + + + b1 R2(C2 Cc) R1(C1 Cc) RZ Cc gm2R1R2Cc = + + + + b2 R1R2(C1C2 CcC1 CcC2) RZ Cc(R1C1 R2C2) = b3 R1R2RZ C1C2Cc

Feedback 12-38 Analog ICs; Jieh-Tsorng Wu Miller Compensation With Nulling Resistor

We have

1 z = 1 − (1/gm2 RZ )Cc 1 g 1 p ≈− p ≈− m2 p ≈− 1 2 + 3 gm2R2R1Cc C1 C2 RZ C1

• In most cases, p3 p1,2.

• Usually want z1 becomes negative and

g | |≈ 1 = ⇒ 1 = · m1 ⇒ = 1 z1 1.2ωu 1.2 RZ RZ Cc RZ Cc Cc 1.2gm1

Feedback 12-39 Analog ICs; Jieh-Tsorng Wu Miller Compensation with Feedforward Transconductor

Fbk

v1 v2 V i gm1g m2 V o

R1 C1 R2 C2

gmf

g R g R + g R + sR R [g (C + C ) − g C ] a(s) = m1 1 m2 2 mf 2 1 2 mf 1 c m1 c + + + + + + 2 + + 1 s[R1(C1 Cc) R2(C2 Cc) gm2R1R2Cc] s [R1R2(C1C2 C1Cc C2Cc)] C 1 To remove zero, let g = g · c = g · mf m1 + m1 + C1 Cc 1 C1/Cc

Feedback 12-40 Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation

Cc2 Cc1 Fbk

v1 v2 v3 V i gm1 gm2 gm3 V o

R1 CR1 R2 C2 3 C3

N(s) a + a s + a s2 a(s) = = 0 1 2 + + 2 + 3 D(s) 1 b1s b2s b3s = a0 gm1gm2gm3R1R2R3 = − + a1 (gm2R2Cc1 Cc2)gm1R1R3 = − + a2 gm1R1R2R3Cc2(C2 Cc1)

Feedback 12-41 Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation

= + + + b1 K R1(Cc2 C1) gm2R2gm3R3R1Cc2 = + + + − 2 + + b2 R2R3(C3 Cc1 Cc2)(C2 Cc1) R2R3Cc1 R1(Cc2 C1)K − − 2 gm2R2Cc1Cc2R1R3 R1R3Cc2 = + + + + + b3 R1R2R3[(C3Cc2 C1C3 C1Cc2)(C2 Cc1) C1Cc1Cc2 C1C2Cc1] = + + + + + K R3(C3 Cc1 Cc2) R2(C2 Cc1) R2Cc1gm3R3

The dominant pole is

≈− 1 p1 R1Cc2(gm2R2gm3R3) | | | | If Cc1 C1,2, then p2 p3 , and

g g (g − g )C g − g p ≈− m2 m3 p ≈− m3 m2 c1 ≈− m3 m2 2 − 3 + + + (gm3 gm2)Cc1 C2C3 Cc1(C2 C3) C2 C3

Feedback 12-42 Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation

• To ensure p2 and p3 are in the LHP, want gm3 >gm2.

• | | | | | | If p1 p2 p3 ,

1 1 g − g p ∝ p ∝ p ≈− m3 m2 1 2 3 + Cc2 Cc1 C2 C3

| | The two-pole model can be used by making p3 ωt.

• If Cc1 is not large enough, p2 and p3 are either complex conjugates or real but closely spaced. Higher unity-gain bandwidth may be achievable when p2 and p3 are not real and widely separated.

Feedback 12-43 Analog ICs; Jieh-Tsorng Wu Zeros in the Nested-Miller Compensation

The numerator of a(s)is C C C (C + C ) = − c1 + c2 − 2 c2 2 c1 N(s) gm1R1gm2R2gm3 1 s s gm3 gm2R2gm3 gm2gm3

Assuming Cc1 C2 and Cc1 Cc2/(gm2R2), then C C C ≈ − c1 − 2 c2 c1 N(s) gm1R1gm2R2gm3 1 s s gm3 gm2gm3     g 4g C g 4g C = − m2  + + m3 c2 = − m2  − + m3 c2  z1 1 1 z2 1 1 2Cc2 gm2Cc1 2Cc2 gm2Cc1

• | | | | z1 is a LHP zero and z2 is a RHP zero. z1 > z2

•| | | | | | z1 and/or z2 can be comparable to p2 , thus degrading phase margin.

Feedback 12-44 Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation with Feedforward Transconductors

Cc2 Cc1 Fbk

v1 v2 v3 V i gm1 gm2 gm3 V o

R1 C1 R2 C2 R3 C3

gmf2

gmf1

R (n + n s + n s2) a(s) = − 3 0 1 2 + + 2 + 3 1 b1s b2s b3s

Feedback 12-45 Analog ICs; Jieh-Tsorng Wu Nested-Miller Compensation with Feedforward Transconductors

= + b1 b1 gmf 2R1R3Cc2 = + + b2 b2 gmf 2R1R2R3(C2 Cc1)Cc2 = b3 b3 = − − − n0 gm1gm2gm3R1R2 gmf 1 gm1gmf 2R1 = − + − n1 gm1(gm2 gmf 2)R1R2Cc1 (gm1 gmf 1)R1Cc2 − + − − gmf 1R2(C2 Cc1) gmf 1R1C1 gm1gmf 2R1R2C2 = − + − + n2 (gm1 gmf 1)R1R2(C2 Cc1)Cc2 gmf 1R1R2(C2 Cc1)C1

• = = To eliminate zeros, one can set n1 n2 0.

• = = If gmf 1 gm1 and gmf 2 gm2, then n0, n1, and n2 are all negative, and both zeros are in the LHP.

• = = ≈ With gmf 1 gm1 and gmf 2 gm2, b1 a1 and the dominant pole p1 is not changed ﬀ by gmf . However, p2 and p3 will be di erent from the case without gmf 1 and gmf 2.

Feedback 12-46 Analog ICs; Jieh-Tsorng Wu Basic Two-Stage Operational Ampliﬁer Design

Jieh-Tsorng Wu

December 23, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Ideal Operational Ampliﬁer Single-Ended Output Fully Differential

Vi Vo Vi Vo

A/2 x Vi A x V i Vcm A/2 x Vi

Vi Vi Vo

• = × Vo A Vi

• Ideal opamp: →∞ →∞ → – A , Zin , Zout 0. – No frequency dependence.

Opamp-I 13-2 Analog ICs; Jieh-Tsorng Wu Basic 2-Stage CMOS Opamp

VDD

M3 M4

V iCM1 M2 c Vo Output V’o Buffer Vi M5 VB1 M7

VSS

Cc Vi Vo A1 A2 1 V’o Vi

Differential Second Optional Input Stage Gain Stage Output Buffer

Opamp-I 13-3 Analog ICs; Jieh-Tsorng Wu Constant gm Bias Generator

VDD W = W L L M14 M13 M3 M4 1 2 M6 W = W L 3 L 4 V iCM1 M2 c Vo W = W V L L i 13 14 VB1 M5 M12 M7 W W M11 = α · L 12 L 11 R VSS B VSS √ 2 α − 1 (W/L) 1 (W/L)5 g = 2µC (W/L)I g = √ g = g · 1 m ox D m11 m1,m2 m11 2 RB α (W/L)11 (W/L)11 µp (W/L)3 1 (W/L)5 µp (W/L)6 (W/L) g = g · g = g · 7 m3,m4 m11 µ 2 m6 m11 µ n (W/L)11 (W/L)11 n (W/L)11 (W/L)11

Opamp-I 13-4 Analog ICs; Jieh-Tsorng Wu Input Stage Small-Signal Model

gm3 go3 gm4 vy VDD

g Cy o4 M3 M4 io1 vy io1 Vo1 vo1 vo1 V V i M1 M2 i C1 go1 go2 G R C vx m 1 1 VB1 M5 gm1 ( v i1 v x )gm2 ( v i2 v x ) VSS go5 Cx

= = = = gm1 gm2 gm3 gm4 go1 go2 go3 go4 gm go ≈ + = Cy Cgs3 Cgs4 2Cgs3

Opamp-I 13-5 Analog ICs; Jieh-Tsorng Wu Input Stage Output Impedance

gm3 go3 gm4 vy = = = = g I vi1 vi2 0 G1 1/R1 vt/it Cy o4 t3 = + + = · vy it it1 it2 it3 it1 vt go4 It1 it →∞ vt f I It2 1 ≈ · ≈ ≈ it2 vt go2 it3 i1 0 go1 go2 = + G1 go2 go4 vx f → 0 gm1 ( v i1 v x )gm2 ( v i2 v x ) go5 Cx ≈ · ≈ ≈ it2 vt go2/2 it3 i1 it2 = + G1 go2 go4

i g (g + g + sC ) g 1 + sC /g t2 = o2 m1 o5 x ≈ o2 · x m1 v g + g + g + g + g + sC 2 + t m2 mb2 o2 m1 o5 x 1 sCx/(2gm1) = + = + + gm1 gm1 gmb1 Cx Cx Cgs1 Cgs2

Opamp-I 13-6 Analog ICs; Jieh-Tsorng Wu Input Stage Diﬀerential-Mode Transconductance

g g g v m3 o3 m4 y 1 1 v = v − v v = − v v =+ v id i2 i1 i1 2 id i1 2 id C go4 i4 y 1 vy i = g v = − g v io1 1 m1 i1 2 m1 id vo1 1 i = g v =+ g v 2 m2 i2 2 m1 id g g i o1 o2 i −i g g 1 2 4 = m4 ≈ m3 vx + + + + i1 gm3 go1 go3 sCy gm3 sCy gm1 ( v i1 v x )gm2 ( v i2 v x ) = − − io i4 i2 + i 1 g 1 sCy /(2gm3) 1 − s/z G (s) ≡ o = − g 1 + m3 = −g · = −g · m md v 2 m1 + m1 + m1 − id gm3 sCy 1 sCy /gm3 1 s/pm 2g g ω = = − m3 ≈− = = − m3 ≈− t3 zm Mirror Zero ωt3 pm Mirror Pole Cy Cy 2

Opamp-I 13-7 Analog ICs; Jieh-Tsorng Wu Input Stage Common-Mode Transconductance

gm3 go3 gm4 vy

g I Cy o4 4 = = vic vi1 vi2 vy io1 = − i1 i2(1 d ) vo1 I I1 2 − = − i4 i1(1 m) g g = − − = − − o1 o2 io1 i4 i2 i1(1 m) i2 vx ⇒ = − + − ≈− + io1 i2(d m d m) i2(d m) g ( v v )g ( v v ) m1 i1 x m2 i2 x i i go5 Cx = o1 ≈− 2 · + Gmc (d m) vic vic

i g g (g + sC ) g + sC g 1 − s/z 2 = m1 = m1 o5 x ≈ o5 x = o5 · t 2(g +g ) vic + m1 mb1 2(g + g ) + g + sC + 2 − 1 + m1 mb1 o5 x 2 sCx/gm1 1 s/pt (go5 sCx) g 2g = = − o5 = = − m1 zt Tail Zero pt Tail Pole Cx Cx

Opamp-I 13-8 Analog ICs; Jieh-Tsorng Wu Input Stage Common-Mode Transconductance

For the M1-M2 source-coupled pair,

= − + − i1 gm1(vic vx) go1(vy vx) = − + − = − − i2 gm2(vic vx) go2(0 vx) gm1(vic vx) go1vx i v = − 1 y + + gm3 go3 sCy

We have g i = i + g v = i − i · o1 1 2 o1 y 2 1 g + g + sC m3 o3 y g = 1 ≈ − o1 = − i1 i2 i2 1 i2(1 d ) + go1 + + 1 + + gm3 go3 sCy gm3 go3 sCy g g g 1 g 1 = o1 ≈ o1 = o1 · = o1 · d + + + g + g − gm3 go3 sCy gm3 sCy m3 1 sCy /gm3 m3 1 s/pm

Opamp-I 13-9 Analog ICs; Jieh-Tsorng Wu Input Stage Common-Mode Transconductance

For the M3-M4 current mirror, + i g g go3 sCy − 4 = m4 = m3 = 1 − = 1 − + + + + + + m i1 gm3 go3 sCy gm3 go3 sCy gm3 go3 sCy + + + + go3 sCy go3 sCy g 1 sCy /go3 g 1 sCy /go3 = ≈ = o3 · = o3 · m + + + g + g − gm3 go3 sCy gm3 sCy m3 1 sCy /gm3 m3 1 s/pm

The common-mode transconductance is

i G (s) ≈− 2 · ( + ) mc v d m ic g 1 − s/z g g 1 + sC /g ≈− o5 · t · o1 · 1 + o3 · y o3 2 − g − g − 1 s/pt m3 1 s/pm m3 1 s/pm g (g + g ) (1 − s/z )(1 − s/z ) g + g = − o5 o1 o3 · t c z = − o1 o3 2g − − c m3 (1 s/pt)(1 s/pm) Cy

Opamp-I 13-10 Analog ICs; Jieh-Tsorng Wu Input Stage Voltage Gain

Adm

ω = · = · Adm Gdm Z1 Acm Gcm Z1 1 1 1 Z = = · 1 + + G sC g 2 g 4 − Acm 1 1 o o 1 s/po g + g ω p = Output Load Pole = − o2 o4 o C 1 Gmd CMRR CMRR = Gmc 2g g (1 − s/z )(1 − s/p ) = m1 m3 · m t + − − go5(go1 go3) (1 s/zt)(1 s/zc) g /2 1 CMRR(∞) = m1 = gm1 2 ω z p z p z p t o c m m t

Opamp-I 13-11 Analog ICs; Jieh-Tsorng Wu Simpliﬁed Two-Stage Model

v1 vo

gm1vi gm6v1 R1 C1 R2 C2

= + = + G1 go2 go4 G2 go6 go7 C1 Cgs6 v 1 − s/z A ≡ o = A (0) 1 v v v − − i (1 s/p1)(1 s/p2) = Av (0) gm1gm6R1R2 g 1 g g p ≈− m1 × p ≈− m6 z =+ m6 1 2 + 1 Cc Av (0) C1 C2 Cc

Opamp-I 13-12 Analog ICs; Jieh-Tsorng Wu Frequency Compensation Using Nulling Resistor

VDD

M14 M13 M3 M4

M6 M10 M16 M15 V i M1 M2 Cc Vo

Vi VB1 M5 M12 M7 M11

R VSS B VB2 VSS

Opamp-I 13-13 Analog ICs; Jieh-Tsorng Wu Frequency Compensation Using Zero-Nulling Resistor

• The zero-nulling resistor Rc is realized by M10 in the triode region. 1 g z = = − m6 1 − − (1/gm6 Rc)Cc (gm6Rc 1)Cc

• Let (W/L)13 = (W/L)15 and (W/L)7 = (W/L)6 , then (W/L)14 (W/L)16 (W/L)11 (W/L)13 V V (W/L) = = = = ov6 = ov13 = 15 Vov6 Vov13 Vov14 Vov10 Vov15 Vov16 Vov10 Vov15 (W/L)13 g 6 (W/L)6 V 6 (W/L)6 (W/L)15 g R = m = ov = m6 c g m10 (W/L)10 Vov10 (W/L)10 (W/L)13

• ≈ − + p2/z1 (gm6Rc 1)Cc/(C1 C2) is independent of process and temperature variations.

Opamp-I 13-14 Analog ICs; Jieh-Tsorng Wu Voltage and Current Range

Input Common-Mode Range

= − + = + + Vic(max) VDD VGS3 Vt1 Vic(min) VSS VDSAT5 VGS1

• The range is limited to the voltage levels where any transistor goes out of saturation.

Output Voltage Range

= − = + Vo(max) VDD VDSAT6 Vo(min) VSS VDSAT7

• Output resistive load can also limit the voltage range, if the available output current is insuﬃcient.

Maximum Output Current = = 1 W − 2 − Io(sink,max) ID7 Io(source,max) kp [Vgs6(max) Vt6] ID7 2 L 6 = − + Vgs6(max) VDD Vi+ Vt2

Opamp-I 13-15 Analog ICs; Jieh-Tsorng Wu Slew Rate VDD

M3 M4 Ix V o M6 V i I V V o i M1 M2 i Cc Vo

V C2 i V ISS B1 M7 t VSS

Exponential Log (SR) V o SR ext SR int SR t Log (C2 )

Opamp-I 13-16 Analog ICs; Jieh-Tsorng Wu Slew Rate

The internal slew rate is generally limited by current available to charge and discharge

Cc from input stage. Therefore, dV I I = o = x(max) = SS SRint dt max Cc Cc I g I = SS × m1 = SS × ωu gm1 Cc gm1 = − × (VGS1 Vt1) ωu = × Vov1 ωu

The external slew rate is limited by the available current to charge and discharge C2. Thus, I − I (max) I − I = D7 x = D7 SS SRext C2 C2

Opamp-I 13-17 Analog ICs; Jieh-Tsorng Wu Settling Time

The frequency response and step response of a single-pole ampliﬁer is Ao − A(s) = V (t) = A 1 − e ωpt + o o 1 s/ωp

The settling time can be written as

A = 1 1 = o 1 ts() ln ln ωp ωu

• = · ωu Ao ωp is the dominant-pole unity-gain frequency.

• = −| | 1 Vo(ts)/A o is the error when settling occurs.

The 10% to 90% rise time is

= 1 = 2.2 = 0.35 = tr ln(9) ωp 2πfp ωp ωp fp

Opamp-I 13-18 Analog ICs; Jieh-Tsorng Wu Input Impedance

Cin- C VDD

Cd Vo M3 M4 Cin+ C M6

Vi M1 M2 Vi C C c t Vo Cgd2 R1 M6 M5 VB1 M7 M2 Vi Vo g m2 Cc R2 VSS

Opamp-I 13-19 Analog ICs; Jieh-Tsorng Wu Input Impedance

Shorting the noninverting input to ground,

Cgs1 C − = C + C− ≈ in d 2

Shorting the inverting input to ground,

Cgs1 C + = C + C+ ≈ + C · (1 + A ) A = g R in d 2 gd2 o1 o1 m2 1

And we have Cgs2 C ≈ C− ≈ 0 C+ ≈ C · (1 + A ) d 2 gd2 o1

Opamp-I 13-20 Analog ICs; Jieh-Tsorng Wu Input Impedance

The equivalent voltage gain of the M2 stage decreases with increasing frequency, due ﬀ the the e ect of Ct. The capacitance C+ is then modiﬁed as

C 1 + gd2 s gm2 C+ ≈ C · A · gd2 o1 C +C 1 + A gd2 t s o1 gm2 where = + · + = + · + Ct Cgs6 Cc (1 Ao2) Cgs6 Cc (1 gm6R2)

• + For gm2/[Ao1(Cgd2 Ct)] <ω

Opamp-I 13-21 Analog ICs; Jieh-Tsorng Wu Output Impedance

Log |Zo|

Cc R2

v1 1/gm6 R1 C1 gm6v1 R2 Z o

with unity-gain feedback | | | | ω | | Log f p1 z1 u p2 Assuming gm6 R1 and R2,wehave 1 + sR (C + C ) Z = R · 1 c 1 o 2 + + 2 1 sgm6R1R2Cc s R1C1R2Cc 1 g 1 g 1 p ≈− = − m1 · p ≈− m6 z ≈− 1 | | 2 1 + gm6R1R2Cc Cc Av (0) C1 R1(Cc C1)

Opamp-I 13-22 Analog ICs; Jieh-Tsorng Wu Output Impedance

• For frequencies larger than z1, Cc acts as a short, the Zo is a resistive 1/gm6.

• ﬀ The closed-loop Zo of the unity-gain bu er is

Z R ≈ o ≈ 2 · − Zoc (1 s/z1)forω<ωu Av Av (0)

= where ωu gm1/Cc.

Opamp-I 13-23 Analog ICs; Jieh-Tsorng Wu Systematic Input Oﬀset Voltage

VDD

M3 M4 V1 1 V I = kV 2 (1 + λV ) Y M6 D 2 ov DS VOS λ = λ λ = λ V V 1 2 3 4 i M1 M2 i Cc V I o = − = SS − ∆I1−2 ID1 ID2 λ1(VY V1) ISS 2 I = | |−| | = SS − VB1 M7 ∆I3−4 I 3 I 4 λ3(V1 V ) M5 D D 2 Y

VSS The systematic input referred dc oﬀset can be expressed as

V − = 1 · − = ov,1−2 · + − VOS,s (∆I1−2 ∆I3−4) (λ1 λ3)(VY V1) gm1 2

Opamp-I 13-24 Analog ICs; Jieh-Tsorng Wu Systematic Input Oﬀset Voltage

• ﬀ The systematic o set is caused by asymmetry in the dc biasing of VY and V1.

• = = To minimize VOS,s, want VDS3 VDS4 VGS6, then

(W/L) (W/L) (W/L) 3 = 4 = 5 (W/L)6 (W/L)6 2(W/L)7

• Further, to minimize process induced variations choose

= = L3 L4 L6

However, this constraint may conﬂict with frequency response and noise constraints.

Opamp-I 13-25 Analog ICs; Jieh-Tsorng Wu Random Input Oﬀset Voltage

| | + | | | | + | | Vi Vj Ii Ij ∆V − = |V |−|V | V − = ∆I − = |I |−|I | I − = i j i j i j 2 i j i j i j 2 W W W W 1 W W ∆ = − = + L i−j L i L j L i−j 2 L i L j

∆ID,3−4 ∆(W/L) − ∆Vt,3−4 ∆ID,1−2 ⇒ = 3 4 − 2 = ID,3−4 (W/L) − Vov,3−4 ID,1−2 3 4 V − ∆I − ∆(W/L) − = + ov,1 2 D,1 2 − 1−2 VOS,r ∆Vt,1−2 2 ID,1−2 (W/L) − 1 2 V − V − ∆(W/L) ∆(W/L) = − ov,1 2 · + ov,1 2 − 1−2 + 3−4 ∆Vt,1−2 ∆Vt,3−4 Vov,3−4 2 (W/L) − (W/L) − 1 2 3 4 gm3 Vov,1−2 ∆(W/L)1−2 ∆(W/L)3−4 = ∆V − − · ∆V − + − + t,1 2 g t,3 4 2 m1 (W/L)1−2 (W/L)3−4

Opamp-I 13-26 Analog ICs; Jieh-Tsorng Wu Input Oﬀset Voltage and Common-Mode Rejection Ratio

The output voltage change due to common-mode input variation is

= · ∆Vo Acm ∆Vic

ﬀ = Want to change di erential input so that ∆Vo 0, then

∆V A = − o = − cm · ∆Vid ∆Vic Adm Adm

Therefore, we have − 1 −1 Adm ∂Vid ∂VOS CMRR ≡ = = A ∂V = ∂V cm ic ∆Vo 0 ic

Opamp-I 13-27 Analog ICs; Jieh-Tsorng Wu CMRR Due to Systematic and Random Oﬀset

Since = + VOS VOS,s VOS,r We have 1 ∂VOS,s ∂VOS,r = + CMRR ∂Vic ∂Vic

∂VOS,s ∂VOS,s ∂V ∂I 1 1 g = · ov1 · d1 = − (λ + λ )(V − V ) · · m1 1 3 Y 1 + + ∂Vic ∂Vov1 ∂Id1 ∂Vic 2 gm1 1 2(gm1 gmb1)ro5 1 1 (λ + λ )(V − V ) = − (λ + λ )(V − V ) · ≈− 1 3 Y 1 2 1 3 Y 1 1 + 2(g + g )r 4(g + g )r m1 mb1 o5 m1 mb1 o5 ∂V ∂V ∂V ∂I ∆(W/L) − ∆(W/L) − OS,r = OS,r · ov1 · d1 = −1 − 1 2 + 3 4 · 1 + + ∂Vic ∂Vov1 ∂Id1 ∂Vic 2 (W/L) − (W/L) − 1 2(gm1 gmb1)ro5 1 2 3 4 ∆(W/L) ∆(W/L) = − − 1−2 + 3−4 · 1 + (W/L)1−2 (W/L)3−4 4(gm1 gmb1)ro5

Opamp-I 13-28 Analog ICs; Jieh-Tsorng Wu Mismatches and Input Stage Transconductance

Deﬁne + + gm,i gm,j ro,i ro,j ∆g − = g − g g − = ∆r − = r − r r − = m,i j m,i m,j m,i j 2 o,i j o,i o,j o,i j 2 Then ∆g 2 1 − m,1−2 2gm,1−2 gm,1−2 G ≈ g − · G ≈− · ( + ) md m,1 2 ∆g mc + d m 1 + m,3−4 1 2gm,1−2ro5 2gm,3−4 where ∆g − 2r 2r ∆r − ≈ 1 − m,1 2 + o5 − o5 · o,1 2 d 1 gm3ro1 gm,1−2 ro1 ro1 ro,1−2

1 (g − g )r 1 ∆gm,3−4 = + m3 m4 o3 ≈ + m + + 1 gm3ro3 1 gm3ro3 gm3ro3 gm,3−4

Opamp-I 13-29 Analog ICs; Jieh-Tsorng Wu Power Supply Rejection Ratio (PSRR)

VDD

vdd v = −A v + A v + A v VDD o v id dd dd ss ss A ≡ v PSRRDD M3 M4 Add A M6 ≡ v PSRRSS Ass vid M1 M2 C c Av(0) Vo A = v − 1 s/p1 = Av (0) gm1gm6R1R2 VB1 M7 M5 g = − m1 Av(0)p1 VSS Cc vss g ≈ m1 | | Av for ω p1 VSS sCc

Opamp-I 13-30 Analog ICs; Jieh-Tsorng Wu Power Supply Rejection Ratio (PSRRSS)

VDD

M3 M4 v A M6 o = = v Av,cm vss1 CMRR C Z 1 c 6 Z ≈ v 6 M1 M2 o gm6 x 1 Z = 7 + r r go7 sC7 x C o7 C x 7 v Z Z g + sC o = 6 ≈ 6 ≈ o7 7 + v v vss2 Z6 Z7 Z7 gm6 ss1 ss2 VSS VSS

v /v + v /v (1 + sr C )(1 − s/p ) 1 = o ss1 o ss2 = 1 + o7 7 1 ≈ 1 PSRRSS Av CMRR gm6ro7Av (0) CMRR

Opamp-I 13-31 Analog ICs; Jieh-Tsorng Wu Power Supply Rejection Ratio (PSRRDD)

g m4 (v - v y ) v M3 M4 v dd2 dd2 v dd1 1 M6 C y 1 v y dd2 g v m3 y v C y c C y0 v v M1 M2 o R R o x y0 1 Cc R 2 M5 VB1 M7

VSS

R C v 1d 1d g dd1 m6 (v - v ) dd1 1 g v m6 o v v v o dd1 1 Cc R 2 R 2

Opamp-I 13-32 Analog ICs; Jieh-Tsorng Wu Power Supply Rejection Ratio (PSRRDD)

The voltage gain from vdd1 to vo is

v 1 1 o = ≈ ≈ 1 + + vdd1 + 1 (g1d sC1d )/(sCc) + C1d /Cc 1 + + 1 R2(g1d sC1d ) gm6R2 gm6R2

+ + For vdd2 input, since gm3 sCy Gy0 sCy0, the resulting current ﬂow in M3 is approximately ≈ · + iy0 vdd2 (gy0 sCy0)

The current is mirrored in M4, and ampliﬁed by M6 and Cc. The voltage gain is

v g + sC v v o = · ≈− y0 y0 ⇒ o o iy0 Av2 vdd2 sCc vdd2 vdd1

Thus A ≈ v ≈ PSRRDD Av vo/vdd1

Opamp-I 13-33 Analog ICs; Jieh-Tsorng Wu PSRRDD with Common-Gate Miller Compensation

g (v − v ) M3 M4 v m6 dd1 1 v dd1 v v v 1 dd1 dd1 o g M6 R C m6 y 1 1d 1d v y M10 Cp R v 2 1 M10 v M1 M2 o Cp Cc x M10 Cc v o M5 Cc Bias M7 R 2

VSS

= = Assume the M10 stage has Rin 1/gm10 and AI 1. Neglecting R1d and C1d ,wehave v 1 Cp C o = ≈ · 1 + s c vdd1 1 · Cc + sCc + 1 Cc gm10 + 1 sCc/gm10 Cp gm6 gm6R2

Opamp-I 13-34 Analog ICs; Jieh-Tsorng Wu Supply Capacitance

CI VDD

C I M3 M4 Csup C gd1 M6 Vn Vo Vy

M1 M2 Cc Vx Vo

Cgs1 Id5 Csup M5 V = − · V V o CI n B1 M7

VSS

• Both Cgs1 and Cgd1 can function as Csup, and noises at Vx and Vy can leak to the output.

Opamp-I 13-35 Analog ICs; Jieh-Tsorng Wu Power-Supply Rejection and Supply Capacitance

• The VDD noise can be coupled to Vy through the diode-connected M3 device. The use of cascode input stage can overcome this problem.

• ≈ If Id5 is modulated by the supply voltage variation, then vx id5/(2gm1). The use of supply-independent bias reference can overcome this problem.

• The noises at the substrate/well terminals of M1 and M2 can change the Vt of the ﬀ devices due to body e ect, and cause Vgs variation, introducing noises at Vx.A solution is to place both M1 and M2 in a single well, and connect well and source terminals together to eliminate body eﬀect.

• Interconnect crossovers can introduce undesired coupling capacitors to the Vi− summing node. Careful layout is required.

• Fully-diﬀerential circuit topology generally has better power-supply rejection performance.

Opamp-I 13-36 Analog ICs; Jieh-Tsorng Wu Device Noise Analysis

VDD VDD

M3 M4 M3 M4 V V v v DS3 DS3 n3 n4

I I o o

M1 M2 M1 M2 v v v n1 n2 nT I I SS SS VSS VSS K 2 ≈ 2 · 1 + f · 1 2 ≈ vn 4kT in 0 3 gm WLCox f g 2 2 = 2 + 2 + m3 2 + 2 vnT vn1 vn2 vn3 vn4 gm1

Opamp-I 13-37 Analog ICs; Jieh-Tsorng Wu Thermal Noise Performance

= = = Assuming M1 M2 and M3 M4, and knowing ID1 ID3 so that

2 g µpCox(W/L)3 µp(W/L)3 m3 = = k = µ C k = µ C g n n ox p p ox m1 µnCox(W/L)1 µn(W/L)1

The input referred thermal noise is

2 2 v(Θ)T 4 1 g 4 1 4 1 g = 4kT + m3 × 4kT = 4kT × 1 + m3 ∆f 3gm1 gm1 3gm3 3gm1 gm1     4 1   µp (W/L)3  = 4kT  ·  × 1 + ·  3 µ n (W/L)1 2kn(W/L)1ID1

• The load contribution can be made small by making gm1 >gm3 or (W/L)1 > (W/L)3.

• gm1 should be made as large as possible to minimize thermal noise contribution.

Opamp-I 13-38 Analog ICs; Jieh-Tsorng Wu Flicker Noise Performance

The input referred 1/f noise is

2 v 2K g 2 2K 2K µ (W/L) 2K (1/f )T = fn + m3 × fp = fn + p 3 × fp ∆f W1L1Coxf gm1 W3L3Coxf W1L1Coxf µ (W/L) W3L3Coxf n 1 2 1 2K Kfp µp L = × fn 1 + · · 1 2 f W L C K µn 1 1 ox fn L3

• Kfp is typically smaller than Kfn by a factor of two or more.

• The load contribution can be made small by making L3 >L1. But longer L3 can limits the signal swing somewhat.

• The width of load devices does not aﬀect the 1/f noise performance. But make it wider can maximize signal swing.

• Making W1 wider can reduce 1/f noise.

Opamp-I 13-39 Analog ICs; Jieh-Tsorng Wu 2-Stage Opamp with pMOST Input Stage

VDD

VB1 M7 M5 Vi Vo Output V’o C Buffer Vi M1 M2 c

M3 M4

VSS

Opamp-I 13-40 Analog ICs; Jieh-Tsorng Wu 2-Stage Opamp with pMOST Input Stage

Comparing to the nMOST-input opamps, the pMOST-input opamps have

• Similar dc voltage gain.

• Smaller gm1 and larger gm6.

• | | | | = Larger unity-gain frequency since ωu p2 and p2 gm6/C2.

• Better slew rate since both Vov1 and ωu are larger.

• Better 1/f noise performance.

• Poorer thermal noise performance.

Opamp-I 13-41 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁers with Single-Ended Outputs

Jieh-Tsorng Wu

December 23, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Two-Stage Operational Ampliﬁer with Cascode

VDD

• The volage gain A ∝ (g r )3. M3 M10 M6 v m o M4 • Size M8 so that M3A M4A M9 = Vo VDS1 VDS2 VDSAT Cc VDD

IB1 • Input common-mode range is M1A M2A reduced by cascodes.

M8 Vi M1 M2 • The additional poles are non- dominant and located near ωT . Vi M5 • VB1 M7 The 2nd stage can also use cascodes.

VSS

Opamp-II 14-2 Analog ICs; Jieh-Tsorng Wu Telescopic-Cascode Operational Ampliﬁer

VDD • ∝ 2 The volage gain Av (gmro) .

M3 M4 • Consider the output current branch,

VB2 M4A − − + M3A VDD (VIC Vt) >∆Vo 3Vov Vo ⇒ − + − VDD VIC >∆Vo 3Vov Vt VDD CL = + + Since VIC,min Vt 2Vov VSS,wehave IB1 M1A M2A − + VDD VSS >∆Vo 5Vov M8 Vi M1 M2 • Consider the non-output branch, Vi V − − + B1 M5 VDD (VIC Vt) >Vt 2Vov ⇒ − − + VDD VIC > 2Vov or VDD VSS >Vt 4Vov VSS

Opamp-II 14-3 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Ampliﬁer

VDD

M10 V bsp M9

M4 V ccp M3 V o V i+ M1 M2 M6 V ccn V i- M5 I M8 M7 1 C L VSS

Opamp-II 14-4 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Ampliﬁer

• Consider output stage

− + − + VDD VSS >∆Vo 4Vov or VDD VSS >Vt 3Vov

Consider input stage

= − + = + + + VIC,max VDD Vov Vt VIC,min VSS Vt Vov Vo,min(I1)

• The diﬀerential-mode voltage gain is

A (0) = v = = − 1 = 1 Av Av(0) gm1Ro p1 Ro + − go2 go9 + go7 1 s/p1 RoCL gm3ro3 gm5ro5 | | At midband frequencies where ω p1 A (0) g ω g A ≈ v = m1 = u ω = m1 v − s u s/p1 sCL CL

Opamp-II 14-5 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Ampliﬁer

• The dominant poile is associated with the only high-impedance node at Vo. All other | | poles are located near ωT , and their magnitude are normally larger than p2 of the two-stage opamps.

• CL provides the dominant-pole frequency compensation. Increasing CL improves the phase margin.

• If lead compensation is desired, a resistor can be placed in series with CL. • Use nMOST input stage for larger gm1 and better thermal noise performance. • Good PSRR since no pole-splitting Cc.

• Slightly higher noise due to more devices.

• Suitable for low-voltage operation.

• Active cascodes can be used to increase voltage gain.

Opamp-II 14-6 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Ampliﬁer

VDD

V bsp

M11 M12 M10 M9

M4 V ccp M3 V o V i+ M1 M2 M6 V ccn V i- M5 I M8 M7 1 C L VSS

Opamp-II 14-7 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Ampliﬁer

If bias currents ID1,D2 >ID3,D4, i.e., I1 >ID9,D10,

• Without M11 and M12, the slew rate is

I I SR = D9 = D10 CL CL

• During slew condition, M11 and M12 can be used to clamp the drain volage of M1

and M2 to reduce bias recovery time, and increase ID9 and ID10 to improve SR.

If bias currents ID1,D2

• This slew rate is I = 1 = + SR I1 ID1 ID2 CL

• M11 and M12 are not required.

Opamp-II 14-8 Analog ICs; Jieh-Tsorng Wu Current-Mirror Operational Ampliﬁer

VDD

M3 M4M6 M5

M9 V ccp M10M12 M11 V o V i+ M1 M2 M13 V ccn V i- M14 I M7 M8 1 C L VSS

Opamp-II 14-9 Analog ICs; Jieh-Tsorng Wu Current-Mirror Operational Ampliﬁer

W = W = W = 1 W W = 1 W L 3 L 4 L 6 K L 5 L 7 K L 8 KI = = = = 1 = 1 = 1 = 1 ID1,D2 ID3,D4 ID6 ID7 ID5 ID8 I1 SR K K 2 CL Kg = = 1 = − 1 = m1 A (0) Kg 1R R p1 ω v m o o go5 go8 u + RoCL CL gm11ro11 gm14ro14

• For a given power dissipation, the current-mirror opamps have larger bandwidth and SR than the folded-cascode opamps. But they also suﬀer from larger thermal noise.

• For small CL, K may have to be reduced to prevent the nondominant poles from degrading the phase margin.

• A practical upper limit on K is around 5. For a general-purpose opamp, K 2.

Opamp-II 14-10 Analog ICs; Jieh-Tsorng Wu Rail-to-Rail Complementary Input Stage VDD

I I 2p 1p Io,n1

V i+ V i- I p Io,n2 M3 M4

V i+ V i- M1 M2

Io,p2 I n V i+ V i-

I I I o,p1 2n 1n

VSS

Opamp-II 14-11 Analog ICs; Jieh-Tsorng Wu Rail-to-Rail Complementary Input Stage

• Total input stage transconductance is

= + Gm gm1 gm3

• Gm variation due to Vic change can degrade CMRR. Want + = + = gm1 gm3 µnCox(W/L)1In µpCox(W/L)3Ip Constant

= If µnCox(W/L)1 µpCox(W/L)3, want + = − + − = In Ip I1n I2p I1p I2n Constant

Opamp-II 14-12 Analog ICs; Jieh-Tsorng Wu Rail-to-Rail Complementary Input Stage

• Let = = = = I1n I1p 4II2n I2p 3I − At Vic (VDD VSS)/2 + = + = In Ip 1I 1I 2 I = = At Vic VSS, In 0 and I2n 0, + = + = In Ip 0I 4I 2 I

= = At Vic VDD, Ip 0 and I2p 0, + = + = In Ip 4I 0I 2 I

• Less than 5% change in Gm is possible. • ﬀ The variation of the input-referred dc o set VOS due to Vic change also degrade CMRR.

Opamp-II 14-13 Analog ICs; Jieh-Tsorng Wu A Rail-to-Rail Input/Output Opamp

VDD

I p M11 M12 Cc

M13 V ccp M21 M14 M3 M4

V bop V o V i+ V i- M23 M25 M1 M2 V bon M24 M26

M22 C M17 V ccn L M18

I Cc n M15 M16

VSS

Opamp-II 14-14 Analog ICs; Jieh-Tsorng Wu A Rail-to-Rail Input/Output Opamp

• Two cascaded gain stages.

• Noises in Vbop and Vbon are canceled at output.

• The bias of the output stage is insensitive to variations in Ip, In and supply voltage.

• The two Cc are connected as Miller frequency compensation using common-gate stages.

• The output pole is C g = c × mo p2 Cgso CL

where gmo and Cgso are respectively the total gm and Cgs of the output stage.

• Reference: Hogervorst, et al., JSSC 12/94, pp. 1505–1513.

Opamp-II 14-15 Analog ICs; Jieh-Tsorng Wu Low-Voltage Multi-Stage Opamp

VDD

M5 M6 M7 M8

M1 M2 C2a C2b M9

M10 V V i+ i- M11 C1a C3 Bias V o M3 M4 C1b

M12

VSS

Opamp-II 14-16 Analog ICs; Jieh-Tsorng Wu Low-Voltage Multi-Stage Opamp

• Four cascaded gain stages.

• Hybrid nested Miller compensation.

• Class-AB output stage.

• A supply voltage below 1.5 V is possible.

• Reference: Eschauzier, et al., JSSC 12/94, pp. 1497–1504.

Opamp-II 14-17 Analog ICs; Jieh-Tsorng Wu Current-Feedback Conﬁguration R2 R2

R1 R1 I o V i V i V o V o V x Z I x i RL RL

Voltage-Feedback Opamp Current-Feedback Opamp

= ≈ →∞ For the voltage-feedback opamp, let Vo/Vx A ωu/s and Zi , then

V R R = o = − 2 · 1 ≈− 2 · 1 Av Vi R1 1 + 1 1 + R2 R1 1 + s 1 + R2 A R1 ωu R1

• Trade-oﬀ between closed-loop gain and closed-loop bandwidth.

Opamp-II 14-18 Analog ICs; Jieh-Tsorng Wu Current-Feedback Conﬁguration

= ≈ For the current-feedback opamp, let Io/Ix A ωu/s, then

1 − Zi Vo R2 AR2 R2 1 A = = − · ≈− · v + + + R +R V R 1 R1R2 Zi (R1 R2 RL) R + + 2 L i 1 + + 1 R2 Zi 1 1 1 s R1 A R1RL 1 + 1 + ωu RL

→ If Zi 0, R ≈− 2 · 1 Av R1 1 + s R2 ωu RL

• The closed-loop gain can be modiﬁed by changing R1, leaving the closed-loop bandwidth unchanged.

• For a given R2, frequency compensation can be optimized. Suitable for high- frequency applications.

Opamp-II 14-19 Analog ICs; Jieh-Tsorng Wu A CMOS Current-Feedback Driver

VDD

I 2I

V o M11 V ccp M21 M1 R2 M3 M23 V bop V o V V i icm V R1 M24 bon M4 M2 M22 R M12 V ccn L

I 2I

VSS

Opamp-II 14-20 Analog ICs; Jieh-Tsorng Wu A CMOS Current-Feedback Driver

• = Ω This opamp has been designed to drive RL 25 and provide 50 mA of output current.

• Two-stage opamp with only one high-impedance node.

• Cgs and Cgd of M21 and M22 are large enough to provide adequate frequency compensation.

• The class-AB common-gate input stage provides large internal slew rate.

• Large voltage swing of Vgs21 and Vgs22 are required.

• Open-loop current gain is determined by the output stage, g ω g ≈ mo = u = mo A(s) ωu sCgo s Cgo

• ≈ + Loop gain T (s) A(s)RL/(RL R2) is independent of R1.

Opamp-II 14-21 Analog ICs; Jieh-Tsorng Wu A General-Purpose BJT Current-Feedback Opamps

VCC

1:1 Output I B Buffer I f 1 V o Q3 Q1 Ro Cc

V i V n R2

I f Q4 Q2 R1

I B 1:1

VEE

Opamp-II 14-22 Analog ICs; Jieh-Tsorng Wu A General-Purpose BJT Current-Feedback Opamps

= Due to the symmetry of the input stage, we have Vi Vn. + If R1 R2 1/(gm1 gm2), we have V − V V = o n − n = 1 − 1 + 1 = − 1 If Vo Vi Vo If R2 R1 R2 R1 R2 sC + 1/R c o V R (R + R ) 1 A = o = o 1 2 v + + Vi (Ro R2)R1 1 sCc(Ro R2) If Ro R2, R 1 A ≈ 1 + 2 v + R1 1 sCcR2 Also the loop gain is 1 1 1 T (s) = ≈ + sCc 1/Ro R2 sCcR2

Opamp-II 14-23 Analog ICs; Jieh-Tsorng Wu Fully Diﬀerential Operational Ampliﬁers

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Fully Balanced Circuit Topology

Vx1 Vi2 Vo1

Vi1 Vo2 Vx2

V = V − V V = (V + V )/2 vod = Adm Acdm vid id i1 i2 ic i1 i2 voc Adcm Acm vic = − = + Vod Vo1 Vo2 Voc (Vo1 Vo2)/2

• In practice, want Adm 1 Acm 1

• If the circuit is fully symmetrical,

= = Acdm 0 Adcm 0

Opamp-III 15-2 Analog ICs; Jieh-Tsorng Wu Fully Balanced Circuit Topology

• = − Signal is carried in Vxd Vx1 Vx2. Let

= + = − + = + − Vx1 A sin ωt n1 Vx2 A sin ωt n2 Vxd 2A sin ωt n1 n2

Assuming n1 and n2 are uncorrelated, then

A2/2 2 2 = = ⇒ = 2A = 2A = SNRx1 SNRx2 SNRxd 2SNRx1 n2 2 + 2 2n2 n1 n2

• Immune to common-mode noise, such as noises from power supplies and substrate.

• No even-order harmonic distortion in Vxd.

• = + Require additional common-mode feedback circuitry to set Vxc (Vx1 Vx2)/2.

Opamp-III 15-3 Analog ICs; Jieh-Tsorng Wu Small-Signal Models for Diﬀerential Loading

T-Network Model π -Network Model

i1 i1 DM Half Circuit CM Half Circuit v v 1 1 id Z Z d c 2 ic Z Z v 2 c d d vc 2 4 2 Zd Zd (-2Z c ) Z 2 c Zd 2 Zc v2 v2 i2 i2

v = v − v v = (v − v )/2 i = (i − i )/2 i = (i + i )/2 d 1 2 c 1 2 d 1 2 c 1 2 v v = d = c Zd Zc i = i = d vc 0 c vd 0

Opamp-III 15-4 Analog ICs; Jieh-Tsorng Wu Small-Signal Models for Diﬀerential Signal Sources

Thevenin-Network Model Norton-Network Model DM Half Circuit CM Half Circuit i i1 i1 d i v Z v 2 c 1 oc 1 vd Z vc od 2 Z 2 ioc od Zoc 2 Zoc Zod vod v 24 2 od voc 2 Zod (-2Z oc ) iod v i voc od d 2 2 ic vd Z vc od ioc 2 2 v2 Zoc v2 i2 i2 Z od i Z iod oc oc 2

v = A v v = A v i = G v i = G v od dm id oc cm ic od md id oc mc ic v v i i = od = oc = od = oc Adm Acm Gmd Gmc v = v = v = v = id iod 0 ic ioc 0 id vod 0 ic voc 0

Opamp-III 15-5 Analog ICs; Jieh-Tsorng Wu Common-Mode Feedback (CMFB)

Vo1 VCM Vod V V cfb nc 2 CM Voc T(s) Vcfb Detector Vod 2

Vo2

T 1 V = (V − V ) · T (s) V = V − V ⇒ V = × V + × V cf b oc CM oc nc cf b oc 1 + T CM 1 + T nc • Want large CMFB loop gain, T , to stabilize Voc.

• May want large ωt of T to suppress high-frequency components in Vnc.

• Must check the frequency stability of 1/[1 + T (s)].

Opamp-III 15-6 Analog ICs; Jieh-Tsorng Wu A Fully Diﬀerential Two-Stage Operational Ampliﬁer

VDD

M3 M4 V M6 B2 M8

Cc1 Cc2 Vo1 Vi1 M1 M2 Vi2 Vo2

M7 VB1 VB1 M5 VB1 M9

VSS VDD VDD

M3 M6 M3 M6

Cc1 Cc1 vi1 M1 vo1 vi1 M1 vo1

M7 M7 go5 Cx 2 2 DM Half Circuit CM Half Circuit

Opamp-III 15-7 Analog ICs; Jieh-Tsorng Wu CMFB Using Resistive Divider and Error Ampliﬁer

Common-Mode Feedback VDD VDD

M6 M8 IB1 IB2 IB3

C1 C2 Vo1 Vo2

MB1 MB2 R1 R2 VCM

VB1 M7 VB1 M9 MB5 MB6 MB3 MB4 VSS VSS

Opamp-III 15-8 Analog ICs; Jieh-Tsorng Wu CMFB Using Resistive Divider and Error Ampliﬁer

C1 M6 voc g inc1 mb1 2 Cc1 CL R1

inc2

M7 voc MB6 MB3 MB5

• | |≈ · The loop gain T gmb5(ro6 ro7) gmb1/(2gmb3).

• C1 and C2 are used to improve high-frequency response.

• ﬀ The resistive loading of R1 and R2 can degrade Adm. Voltage bu ers can be added between the opamp’s outputs and the resistive divider.

Opamp-III 15-9 Analog ICs; Jieh-Tsorng Wu CMFB Using Resistive Divider and Direct Current Injection

Common-Mode Feedback VDD VDD

M6 M8 IB1 IB2

C1 C2 Vo1 Vo2 VDD

R1 R2 MB1 MB2 MB3 VCM

VB1 M7 VB1 M9 IB3

VSS VSS

Opamp-III 15-10 Analog ICs; Jieh-Tsorng Wu CMFB Using Dual Diﬀerential Pairs

Common-Mode Feedback VDD VDD

M6 M8 IB3 IB4 IB1 IB2

Vo1 MB3 MB4 MB2 MB1 Vo2 I2 VCMI 1

I3 VB1 M7VB1 M9 MB6 MB5 MB7 MB8 VSS VSS

Opamp-III 15-11 Analog ICs; Jieh-Tsorng Wu CMFB Using Dual Diﬀerential Pairs

For the MB1-MB2 and MB3-MB4 source-coupled pairs, k W I = I = I = 2 × · V 2 k = k BB B3 B4 2 ov L k I I I I I I = V 4 BB − V 2 I = BB + dd I = BB − dd dd 2 id k id d1 2 2 d2 2 2 I k I I = BB + (V + V /2 − V ) 4 BB − (V + V /2 − V )2 1 2 4 oc od CM k oc od CM I k ≈ BB + (V − V + V /2) 4V 2 − (V /2)2 − (V − V )V 2 4 oc CM od ov od oc CM od I k ≈ BB + (V − V + V /2) 4V 2 − (V /2)2 2 4 oc CM od ov od    2  1 (V − V )V 1 (V − V )V × 1 − oc CM od − oc CM od + ···  2 2 − 2 8 2 − 2  4Vov (Vod /2) 4Vov (Vod /2)

Opamp-III 15-12 Analog ICs; Jieh-Tsorng Wu CMFB Using Dual Diﬀerential Pairs

I k I ≈ BB + (V − V − V /2) 4V 2 − (V /2)2 2 2 4 oc CM od ov od    2  1 (V − V )V 1 (V − V )V × 1 + oc CM od − oc CM od + ···  2 2 − 2 8 2 − 2  4Vov (Vod /2) 4Vov (Vod /2) k I = I + I ≈ I + (V − V ) 4V 2 − (V /2)2 3 1 2 BB 2 oc CM ov od    2 2  1 V 1 (V − V )V × 1 − od − oc CM od + ···  4 2 − 2 8 2 − 2  4Vov (Vod /2) 4Vov (Vod /2)

• The input devices, MB1–MB4, must remain in the forward-active region over the

voltage range of Vo1 and Vo2. • The variation in Vod can produce an ac component in I3 as well as Voc. • = = + If Voc VCM, I1 and I2 are nonlinear functions of Vod ,butI3 I1 I2 is a constant.

Opamp-III 15-13 Analog ICs; Jieh-Tsorng Wu CMFB Using Transistors in the Triode Region

Common-Mode Feedback VDD VDD

M6 M8 IB1 IB2 IB3

Vo1

Vo2 MB3 MB4 MB6

VxyV

VB1 M7VB1 M9 VCM MB5 I1 I2 MB1 MB2

VSS VSS

Opamp-III 15-14 Analog ICs; Jieh-Tsorng Wu CMFB Using Transistors in the Triode Region

= = = MB1, MB2, and MB5 are in the triode region. Let kB1 kB2 kB5 k, 1 1 1 I = k V − V − V V I = k V − V − V V I = k V − V − V V 1 o1 tn 2 x x 2 o2 tn 2 x x B3 CM tn 2 y y I ⇒ + = − − 1 ≈ = B3 I1 I2 2k Voc Vtn Vx Vx Vx Vy 2 k V − V − 1V CM tn 2 y − − 1 Voc Vtn Vx V − V I + I = 2I · 2 = 2I 1 + oc CM 1 2 B3 − − 1 B3 − − 1 VCM Vtn 2Vy VCM Vtn 2Vy

• + Output swing is reduced, since it is required that Vo1,o2 >Vtn Vx.

• ﬀ MB1 and MB2 are in the triode region, their e ective gm can be small, thus degrading loop gain and bandwidth of the CMFB.

Opamp-III 15-15 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor CMFB

Common-Mode Feedback VDD VDD

M6 M8 IB1 IB2 IB3 φ1

φ2

Vo1

Vo2

1 2 2 1 VCM VCM S5S1 S2 S6 I1 I2 C3 C1 C2 C4 1 2 Vx 2 1 VCB VB1 M7VB1 M9 VCB S7 S3 S4 S8 MB1 MB2 MB3

VSS VSS

− = − ⇒ ≈ Voc Vx VCM VCB Voc VCM

Opamp-III 15-16 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor CMFB

• ﬀ The opamp operates in two di erent modes. It is in the normal mode when φ2 is low.

• ﬀ Assuming ∆Q charges are injected into C3 and C4 when φ1 switches are turned o ,

− = − + ∆Q ⇒ ≈ + ∆Q Voc Vx VCM VCB Voc VCM C3 C3

• The loop gain of the CMFB is approximately

C |T |≈ 1 × g · R + m,B1 o1 C1 Cgs,B1

• ﬀ C1 and C2 add di erential-mode capacitive loading to the outputs.

• + + The additional common-mode capacitive loading is (C1 C2) (Cgs,B1 Cgs,B2).

• The value of C3,4 may be between 1/4–1/10 of C1,2 for low-pass ﬁlter function.

Opamp-III 15-17 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Ampliﬁer

VDD

M9 M10 VBP1

M3 M4 VBP2

Vo1

Vi1 M1 M2 Vo2

M6 VBN2MB3 V BN2 Vi2 M5 MB4

I1 M8 VBN1 MB1 CMFB M7 MB2

VSS

Opamp-III 15-18 Analog ICs; Jieh-Tsorng Wu Folded-Cascode Operational Ampliﬁer

• Frequency compensation is provided by the capacitive loads at the outputs.

• ≈ Non-dominant poles are determined by M3 and M4, and ωt3 (ωt4).

• It is not uncommon that ID1,D2 ID3,D4.

• For high-speed designs, use pMOST input stage. The resulting opamps has higher non-dominant poles.

• Active cascode conﬁguration can be applied to M3, M4, M5, and M6.

Opamp-III 15-19 Analog ICs; Jieh-Tsorng Wu Current-Mirror Operational Ampliﬁer

VDD

M3 M4M6 M5

M9 VBP2 M11 M10 M12 Vo1 Vi1 M1 M2 Vo2

Vi2 M13 VBN2 MB3 VBN2 M14 MB4

I1 M7 VBN1 MB1 CMFB M8 MB2

VSS

Opamp-III 15-20 Analog ICs; Jieh-Tsorng Wu Current-Mirror Operational Ampliﬁer

The M3-M5 and M4-M6 current mirrors have a current gain of K . W = W = 1 W = 1 W L 3 L 4 K L 5 K L 6 1 1 1 I = I = I = I = I = I = I D1 D2 D3 D4 K D5 K D6 2 1

• The single-ended maximum output current for slewing is

K I = I o(max) 2 1

• For a general-purpose fully diﬀerential opamp, may use large pMOST input stage, K=2, and wide-swing enhanced output-impedance cascode current mirrors.

Opamp-III 15-21 Analog ICs; Jieh-Tsorng Wu Current-Mirror Push-Pull Operational Ampliﬁer

VDD

K:1 1:1 1:1 1:K

M1 M2M4 M3 Vi1 Vi2 Vo1 Vo2

Vi2 Vi1

I1 I1 CMFB CMFB K:1 1:K

VSS

Opamp-III 15-22 Analog ICs; Jieh-Tsorng Wu Current-Mirror Push-Pull Operational Ampliﬁer

• The single-ended maximum output current for slewing is

= Io(max) KI1

• The small-signal response is slower due to additional signal paths.

Opamp-III 15-23 Analog ICs; Jieh-Tsorng Wu Class-AB Operational Ampliﬁer

VDD

K:1 1:K

M1 M2 Vi1 M3 M4 Vi2

Vo1 Vo2 M5M7 M8 M6

I I

I12I CMFB CMFB K:1 1:K

VSS

Opamp-III 15-24 Analog ICs; Jieh-Tsorng Wu Class-AB Operational Ampliﬁer

If nMOSTs M1–M4 are identical, and pMOSTs M5–M8 are identical, and all current mirrors have a current gain of K , then the bias currents are

1 1 I = I = I = I = I = I = I D1 D2 D3 D4 K 1 K 2

• Low quiescent power and large slew rate.

• The input level shifter increases the noise and oﬀset, and adds additional poles.

• Not suitable for low-voltage operation.

Opamp-III 15-25 Analog ICs; Jieh-Tsorng Wu Fully Diﬀerential Operational Ampliﬁers

VDD Telescopic-Cascode VDD

VDD VB1 Vb1 M8 M7 M9 M10 VB1 M8 M9 VB2 M7 M6 M5 Vb2 Vo2 Vo1 M3 M4 Vi1 M1 M2 Vi2 VB3 V V o1 o2 M4 M3 Vo1 Vo2 C C c2 c1 Vi1 M1 M2 Vi2 Vb3 VB2 M5 M6 Vi1 M1 M2 Vi2 M5 M3 M4 M6 Vb4 Vb4 M11 M7 M8

VSS VB4 M9 VSS Two-Stage Folded-Cascode VSS

= − = − − ∆Vo(Two Stage) VDD 2VDSAT ∆Vo(Telescopic) VDD 5VDSAT 3Vmargin = − − ∆Vo(Folded-Cascode) VDD 4VDSAT 2Vmargin Speed ∆V 2 g /C ∆V 2 SNR · ∝ o · m ∝ o · Power kT/C VDD I VDD

Opamp-III 15-26 Analog ICs; Jieh-Tsorng Wu Active-Cascode Telescopic Operational Ampliﬁer

VDD

VB1 • Have the best speed/power ratio. M8 M7 VPC • A1 and A2 auxiliary ampliﬁers are used to increase

output impedance and the dc voltage gain, Av (0).

M6 M5 A1 • Explicit compensation capacitors may be required at Vo2 Vo1 the outputs of A1 and A2. A2 M4 M3 • To increase ∆Vo, M7, M8, and M9, can be biased in the triode region. However, Av (0) is reduced due to the reduced r of M7 and M8. Also, CMRR and PSRR are VNC o degraded due to the reduced r of M9. Vi1 M1 M2 Vi2 o

• Reference: Gulati and Lee, JSSC 12/98, pp. 2010– VB4 M9 2019.

VSS

Opamp-III 15-27 Analog ICs; Jieh-Tsorng Wu Fully Diﬀerential Gain-Enhancement Auxiliary Ampliﬁers

A1 Aux AmplifierVDD A2 Aux Amplifier VDD

VB1 VB1 Vb1

Vo Vo Mb1 VB3 VDD VNC Vi Vi VB2 VPC Vi Vi VSS Ma1 Vo Vo VVB4 B4 Vb4

VSS VSS

• ≈ ≈ VS3 VS4 VNC, due to the CMFB of M3, M4, and A2.

• ≈ ≈ VS5 VS6 VPC, due to the CMFB of M5, M6, and A1.

Opamp-III 15-28 Analog ICs; Jieh-Tsorng Wu Replica-Tail Feedback

Vo2 Vo1 VDD A2 M4 M3 Ic VNC A3 Vbt Vy

VNC Cc Vi1 M1 M2 Vi2 M1r M2r Vi1

M9 M9r VDD VSS VSS VB1 VB1 A3 Aux Amplifier Vo Vo VB3 VNC VyiVi V

Vbt VB4 A2 Aux Amplifier

VSS VSS

Opamp-III 15-29 Analog ICs; Jieh-Tsorng Wu Replica-Tail Feedback

• The feedback loop increase M9’s output resistance, Ro9, i.e., = + · = + Ro9 ro9 1 A3 (gm9rro9r)(gm1r ro1r) ro9 1 Aloop

• It can be shown the eﬀective common-mode transconductance of M1-M2-M9 is

+ · 1 Aloop M g G G = G × M = 1 − m9 · mr e m + 1 Aloop gm9r Gm

g G = m g = g + g m + m m1 m2 1 gmro9 g G = mr g = g = g mr + mr m1r m2r 1 gmrro9r

• The mismatch M and the bandwidth of the feedback loop limit the enhancement eﬀect.

Opamp-III 15-30 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁers and Their Basic Conﬁgurations

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Ideal Operational Ampliﬁer Single-Ended Output Fully Differential

Vi Vo Vi Vo

A/2 x Vi A x V i Vcm A/2 x Vi

Vi Vi Vo

• = × Vo A Vi

• Ideal opamp: →∞ →∞ → Ð A , Zin , Zout 0. Ð No frequency dependence.

Opamps-BC 16-2 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁer Imperfections (I)

VDD

V IB1 OS Zic Z Vi+ o

I IOS Ve B Zid 2 AVe Vo Vi−

IB2 I B Zic

VSS

+ Vi+ Vi− Diﬀerential Input = V ≡ V + − V − Common-mode Input = V ≡ id i i ic 2

Opamps-BC 16-3 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁer Imperfections (II)

• Finite diﬀerential-mode gain, A ≡ dVo dm dVid = Vic 0 • Non-zero common-mode gain, A ≡ dVo cm dVic = Vid 0 Adm Common-Mode Rejection Ratio (CMRR) ≡ Acm

• Frequency response: Adm(s) and Acm(s).

• Input impedance: Zid and Zic.

• Output impedance: Zo.

• Power supply bias current: IDD.

Opamps-BC 16-4 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁer Imperfections (III)

• Input oﬀset voltage: V ≡ (V + − V −)| = OS i i Vo 0

• ≡ + Input bias current: IB (IB1 IB2)/2

• ﬀ ≡ − Input o set current: IOS IB1 IB2

• Input common-mode range: Vic(max) and Vic(min). Range of Vic for which ampliﬁer is operational.

• Output voltage range: Vo(max) and Vo(min).

• + − Maximum output currents: Io(max) and Io(max).

• + − Internal slew rate: SR and SR . Internally-limited rate of change in Vo in response to a step input.

Opamps-BC 16-5 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁer Imperfections (IV)

• Power supply signal gain: ADD(s) and ASS(s). Power supply rejection ratio (PSRR) are: A A ≡ dm ≡ dm PSRRDD PSRRSS ADD ASS

• Supply capacitance. Capacitive coupling between power supplies and the opamp’s input leads.

• Inherent noises in active devices and resistors.

Opamps-BC 16-6 Analog ICs; Jieh-Tsorng Wu Inverting Conﬁguration

Let Z = ∞ for the opamp, then I in Z − − − 1 V − V V − V V − = − = i − o = Vi Vo I I1 I 0 − Z1 Z I I = − × − 1 Vo A V − −AV

  V Z  1  Z 1 Closed-Loop Gain = A = o = −   = − CL + Vi Z1 1 + 1 1 + Z Z1 1 rr A Z1 V Z Z Input Impedance = Z = i = 1 ≈ 1 ic A I1 1 + CL 1 + 1 · − Z A A Z1

Opamps-BC 16-7 Analog ICs; Jieh-Tsorng Wu Inverting Conﬁguration

The error term, rr(s), is due to the ﬁnite opamp gain. = 1 + Z rr 1 A Z1

• rr(s) can be expressed in terms of magnitude and phase, i.e.,

= jϕrr(ω) ≈ + rr(jω) mrr(ω)e mrr(ω) jϕrr(ω)

• If rr 1, ≈−Z · − ACL (1 rr) Z1

Opamps-BC 16-8 Analog ICs; Jieh-Tsorng Wu Examples of Inverting Conﬁguration

Inverting Amplifier Inverting Integrator R C

R1 R1 Vi Vi Vo Vo

For the inverting ampliﬁer R 1 1 R A = − = 1 + CL + rr R1 1 rr A R1

For the inverting integrator 1 1 1 1 A = − = 1 + CL + rr sR1C 1 rr A sR1C

Opamps-BC 16-9 Analog ICs; Jieh-Tsorng Wu Inverting Summer Conﬁguration

Z 1 V 1 Vo

Z 2 V 2

Z N V N   N N Z  1  Z 1 V = − V ·   = − V · o i i + Zi 1 N Z Zi 1 rr i=1 1 + 1 + = i=1 A i 1 Zi

Opamps-BC 16-10 Analog ICs; Jieh-Tsorng Wu Noninverting Conﬁguration

ZB = ∞ Let Zin for the opamp, then IB − − ZA − V − V V − = − = o − V = Vo I IB IA 0 − ZB ZA I I = − × − − A Vo A (Vi V ) V i − − A(Vi V )   V Z  1  1 Closed-Loop Gain = A = o = 1 + B   = A (s) CL CL,∞ + Vi ZA 1 + 1 1 + ZB 1 rr A ZA Z Input Impedance = Z = Z (1 + T ) Output Impedance = Z = o ic i oc 1 + T Z T = Loop Gain = A × A + ZA ZB

Opamps-BC 16-11 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Applications

C2 C2 C C I 1 1 1 1Va o V i V o V i V o

2 2 CL Cp CL

φ1 Model During φ1 φ2

= − × For the opamp in closed-loop gain calculation, let Vo A Va. V V 1 C (V − V ) = C V + C (V − V ) ⇒ C V + o = −C o − C V + 1 1 i a p a 2 a o 1 i A p A 2 o A   + V C  1  C 1 1 C1 Cp A = o = − 1   = − 1 = 1 + CL C +C +C + rr Vi C2 1 + 1 1 2 p C2 1 rr A C2 A C2

Opamps-BC 16-12 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Step Response

= − For the opamp in step response calculation, let Io GmVa.

C (V − V ) = C V + C (V − V ) I = −G V = sC (V − V ) + sC V 1 i a p a 2 a o o m a  2 o a L o − · C2 − · C2 V C 1 s G C 1 s G ⇒ A = o = − 1  m  = − 1  m  CL (C +C )C +(C +C +C )C + · Vi C2 1 + s · 1 p 2 1 2 p L C2 1 s τa C2Gm (C + C )C + (C + C + C )C C + C + C C + [(C + C ) C ] = 1 p 2 1 2 p L = 1 2 p · L 1 p 2 τa C2Gm C2 Gm

G = = m = + + Open-Loop Unity-Gain Frequency ωu,OL CL CL [(C1 Cp) C2] CL C Feedback Factor = f = 2 + + C1 C2 Cp − = = · = 1 Closed-Loop 3 dB Bandwidth ωu,CL ωu,OL f τa

Opamps-BC 16-13 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Step Response

The closed-loop step response is − dVo Vstep = − t/τa = Vo(t) Vstep 1 e dt t=0 τa

The settling time is 1 V (t ) t = τ × ln = 1 − o settle settle a ∞ Vo( )

• × For <0.001, require tsettle > 6.9 τa.

• Total delay can be estimated by Vstep 1 t = t + t = + τ × ln d slew settle SR a

Opamps-BC 16-14 Analog ICs; Jieh-Tsorng Wu Analog Switches and Sample-and-Hold Circuits

Jieh-Tsorng Wu

October 8, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Sample-and-Hold (Track-and-Hold) Circuits

Switched-Capacitor S/H φ φ

V o V V V 1 i S/H o i M1 C L

φH

V o (k) V o

V i φ φL kTs

= + × + + Vo(k) (1 ) Vi (kTs ∆t) Vos

S/H 17-2 Analog ICs; Jieh-Tsorng Wu Sample-and-Hold (Track-and-Hold) Circuits

Impairments:

• Finite bandwidth in sample mode.

• Acquisition time and hold settling time.

• Aperture jitter ∆t.

• ﬀ Sampling pedestal (O set VOS and gain error ).

• Droop in hold mode.

• Feedthrough.

• Thermal Noise.

S/H 17-3 Analog ICs; Jieh-Tsorng Wu MOST Switches in Sample Mode

φ = φH

G C C gs gd SDV o V i g ’ on ’ C C C sb db L

W W g = µC (V − V ) = µC (ϕ − V − V ) on ox L GS t ox L H i t 1 1 C = C + WLC C = C + WLC gs ovs 2 ox gd ovd 2 ox 1 1 C = C + WLC (V ) C = C + WLC (V ) sb sb 2 J SB db db 2 J DB

S/H 17-4 Analog ICs; Jieh-Tsorng Wu MOST Switches from Sample to Hold Mode

φ V φH V i o φL C L G

Cov CCH Cov

S D Q CH

= + = + + Vo Vi ∆V (1 )Vi VOS

• ∆V is due to switch’s clock feedthrough and charge injection.

• ∆V depends on the waveform of φ.

• ﬀ Due to the ﬁnite slope of φ, the exact turn-o time of the switch depends on Vi .

S/H 17-5 Analog ICs; Jieh-Tsorng Wu Switching Errors in Slow-Gating MOST Switches

The body eﬀect of MOSTs can be approximately by = + + − ≈ + − Vt Vt0 γ VS 2φf 2φf Vt0 (n 1)Vs

• n is a constant, and 1

For slow gating (slow φ fall time), ∆V is due to the clock feedthrough after the switch is turned oﬀ.

C C ∆V = − ov (V + V − φ ) = − ov (nV + V − φ ) = V + V + i t L + i t0 L i OS Cov CL Cov CL C C ⇒ = −n · ov V = −(V − φ ) · ov + OS t0 L + Cov CL Cov CL

S/H 17-6 Analog ICs; Jieh-Tsorng Wu Switching Errors in Fast-Gating MOST Switches

For fast gating (fast φ fall time), assuming the channel charge QCH is divided equally between input and output, then

C 1 1 ∆V = −(φ − φ ) ov + Q = V + V H L + CH + i OS Cov CL 2 Cov CL = − · − − = − · − + − QCH CCH [(φH Vi ) Vt] CCH ( nVi φH Vt0) = · − CCH Cox W (L 2LD) n C C 1 C ⇒ =+ · CH V = −(φ − φ ) ov − (φ − V ) CH + OS H L + H t0 + 2 Cov CL Cov CL 2 Cov CL

• In practice, and VOS decrease with increasing fall time of φ.

• ﬀ The body e ect of Vt can cause nonlinearity.

S/H 17-7 Analog ICs; Jieh-Tsorng Wu MOST S/H Speed-Precision Tradeoﬀ

W On Conductance = g = µC V on ox L ov Vi Vi V Charge Injection = ∆Q = α · Q Q C L2 Q = C WLV = g · ox ov on µ

= = C Time Constant in Sampling Mode τon gon ∆Q αL2 ∆V αL2 Absolute Voltage Error = ∆V = = Relative Voltage Error = = C µτon Vi µτonVDD • Want Ts,on > 7τon for a 0.1% settling accuracy, where Ts,on is the sampling time.

• α can be reduced by compensation.

• Relative error ∆V/Vi is increased when reducing VDD.

S/H 17-8 Analog ICs; Jieh-Tsorng Wu Aperture Jitter Due to the Finite Falling Time

(k-1)Ts kTs

φ tf V DD φ Vi Vo

C Vi Vt

0t t

kTs V − (V + V ) V = × DD i t ≤ ≤ − t0 ∆t tf 0 ∆t tf 1 VDD VDD

• The jitter is input dependent, and introduces noise at output.

S/H 17-9 Analog ICs; Jieh-Tsorng Wu Thermal Noise in MOST S/H

R on m Ts Vi Vo Vi Vo

C C

S H Sn (f) Sn (f)

During sampling mode, the two-sided noise PSD at Vo is

1 1 4kTR 1 SS(f ) = S (f ) = · 4kTR ·|H(j2πf )|2 = · on B = n n on + 2 n 2 2 1 (2πf RonC) 4RonC

• = For sampling rate fs 1/Ts, want

7 1 T = m · T > 7 · R C ⇒ B > · · f or B ≥ 5f s,on s on n 4 m s n s

S/H 17-10 Analog ICs; Jieh-Tsorng Wu Thermal Noise in MOST S/H

During the hold mode, the noise is sampled and the noise PSD is

∞ 2B 1/(2R C) kT 1 SH(f ) = S (f − i · f ) ≈ n × S (f ) ≈ on × 2kTR = · n n s f n f on C f i=−∞ s s s

• It is assumed that Bn fs.

• − ≤ ≤ The total noise power in the baseband fs/2 f fs/2 is hence kT/C.

• Want large C for low-noise performance.

• Reference: Roubik Gregorian and Gabor Temes, “Analog MOS Integrated Circuits for Signal Processing,” John Wiley & Sons, Inc., 1986.

S/H 17-11 Analog ICs; Jieh-Tsorng Wu Charge Compensation for MOST Switches

φφφ φ V M1 o M2 M1 V o M2 V V i i R R S ∆Q1 ∆Q2 S ∆Q1 ∆Q1 ∆Q2 C C C L L L

Dummy Switch Dummy Switch with Equalizing Capacitor

Design the M2 dummy switch so that

1 L = L W = W 2 1 2 2 1

Then 1 ∆Q = ∆Q + α∆Q ∆Q = ∆Q + ∆Q 1 ov1 CH1 2 ov1 2 CH1

• The problem is that α is not exactly 1/2.

S/H 17-12 Analog ICs; Jieh-Tsorng Wu Diﬀerential Sampling

V V − = + + − + + i1 o1 Vo1 Vo2 [Vi1(1 1) VOS1] [Vi2(1 2) VOS2] M1 C = (V − V )[1 + ] + (V + V ) + V L i1 i2 D i1 i2 C OS + = 1 2 = Diﬀerential-Mode Gain Error D 2 − Vi2 Vo2 1 2 M2 = = Common-Mode Gain Error C 2 C L = − = ﬀ VOS VOS1 VOS2 O set

• The switching errors of M1 and M2 at Vo1 and Vo2 are to the ﬁrst order equal and hence appear as a common-mode component at the output.

• Good CMRR and PSRR. Less sensitive to φ waveform.

• ﬀ = The body e ect can cause C 0 as well as nonlinearity.

S/H 17-13 Analog ICs; Jieh-Tsorng Wu Bottom-Plate Sampling

φ The charge in C can be expressed as M1 Vi Vo = · QC(A) C Vi (t) Q 1 = · − C QC(B) C Vi (kTs) ∆Q2 x Q (C) = C · V (kT ) − ∆Q + ∆Q ≈ C · V (kT ) − ∆Q Q2 C i s 2 1 i s 2 φa M2 • The switching charge ∆Q2 is independent of Vi , and contains little noise due to aperture jitter.

φ • Since node x is ﬂoating during period B and C, the ≈ switching charge ∆Q1 0. φa

ACB • Parasitic capacitance from node x to ground can enhance ∆Q1. kTs

S/H 17-14 Analog ICs; Jieh-Tsorng Wu Complementary Analog Switches

g n g ABABV p DD V V ii V i 01V DD gap

W W g = µC (V − V − V ) = β(V − V − nV ) β = µC V = V + (n − 1)V on ox L g s t g t0 s ox L t t0 s = − − = − − − gn βn[VDD Vt0,n nnVi ] gp βp[VDD Vt0,p np(VDD Vi )] + nnVt0,p npVt0,n 2V V = V = t0 if n = n and V = V DD(min) + − DD(min) − n p t0,n t0,p nn np nnnp 2 n

• If VDD >VDD(min), no gap between gn and gp curves, thus conduction for any Vi is possible by parallel connection of nMOST and pMOST.

S/H 17-15 Analog ICs; Jieh-Tsorng Wu ADiﬀerential BJT Sampling Switch

VCC

Q3 Q4 CF R3 R4 CF CF

Q5 Q6 V o- V o+ V i+ Q1 Q2 V i-

CH CH φ Q7 Q8φ R1 R2 φ Q9 Q10 φ

I 22I 1 I

VEE

S/H 17-16 Analog ICs; Jieh-Tsorng Wu ADiﬀerential BJT Sampling Switch

• The nonlinearities of Q1 and Q2 are canceled by Q3 and Q4.

• The diﬀerential operation results in only odd harmonics introduced by the Q5 and Q6 followers.

• During hold mode (φ = 0), Q5 and Q6 are in cut-oﬀ region, the feedthrough gain is Cje5 Cje5 C A (Without C ) ≈ A (With C ) ≈ 1 − F H F + H F + CL Cje5 CL Cje5 Cje5

• Reference: P. Vorenkamp, et al., Fully Bipolar 120 MS/s 10-b Track-and-Hold Circuit, JSSC 7/92, pp. 988–992.

S/H 17-17 Analog ICs; Jieh-Tsorng Wu Open-Loop MOST S/H

M2 C φφH2

A1 V o A1 V o V i V i M1 M1 C C H1 H1

• M2 and CH2 are used to compensate for the switching error of M1.

• The VOS of the opamp is shown in Vo.

• The aperture jitter can be reduced by having clock signals that change above and

below Vi by ﬁxed amounts.

S/H 17-18 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Miller Holding Capacitor

φ φ 1 2 Sample Mode Hold Mode M3 V i V i M1 φ1 C C C H H H

M2 V1 V1 A1 V o A1V o A1 V o

VOS VOS φ1

φ2 = = φ1 1 φ2 1 t1 t2

S/H 17-19 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Miller Holding Capacitor

ﬀ = ∞ = To consider the VOS e ect, let A1 and Vi 0, then

= = − Vo(t1) VOS(t1) Vo(t2) VOS(t2) VOS(t1)

• The VOS is sampled in the sample mode, and canceled in the hold mode.

ﬀ = To consider the ﬁnite gain e ect, let VOS 0, then during the hold mode, V 1 V − V = V V = −A V ⇒ V = i ≈ V · 1 − o 1 i o 1 1 o 1 i 1 + A1 A1

• The Vo is reset to ground in sample mode. High slew-rate opamp is required.

• The virtual ground is not ideal at high frequencies in the sample mode.

• The switching errors are concerns.

S/H 17-20 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Miller Capacitor and Bottom-Plate Sampling

Sample Mode Hold Mode 1 Vi1 Vi1 S1 C C C L1 L1 L1 C C C H1 H1 H1 S3 1a 2 Vo1 Vo1 Vo1 S5 VCMI 1a 2 VCMI Vo2 Vo2 Vo2 S4 S6

C C C H2 H2 H2 C C C 1 L2 L2 L2 Vi2 Vi2 S2 = = φ1 1 φ2 1

S/H 17-21 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Miller Capacitor and Bottom-Plate Sampling

• The opamp is open-loop during the sample mode. Glitches can occur during the transition from the sample mode to the hold mode.

• VOS of the opamp is not canceled.

• The outputs, Vo1 and Vo2, are precharged to Vi1 and Vi2 during the sample mode, so that the settling time in the hold mode can be reduced.

• ﬀ + The input common-mode voltage, VCMI, can be di erent from the value of (Vi1 Vi2)/2.

• + The VCMO of the opamp’s CMFB should closely follow the value of (Vi1 Vi2)/2.

• The mismatches of the switching errors of S3–S8 can introduce a constant oﬀset voltage in the outputs.

S/H 17-22 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Double Miller Capacitors

φ Sample Mode Hold Mode Q 1 V i V o V i V o M1 φa C C C C C C H1 H2 H1 H2 H1 H2 Q 2 M2 V 1 A1 A1 A1 V 2

φ = 1 φ = 0 φ φa

S/H 17-23 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Double Miller Capacitors

ﬀ Let ∆Q2 be the charge injecting to V1 when M2 turns o . Then

= − ≈ = − ∆Q2 CH1(∆V1 ∆Vo) ∆Vo ∆V2 A1∆V1 1 ∆Q A ∆Q ⇒ ∆V = · 2 ∆V = − 1 · 2 1 + o + 1 A1 CH1 1 A1 CH1

• ∆Q2 is independent of Vi .

ﬀ Let ∆Q1 be the charge injecting to Vo when M1 turns o . Then

= − + − ≈ = − ≈− ∆Q1 CH1(∆Vo ∆V1) CH2(∆Vo ∆V2) ∆V1 ∆Vo ∆V2 A1∆V1 A1∆Vo 1 ∆Q ⇒ ∆V = · 1 o + 1 A1 CH2

• Small CH1 and CH2 can be used.

S/H 17-24 Analog ICs; Jieh-Tsorng Wu MOST S/H Using Double Miller Capacitors

• The VOS is sampled in the sample mode, and canceled in the hold mode.

• The opamp’s output has small voltage variation. Thus, it is easier to design the opamp for high speed.

• Suitable for high speed.

S/H 17-25 Analog ICs; Jieh-Tsorng Wu A MOST Recycling S/H

φ1 φ2 Sample Mode Hold Mode V V i o V i V o V o M1 M2 φ1 B1 B2 B1 B1 a M3 φ1 C C C C C C H1 H2 H1 H2 H1 H2

A1 A1 A1 M5 a a φ C φ 1 H3 1 CLK φ1 a φ1

φ1 φ2 φ2 a φ2

S/H 17-26 Analog ICs; Jieh-Tsorng Wu A MOST Recycling S/H

• B1 and B2 are two unity-gain buﬀer.

• M5 and CH3 is to compensate for the M4’s switching error.

• ﬀ The switching errors of M1 and M2 does not a ect Vo.

• ﬀ ﬀ The switching error of M3 does a ect Vo. But its e ect is reduced by the opamp’s voltage gain.

• ﬀ Mismatch between B1 and B2 can a ect Vo.

S/H 17-27 Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H

A1 1 V o V i M1 C H

S/H 17-28 Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H

• The circuit is in the track mode when φ = 1, and is in the hold mode when φ = 0.

• High input impedance.

• The oﬀset and gain of the output buﬀer are not critical.

• The input oﬀset of the A1 opamp is not canceled.

• The speed can be seriously degraded due to the necessity of guaranteeing that the loop is stable in the track mode.

• The A1 opamp is open loop when in the hold mode. It takes time to recover the bias when switches to the track mode.

S/H 17-29 Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H with Improved tslew

φ M3

A1 1 V o V i M1 C H

• During hold mode, A1 is conﬁgured as a unity-gain ampliﬁer. Thus, the slewing time is greatly minimized.

S/H 17-30 Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H Using Active Integrator

C φ H1

A1 V i M1 A2 V o

φ φ M3 M2 C H2

S/H 17-31 Analog ICs; Jieh-Tsorng Wu Closed-Loop S/H Using Active Integrator

• When in the track mode, the voltage on both sides of M1 are closed to ground, and are nearly signal independent.

• Aperture jitter is minimized.

• ﬀ The switching error of M1 causes a dc o set in Vo, which will be signal independent.

• M2 and CH2 are to compensate for the M1 switching error.

• When in the hold mode, M3 clamps the A1’s output to ground, speeding up the time it takes the S/H to return to the tack mode.

• M3 also reduces signal feedthrough when in the hold mode.

• The speed is degraded because of the necessity to guarantee stability in the track mode.

S/H 17-32 Analog ICs; Jieh-Tsorng Wu An RC Closed-Loop S/H

R C φ H R V i M1 A1 V o φ M2

• The A1 opamp need to have low output impedance.

S/H 17-33 Analog ICs; Jieh-Tsorng Wu A Switched-Capacitor Closed-Loop S/H

φ φ 1 2 Sample Mode φ = 1 V i 1 V i C C M1 M4 H1 H3 a C C H3 H1 φ2 A1 M5 A2 Vo a A1 V φ1 M2 A2 o C C H4 a H2 M3 φ2 M6 C C H4 H2 φa 1 = Hold Mode φ2 1

C C H3 H1 φ1

φ2 A1 a A2 Vo φ1 C a H2 φ2

S/H 17-34 Analog ICs; Jieh-Tsorng Wu A Switched-Capacitor Closed-Loop S/H

• The Vo is always valid.

• The VOS1 of A1 is stored in CH2 during the sample mode.

• The M2’s switching error is canceled by M3.

• The M5’s switching error is canceled by M6.

• ﬀ The switching error of M1 and M4 doesn’t a ect Vo.

S/H 17-35 Analog ICs; Jieh-Tsorng Wu Charge Redistribution Sampled-Data Ampliﬁer

C C C 2 2 2

a Q 1 S3 1 V1 V V V V V i o i o o S1 C C C 1 1 1 2 S2 V V V OS OS OS

= = a φ1 1 φ2 1 φ1

φ1

φ2

t1 t2

S/H 17-36 Analog ICs; Jieh-Tsorng Wu Charge Redistribution Sampled-Data Ampliﬁer

= ∞ = To consider the ideal case, let A and VOS 0, then

= Vo(t1) 0 C = ⇒ = 1 × C1Vi (t1) C2Vo(t2) Vo(t2) Vi (t1) C2

ﬀ = ∞ To consider the VOS e ect, let A , then

V (t ) = V (t ) o 1 OS 1 C C V (t ) = 1 × V (t ) + V (t ) + 1 + 1 × V (t ) − V (t ) o 2 C i 1 OS 1 C OS 2 OS 1 2 2 C C C = 1 × + 2 · + + 1 × − Vi (t1) VOS(t1) 1 VOS(t2) VOS(t1) C2 C1 C2

• ﬀ · The input referred o set is VOS (C2/C1).

S/H 17-37 Analog ICs; Jieh-Tsorng Wu Charge Redistribution Sampled-Data Ampliﬁer

ﬀ = = To consider the ﬁnite gain e ect, let VOS 0, then during φ2 1

C + = − = − ⇒ = 1 · 1 × C1Vi C1V1 C2(Vo V1) Vo AV1 Vo Vi C2 1 + 1 1 + C1 A C2

ﬀ = ∞ = = To consider the e ect S3 switching error, let A , VOS 0, and Vi 0, then during = φ2 1 = = −∆Q Vo VOS C2

• VOS is independent of input.

• ﬀ If S3 is opened before S1, the switching errors of S1 and S2 have no e ect on Vo.

S/H 17-38 Analog ICs; Jieh-Tsorng Wu Charge Redistribution Summing Ampliﬁer

C 3 = During the sample mode (φ1 1) a 1 1 = V S5 Vo VOS i1 S1 V o = 2 C During the hold mode (φ2 1) V 1 i2 S2 V OS C = 1 − 1 Vo (Vi1 Vi2) V C3 i3 S3 C + 2 − + (Vi3 Vi4) VOS 2 C C V 2 3 i4 S4

S/H 17-39 Analog ICs; Jieh-Tsorng Wu Sampled-Data Ampliﬁer with CDS

C C C 2 1 2 2 S5 S4 a 2 1 S3 2 V1 V V V V V i o o i o S1 C C C 1 1 1 1 S2 V V V OS OS OS

= = a φ1 1 φ2 1 φ1

φ1

φ2

t1 t2

S/H 17-40 Analog ICs; Jieh-Tsorng Wu Sampled-Data Ampliﬁer with CDS

Let A = ∞, then

V (t ) = V = V = V (t ) o 1 c1 c2 OS 1 C C = − 1 × + + 1 − Vo(t2) Vi (t2) 1 [VOS(t2) VOS(t1)] C2 C2

• − − The correlated double-sampling (CDS) technique, resulting in VOS(nTs) VOS(nTs ﬀ ﬀ Ts/2), can reduce the e ects of the opamp’s input o set voltage and its 1/f noise.

• To minimize switching noises, realize switches with nMOSTs whenever possible, and turn oﬀ the switches near the virtual ground node of the opamps ﬁrst.

• Reference: C. Enz and G. Temes, “Circuit Techniques for Reducing the Eﬀects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization,” Proc. IEEE, Nov. 1996, pp. 1584–1614.

S/H 17-41 Analog ICs; Jieh-Tsorng Wu A Capacitive-Reset Sampled-Data Ampliﬁer

a C C C 2 3 3 3 S6 S5 1a C C C 2 1 2 2 S4 S3 2 2 V1 V1 V V V V V i o o i o S1 C C C 1 1 1 1 S2 V V V OS OS OS C 4 = = φ1 1 φ2 1 a φ1 a φ2

φ1

φ2

t1 t2 t3 t4

S/H 17-42 Analog ICs; Jieh-Tsorng Wu A Capacitive-Reset Sampled-Data Ampliﬁer

ﬀ = ∞ = To consider the VOS e ect, let A and Vi 0, then

V (t ) = V (t ) 1 1 OS 1 C V (t ) = 1 + 1 × V (t ) − V (t ) o 2 C OS 2 OS 1 2 C C + C V (t ) = V (t ) + V (t ) + 2 × V (t ) + 1 + 1 2 × V (t ) − V (t ) ≈ V (t ) o 3 OS 3 o 2 C o 2 C OS 3 OS 2 OS 3 3 3 C = + 1 × − Vo(t4) 1 VOS(t4) VOS(t3) C2

• = ﬀ During φ2 1, the e ects of opamp’s VOS and 1/f noise are reduce by CDS.

S/H 17-43 Analog ICs; Jieh-Tsorng Wu A Capacitive-Reset Sampled-Data Ampliﬁer

ﬀ = To consider the ﬁnite gain e ect, let VOS 0, then

−C V (t ) − C V (t ) = C [V (t ) − V (t )] + C [V (t ) − V (t )] V = −V /A 1 1 1 2 1 1 1 i 2 1 2 2 o 2 1 2 1 o C C ⇒ = − 1 · 1 × + 1 + 1 · 1 × Vo(t2) Vi (t2) 1 Vo(t1) C2 1 + 1 1 + C1 A C2 1 + 1 1 + C1 A C2 A C2 C ≈− 1 − × + − × (1 1) Vi (t2) 1(1 1) Vo(t1) C2 C C C ≈ − + 1 − + 2 − ≈ ≈− 1 Vo(t3) (1 2)Vo(t2) (1 2)Vi (t2) (1 3)Vo(t2) Vo(t2) Vi (t2) C3 C3 C2 C ≈− 1 − × + − × Vo(t4) (1 1) Vi (t4) 1(1 1) Vo(t3) C2 C C C ≈− 1 × V (t ) + 1 × [V (t ) − V (t )] + 2 1 × V (t ) C i 4 1C i 4 i 2 1C i 2 2 2 2 C C C = 1 + 1 = 1 + 1 = 1 + 2 1 1 2 1 3 1 A C2 A C3 A C3

S/H 17-44 Analog ICs; Jieh-Tsorng Wu A Capacitive-Reset Sampled-Data Ampliﬁer

• = ﬀ During φ2 1, the e ects of opamp’s VOS and 1/f noise are reduce by CDS.

• = 2 During φ2 1, the errors due to opamp’s ﬁnite gain, A, are proportional to 1/A for low-frequency input.

• = = During φ1 1, the output keeps the value obtained in the previous φ2 1 period.

• C4 is an optional deglitching capacitor used to provide continuous-time feedback during the nonoverlap clock times. This capacitor would normally be small.

• The clock phases for S1 and S2 can be exchanged, to obtain noninverting gain.

• When CDS is used, the opamps should be designed to minimize thermal noise rather than 1/f noise.

S/H 17-45 Analog ICs; Jieh-Tsorng Wu A Capacitive-Reset CDS Ampliﬁer

= C φ1 1 2

C 1 V o S5 C 1 A 2 2 C’ C’ S7 1 2 S3 V 1 i 2 V V i o S1 C C 1 φ = 1 2 S9 2 C’ 1a C’ 1 2 1 1 C 1 S2 S8 V V i o S4 S10 S6 2 2a 2 A C’ C’ 1 2

S/H 17-46 Analog ICs; Jieh-Tsorng Wu A Capacitive-Reset CDS Ampliﬁer

• = During φ1 1, C1 and C2 are used in the feedback network to have

C ≈− 1 · Vo Vi C2

but with errors due to VOS,1/f noise, and A.

• = During φ1 1, the opamp input voltage is sampled and stored in C1 and C2.

• = During φ2 1, C1 and C2 are used in the feedback network, the output errors due to VOS,1/f noise, and A are canceled by the correlated double-sampling (CDS) operation.

S/H 17-47 Analog ICs; Jieh-Tsorng Wu Comparators and Oﬀset Cancellation Techniques

Jieh-Tsorng Wu

October 25, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Comparators

Vi1 V o Typical Architecture Vi2

Vi1 V oVA Latch o Vi2

CLK Vi1 Vi2 0

• A comparator compare the instantaneous values of two inputs generate a digital 1 or 0 level depending on the polarity of the diﬀerence.

• Usually a clock is applied to improve the performance.

Comparators 18-2 Analog ICs; Jieh-Tsorng Wu Comparator Design Considerations

• Resolution (gain).

• Accuracy (oﬀset).

• Input range (dynamic range).

• Common-mode rejection.

• Speed (conversion time, over-drive recovery).

• Power dissipation.

• Input kickback noise.

• Area

Comparators 18-3 Analog ICs; Jieh-Tsorng Wu Comparison with Single-Pole Ampliﬁer

Vo Vo Vi Ao Vi R C U

g t m V i t a Vo − C U = = A 1 − e ta/(RC) A = g Rτ= V o o m m g i   m t 1 t a = A × ln   ⇒ a ≈ U if U A o U o τm 1 − τm Ao

• The ampliﬁcation in a comparator need not be linear.

Comparators 18-4 Analog ICs; Jieh-Tsorng Wu Comparison with Multi-Stage Cascaded Ampliﬁer

Vo1 Vo2 Vo

V i R C R C R C

g g g m V i m V o1m V o(N−1)

ta 1 ≈ × N (U N!) for ta Aoτm τm

• There exits an optimum number of cascaded stages for minimum ta.

• Optimum in N is very broad. √ • Gain of 10 (i.e. 10 dB) per stage results in near optimum delay (within 10%).

Comparators 18-5 Analog ICs; Jieh-Tsorng Wu Comparison with Positive-Feedback Regeneration

Vo(t) V o V (0) Vo1 Vo2 o

t g C R m g R C t m a

− Vo(ta) (Ao 1)ta C = = RC = = U e Ao gmRτm Vo(0) gm t 1 t a = × ln(U) ⇒ a ≈ ln(U)ifA 1 1 o τm 1 − τm Ao

Comparators 18-6 Analog ICs; Jieh-Tsorng Wu Comparison with Positive-Feedback Regeneration

• The gain is not bounded by Ao.

• It is faster than the multi-stage cascaded ampliﬁer, and dissipates less power.

• Require a strobe signal (clock).

• = Let Tc be the conversion time, the ﬁnal output Vo(Tc) V , and the initial sampled − + input Vo(0) has a uniform distribution between V and V . Then the probability of observing a metastable state is

T V/U 1 −(Ao−1)Tc − c P = = = e RC ≈ e C/gm V U

The metastable state occurs when the sampled input is so small that the regenerated | | | | output, Vo , cannot reach V after the Tc period.

Comparators 18-7 Analog ICs; Jieh-Tsorng Wu Output Oﬀset Storage (OOS)

V V 2 c o V i Latch V’ S1 o A C Q S2 o C 1 S3 L V OS V OSL 1a

= During the reset mode (φ1 1)

= = × Vo 0 Vc A VOS

= During the ampliﬁcation mode (φ2 1) C ∆Q C ∆Q V C + C V = V × A · o + − V = A · o V + − OSL · o L o i + + OSL + i Co CL Co CL Co CL ACo A Co V C + C ﬀ = = 1 · ∆Q − OSL · o L Input-Referred O set VOS,in A Co A Co

Comparators 18-8 Analog ICs; Jieh-Tsorng Wu Output Oﬀset Storage (OOS)

• During the reset-to-ampliﬁcation transition, let S3 open before S2, so that ∆Q can be a constant.

• Ampliﬁer A cannot employ high gain.

• Ampliﬁer A must cover the input common-mode range.

• Want latch with high-impedance (capacitive) input so as not to discharge Co during ampliﬁcation.

• Make Co CL to avoid attenuation.

Comparators 18-9 Analog ICs; Jieh-Tsorng Wu Multistage Output Oﬀset Storage

S1 V V V c1 X c2 Y c3 V V i o C C C A1 1 A2 2 A3 3 V OS1 V OS2 V OS3 S2 S3 S4 S5

S2 S3

I II III IV V

Comparators 18-10 Analog ICs; Jieh-Tsorng Wu Multistage Output Oﬀset Storage

During Period I, S1 open, S2ÐS5 closed.

= = = Vc1 A1VOS1 Vc2 A2VOS2 Vc3 A3VOS3

During Period II, S3 open.

= = = + = − VX 2 S3 Switching Error Vc1 A1VOS1 2 Vc2 A2(VOS2 2)

During Period III, S4 open.

= = = − + = − VY 3 S4 Switching Error Vc2 A2(VOS2 2) 3 Vc3 A3(VOS3 3)

During Period IV, S5 open.

= = = − + Vo 4 S5 Switching Error Vc3 A3(VOS3 3) 4

Comparators 18-11 Analog ICs; Jieh-Tsorng Wu Multistage Output Oﬀset Storage

During Period V (ampliﬁcation mode), S2 closed, S1 open.

= · · · + Vo A1 A2 A3 Vi 4 V = 4 OS,in · · A1 A2 A3

Comparators 18-12 Analog ICs; Jieh-Tsorng Wu Input Oﬀset Storage (IOS)

1a Q S3 V V 2 c o V V’ i Latch o S1 Ci A S2 C 1 L V OS V OSL

= During the reset mode (φ1 1) A V = V = V × o c OS A + 1 = During the ampliﬁcation mode (φ2 1) A ∆Q V ∆Q V V = −V × A + V − A − V = −A V − OS + + OSL o i OS + OSL i + A 1 Ci A 1 Ci A V ∆Q V Input-Referred Oﬀset = V = − OS + + OSL OS,in + A 1 Ci A

Comparators 18-13 Analog ICs; Jieh-Tsorng Wu Input Oﬀset Storage (IOS)

• The S3 switching error ∆Q is input-independent.

• During the reset-to-ampliﬁcation transition, let S3 open before S2.

• The IOS allows rail-to-rail input common-mode level and quick overdrive recovery.

• Ampliﬁer A can employs high gain.

• Amplifier A may require compensation Cc to ensure closed-looped stability. Cc can be switched off during the amplification mode.

Comparators 18-14 Analog ICs; Jieh-Tsorng Wu Multistage Input Oﬀset Storage

V S3 V S4 S1 c1 c2 V V i o C C X 1 A1 2 A2 V OS1 V OS2

I II III IV

Comparators 18-15 Analog ICs; Jieh-Tsorng Wu Multistage Input Oﬀset Storage

During Period I, S1 open, S2ÐS4 closed.

A A A A V = 1 V V = 2 V − V = 2 V − 1 V c1 + OS1 c2 + OS2 c1 + OS2 + OS1 A1 1 A2 1 A2 1 A1 1

During Period region II, S3 open. Let 1 be the 3 switching error.

A A A V = 1 V + V = 2 V − 1 V + A c1 + OS1 1 c2 + OS2 + OS1 1 1 A1 1 A2 1 A1 1

During Period III, S4 open. Let 2 be the S4 switching error.

A A A V = 2 V − 1 V + A + V = 2 V − A c2 + OS2 + OS1 1 1 2 o + OS2 2 2 A2 1 A1 1 A2 1

Comparators 18-16 Analog ICs; Jieh-Tsorng Wu Multistage Input Oﬀset Storage

During Period IV (ampliﬁcation mode), S2 open, S1 closed. A V V = A A V + 2 V − A = A A V + OS2 − 2 o 1 2 i + OS2 2 2 1 2 i + A2 1 A1(A2 1) A1 V Input-Referred Oﬀset = V = OS2 − 2 OS,in + A1(A2 1) A1

Comparators 18-17 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Auto-Zeroing Inverter

VDD V o 2 V i1 MA S1 X 1 V o 1 C S3 V I Bias Point i2 MB S2 V x VSS

Comparators 18-18 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Auto-Zeroing Inverter

• Trade-oﬀ between speed and resolution by selecting diﬀerent value of C.

• Very sensitive to supply noises.

• Power dissipation is strongly process- and supply-dependent.

• Kickback noise presented at the inputs.

• Reference: T. Kumamoto, et. al., JSSC, 12/86, pp. 976Ð982.

Comparators 18-19 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Cascaded Auto-Zeroing Inverters

VDD VDD

V i1 M1 M3 S1 Latch V o C S3C S4 V 1 2 i2 M2 M4 S2

VSS VSS CK

Comparators 18-20 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Preamp + Regenerative Sense Ampliﬁer

VDD

M3 M5

M4 M6

V o

V i1 M1 M2

V i2 M7 M8 M9 M10

VDD I 1 M11φ M12 VSS VSS VSS

Comparators 18-21 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Preamp + Regenerative Sense Ampliﬁer

• = During the track mode (φ 1), want gm7,m8

• During the latch mode (φ = 0), M7, M8, and M11 must be large enough to prevent

the change of latched state by the Vi variation.

• All nodes are low impedance, thus giving fast operation.

• Overdrive recovery can be improved by adding an equalizing switch between the Vo nodes.

• The preampliﬁer buﬀers the kickback from the input circuitry.

• Reference: B. Song, et al., JSSC, 12/90, pp. 1328Ð1338.

Comparators 18-22 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Preamp + Regenerative Sense Ampliﬁer

VDD VDD

φ M13 M3 M5

M4 M6 M11 M12

IVT1 A

V o V i1 M1 M2 B IVT2 V i2 M8 M7 φ M9 M10 I 1 VSS VSS VSS

Comparators 18-23 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Preamp + Regenerative Sense Ampliﬁer

• During the track mode (φ = 1), need M7 and M8 large enough to overpower the M9-

M10 cross-coupled pair and pull VA and VB below the input threshold level of IVT1 and IVT2.

• During the latch mode (φ = 0), the M9-M10 and M11-M12 pairs provide regeneration.

They must be large enough to to prevent the change of latched state by the Vi variation. The input threshold level of IVT1 and IVT2 must be high enough to avoid false triggering.

Comparators 18-24 Analog ICs; Jieh-Tsorng Wu MOST Comparator: Merged Preamp + Sense Ampliﬁer

VDD

• No power dissipation when M5 M6 M7 M8 CK=0. M9 M10 CK CK • When CK=1, the M1-M2 pair is V o activated ﬁrst, the M3-M4 pair is second, and the M5-M6 pair is M3 M4 the last.

• Kickback noise is generated at M1 M2 input during the 0-to-1 transition Vi of CK.

• Reference: B. Razavi, 1999 CK M11 ISSCC Short Course.

VSS

Comparators 18-25 Analog ICs; Jieh-Tsorng Wu Oﬀset Canceled Latches: Idea

S3 S1 1 RL1 S5

V i 2 V o 1 G S2 Gm1 m2 S6 S4 1 RL2 C2

• = During reset mode (φ1 1), the OOS is applied to both Gm1 and Gm2.

• During reset mode, the ﬁnite on-resistance of S5 and S6 may cause oscillation.

• During reset-to-regeneration transition, any mismatch of the switching errors between S5 and S6 can trigger a false regeneration, yielding a large input-referred oﬀset.

Comparators 18-26 Analog ICs; Jieh-Tsorng Wu Oﬀset Canceled Latches: Simpliﬁed Schematic

B1 C1 1 S7

S3 S1 1 RL1 S9 S5 2 1

V i 2a V o

G G 1 S6 S2 m1 m2 S10 S4 2 1 RL2 1 S8 C B2 2

Comparators 18-27 Analog ICs; Jieh-Tsorng Wu Oﬀset Canceled Latches: Simpliﬁed Schematic

• During reset mode, the positive feedback loop is completely broken.

• The regeneration begins only after Vi has been sensed and ampliﬁed.

• ﬀ Bu ers B1 and B2 isolate output nodes from C1 and C2, thus enhancing regeneration speed.

• The residual oﬀset is primarily cause by the switching errors of S5ÐS10.

• Reference: B. Razavi, et al., “Design Techniques for High-Speed High-Resolution Comparators,” JSSC, 12/92, pp. 1916Ð1926.

Comparators 18-28 Analog ICs; Jieh-Tsorng Wu Oﬀset Canceled Latches: MOST Implementation

VDD

M7M5 M6 M8

M9 M10 AB C1 C2 C MS9EFD MS10 V o+ V o- MS7M3 M4 MS8 I3 I4 MS5 MS6 VSS VSS V B1 I2 V B1 VSS φ1 φ1 φ2 φ2 φ1 φ1 MS1 MS2 V 1+ M1 M2 V 1-

V 2+ V 2- MS3 MS4 I1 φ1 φ1 VSS

Comparators 18-29 Analog ICs; Jieh-Tsorng Wu Oﬀset Canceled Latches: MOST Implementation

• M7 and M8 are active loads, which both decrease the voltage drops across M5 and

M6, increase available gain, increase Vo output swing, and enhance speed.

• d An equalizing switch driven by φ1 can be placed between node C and D to eliminate the switching error mismatch between MS7 and MS8.

• d An equalizing switch driven by φ2 can be placed between node E and F to eliminate the mismatch between MS5 and MS6. In this case, MS9 and MS10 are driven by dd φ2 and the charge absorption mismatch between MS9 and MS10 becomes the only signiﬁcant contribution to the oﬀset, which is

g + g = ∆Q · m3 m7 VOS(in) C gm1

• Reference: B. Razavi, JSSC, 12/92, pp. 1916Ð1926.

Comparators 18-30 Analog ICs; Jieh-Tsorng Wu BJT Latched Comparator

VCC

R1 R2 Q7

Q1 Q2 Q3 Q4 V V i o

Q5 Q6 φ

I1 I2 I3

VEE

Comparators 18-31 Analog ICs; Jieh-Tsorng Wu BJT Latched Comparator

• = During the track mode (φ 1), the variation of input capacitance with Vi causes input-dependent delay and hence harmonic distortion.

• Speed may be limited by overdrive recovery.

• During latch-to-track transition, Q1 and Q2 are initially oﬀ, the I1 current then ﬂows through Q5 and the emitter junctions of Q1 and Q2 to the input, creating kickback noise.

• Usually preceded by a buﬀer.

Comparators 18-32 Analog ICs; Jieh-Tsorng Wu BJT Comparator with High-Level Latch

VCC

R1 R2

• During the latch mode (φ = 0), the variation V o in Vi will not disturb the latched state.

Q3 Q4 • Q1 and Q2 are never turned oﬀ, thus reducing kickback noise. Q5 φ Q6 Q7 φ Q8 • The kickback noise results only from the B A transients at nodes A and B. Adding a resistor between A and B decreases these Q1 Q2 transient and improves the recovery at these V i node.

VEE

Comparators 18-33 Analog ICs; Jieh-Tsorng Wu A Sampled-Data Ampliﬁer with Internal Oﬀset Cancellation

= φ1 1 C 3 C C 1 5 V V 1 i1 o1 C a1 a2 3 2 V V 1 i2 o2 C C C C 6 1 1 5 2 V V C i1 o1 4 1 2 a1 a2 1 = 1 φ2 1 V V o2 i2 C C C 1 3 2 6 C C 1 5 V C 2 o1 4 1 a1 a2

V o2 C C 2 6 C 4

Comparators 18-34 Analog ICs; Jieh-Tsorng Wu A Sampled-Data Ampliﬁer with Internal Oﬀset Cancellation

• During reset mode, OOS is applied to a1 and IOS is applied to a2. a1 is low gain and a2 is high gain.

• The OOS and IOS perform correlated double sampling (CDS) so that the eﬀect of 1/f noise is also reduced.

• Additional capacitors in the signal path (i.e., C5 and C6) can degrade the closed-loop settling behavior.

• Reference: Yen, JSSC, 12/82, pp. 1008Ð1013.

Comparators 18-35 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁer with Oﬀset Compensation

S3 S1 1

V 2 i V o S2 Gm1 R S4 1S5

Gm2 S6 C1 C2

• The Gm2 compensation circuit is not in the signal path. The original frequency/speed performance can be maintained.

Comparators 18-36 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁer with Oﬀset Compensation

= During the reset mode (φ1 1)

= · + − · Vo VOS1 Gm1R (VOS2 Vo) Gm2R V · G R + V · G R G ⇒ V = OS1 m1 OS2 m2 ⇒ V ≈ V · m1 + V If G R 1 o + o OS1 OS2 m2 1 Gm2R Gm2 • ﬀ VOS1 and VOS2 are the input-referred o set of the Gm1-R and Gm2-R pairs.

= During the amplification mode (φ2 1) G V V G = · + m1 + + · = + OS1 + OS2 + m2 Vo Vi Gm1R VOS1 VOS2 ∆V Gm2R Gm1R Vi ∆V Gm2 Gm2R Gm1R Gm1 V V G ff = = OS1 + OS2 + · m2 Input-Referred O set VOS,in ∆V Gm2R Gm1R Gm1 • ff ∆V is due to the mismatch between the switching errors of S5 and S6. Its e ect on Vo can be reduced by making Gm2/Gm1 small.

Comparators 18-37 Analog ICs; Jieh-Tsorng Wu Operational Ampliﬁer with Oﬀset Compensation

VDD

M9 M10 VBP1

M3 M4 VBP2

S3 Vo1 1 2 Vi1 M1 M2 Vo2 S1 1 M11 1 2 M6 VBN2 M12 Vi2 M5 S5 S6 S2 C C S4 1 2 1 IV1 M8 BN1 I2 M7

VSS

Comparators 18-38 Analog ICs; Jieh-Tsorng Wu The Chopper Stabilization Technique 1 f c 1

Vi A Vo 1 LPF VOS f

f f f f f 0 0 0 0 0 fc fc

• The bandwidth of the ampliﬁer A must be wider than fc.

• The ampliﬁer A should employ design of minimizing thermal noise.

Comparators 18-39 Analog ICs; Jieh-Tsorng Wu A Chopper Operational Ampliﬁer

VDD

φ I I I R1 R2 3 4 5 M5 M6 C1

M3 M4 1 V φ C2 o

RL Vi M1 M2

Vi M7 M8 M9 I1 I2

VSS φ a

b φa b φb a

Comparators 18-40 Analog ICs; Jieh-Tsorng Wu A Chopper Operational Ampliﬁer

• The M1ÐM2 is a low-gain low-noise stage.

• The M3ÐM4 is a high-gain stage with low Gm. A common-mode feedback circuit is required to stabilize the drain voltages of M3 and M4.

• The M5ÐM8 is a high-gain Miller stage for frequency compensation and low-pass ﬁlter.

• The M9 is a low-gain buﬀer stage.

• The chopper can introduce additional kT/C noise.

• Reference: A. Bakker, et al., “A CMOS Nested-Chopper Instrumentation Ampliﬁer with 100-nV Oﬀset,” JSSC 12/2000, pp. 1877Ð1883.

Comparators 18-41 Analog ICs; Jieh-Tsorng Wu Residual Oﬀset of Chopper Ampliﬁer

1 f c 1

Vi A Vo 1 LPF VOS f

t Modulation Signal

t Spikes at Input

t Demodulation Signal

Residual Offset t Demodulated Spikes

Comparators 18-42 Analog ICs; Jieh-Tsorng Wu Chopper Modulation with Guard Time

1 f c 1

Vi A Vo 1 LPF VOS f

t Modulation Signal

t Spikes at Input

t Demodulation Signal

Residual Offset t Demodulated Spikes

Comparators 18-43 Analog ICs; Jieh-Tsorng Wu Chopper Modulation with Guard Time

• The spikes at the input is due to the switching error mismatch of the chopper.

• The residual offset is linear dependent on chopper frequency. √ • Reference: Q. Huang and C. Menolfi, “A 200nV Offset 6.5nV/ Hz Noise PSD 5.6kHz Chopper Instrumentation Amplifier,”, ISSCC 2002.

Comparators 18-44 Analog ICs; Jieh-Tsorng Wu Oscillators

Jieh-Tsorng Wu

October 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering The Barkhausen Criteria

S e S i a S o

S fb f

= · = · = − So a Se Sfb f So Se Si Sfb S a a Closed-Loop Gain = A ≡ o = = Loop Gain = T ≡ a × f Si 1 + af 1 + T

The feedback system oscillates at ωo,if

| | ≥ ∠ = ◦ T (jωo) 1 T (jωo) 180

OSCs 19-2 Analog ICs; Jieh-Tsorng Wu Three-Stage Ring Oscillator

VDD VDD VDD V1

R R R V1 V2 V3

V2 C C C

3 3 gmR A0 1 −T (s) = − = − A = g Rω= 1 + sRC 3 0 m p RC 1 + s ωp

OSCs 19-3 Analog ICs; Jieh-Tsorng Wu Three-Stage Ring Oscillator

From the Barkhausen criteria, ω −1 o = ◦ ⇒ = tan 60 ωo 3ωp ωp A3 0 = 1 ⇒ A = g R = 2 3 0 m 2 1 + ωo ωp

◦ ◦ ◦ • The phase diﬀerence between the neighboring nodes is 180 + 60 = 240 .

• ﬀ If A0 > 2, the oscillation amplitude increase exponentially until nonlinear e ect limits the growth. A − 2 A V (t) ∝ exp 0 ω t cos 0ω t 2 p 2 o

OSCs 19-4 Analog ICs; Jieh-Tsorng Wu Three-Stage CMOS Inverter Ring Oscillator

VDD

VDD V1 V2 V3

GND

= 1 = 1 + = 1 + fo tp tpHL tpLH 0.69ReqnC 0.69ReqpC 6tp 2 2 −1 VDD/2 V 3 V 7 R = dV ≈ DD 1 − λV eq I (1 + λV ) 4I 9 DD VDD/2 VDD DSAT DSAT

• The oscillation frequency fo can be varied by changing VDD.

OSCs 19-5 Analog ICs; Jieh-Tsorng Wu Four-Stage Diﬀerential Ring Oscillator

VDD

R RC CR R Va Vmax V1a V2a V1b V2b Vb Vmin M1 M2 V2c Vc

M5 t VB IS IS

OSCs 19-6 Analog ICs; Jieh-Tsorng Wu Four-Stage Diﬀerential Ring Oscillator

From the Barkhausen criteria, ω −1 o = ◦ = ⇒ = tan 45 ωp RC ωo ωp ωp A4 0 = 1 ⇒ A = g R = 2 4 0 m 2 1 + ωo ωp

The delay stage is usually designed to experience complete switching, i.e.,

= = − = − = Vmax VDD Vmin VDD ISR∆VVmax Vmin ISR

OSCs 19-7 Analog ICs; Jieh-Tsorng Wu Diﬀerential Delay Stage

Let 2(I /2) ====== S ∆V ISRVt Vt1 Vt2 Vov Vov1 Vov2 µCox(W/L)1,2

• To maintain M1 and M2 in the forward-active region, ISR 2Vov Vov <∆V/ 2. √ √ • = · ⇒ For enough loop gain, want gmR [(IS/2)/(Vov /2)] R> 2 Vov <∆V/ 2.

• The minimum VDD can be approximated by

∆V V ≈ V + V + V + DD,min ov5 t ov 2

OSCs 19-8 Analog ICs; Jieh-Tsorng Wu Delay Variation Using Variable Resistors

VDD MB1=M3=M4 and MB2=M5,

MB1 ∆V = V − V ≈ I R Vcb M3 DD R S on V R M4 1 I ω = ≈ S p · Vb Va RonC ∆V C A = g R M1 M2 0 m1,2 on = ∆V W MB2 2µnCox IS IS L 1,2 Vct M5 IS ∆V W = 2µ C n ox L IS 1,2

• MB1, M3, and M4 are biased in the triode region.

• A0 decreases at higher oscillation frequencies.

OSCs 19-9 Analog ICs; Jieh-Tsorng Wu Delay Variation Using Positive Feedback

VDD

IT R1 R2

Va Vb Vct1 Vct2

M1 M2 M3 M4

M5 M6 VB1 VB2 VB1 VB2 IS1 IS2

C gm1,2 I = I + I ∆V = I R ω =≈ A ≈ T S1 S2 T 1,2 p G − g 0 G − g 1,2 m3,4 1,2 m3,4 = = gm1,2 2µnCox(W/L)1,2IS1 gm3,4 2µnCox(W/L)3,4IS2

OSCs 19-10 Analog ICs; Jieh-Tsorng Wu Delay Variation Using Interpolation

VDD

R1 R2

Va Vb VDD M1 M2

R3 R4

IS1 M3 M4

Vin1 M5 M6

IS2 Vin2

+ = IS1 IS2 Constant

OSCs 19-11 Analog ICs; Jieh-Tsorng Wu LC-Tuned Delay Stage

|H| VDD gm R

LCR ω = 1 Vo ωr √ (−H) LC V i o R 90 Q = ω RC = r ω L ω r o 90 ωr 1 s V (s) g Q ω = o = m = · r H(s) gmR V (s) (sL)−1 + sC + 1/R 2 i s + 1 s + 1 ωr Q ωr

OSCs 19-12 Analog ICs; Jieh-Tsorng Wu LC-Tuned Delay Stage

In the frequency domain

= · 1 = · H(jω) gmR gmR A(jω) 1 + jQ ω − ωr ωr ω

• − A(jω) is a band-pass function with 3 dB frequencies at ω1 and ω2, and bandwidth = − B ω2 ω1. ω R ω · ω = ω2 B = r = ω2RC = 1 2 r Q r L • = − If ∆ω ω ωr ωr,wehave

1 A(jω) ≈ 1 + j2Q · ∆ω ωr

OSCs 19-13 Analog ICs; Jieh-Tsorng Wu LC-Tuned Ring Oscillators

VDD VDD VDD

LCR LCRRLC LCR

V1 V2 V1 V2 M1 M2 M1 M2

√ • = = Oscillation frequency is ωo ωr 1/ LC.

• ◦ V1 and V2 are 180 out of phase.

• Need gmR>1 to start oscillation.

• Varactors, such as pn junctions with reverse bias or MOSTs in the accumulation

mode, are used for ωo variation.

OSCs 19-14 Analog ICs; Jieh-Tsorng Wu Colpitts Oscillator

VDD Vo

LCR C1 LCR Vo V1 V B C1 C2 gm sC2mg V C2 o

C1 LCR 1 : N

C1 C2 C2 N C1

OSCs 19-15 Analog ICs; Jieh-Tsorng Wu Colpitts Oscillator

• The oscillation frequency is 1 C C ω ≈ ω = C = C + (C C ) = C + 1 2 o r p 1 2 + LCp C1 C2

• The loop gain at ωr is

g g | | = m · 1 = m T (jωr) G + gm N G · N + gm N2 N

Want g R |T (jω )| > 1 ⇒ g R>N+ m r m N • ∼ If C1 C2, i.e., N 1, oscillation cannot occur.

OSCs 19-16 Analog ICs; Jieh-Tsorng Wu One-Port Oscillators

I I

0 LCG V f(V) V 0

1 dV dV 2 d Vdt+ C + G · V + f (V ) = 0 ⇒ LC + L [G · V + f (V )] + V = 0 L dt dt dt • For small-signal analysis, let ( ) = − · with = − ( ) . Then, we have f V a V a df V /dV V =0

LCs2 + L(G − a)s + 1 = 0 G − a 1 G − a 2 s ,s = − ± j − = α ± jβ ⇒ V (t) ≈ Aeα cos βt 1 2 2C LC 2C

Need a>Gto start oscillation.

OSCs 19-17 Analog ICs; Jieh-Tsorng Wu The van der Pol Approximation √ Let T = t/ LC,wehave

d 2V L d + · [F (V )] + V = 0 F (V ) = G · V + f (V ) dT2 C dT

The van der Pol approximation for F (V )is

= − · + · 3 = − Fv (V ) a1 V b1 V a1 a G

F v (V) V x a ± = ± 1 Vx V b1 V 1 a V − = · 1 V max 3 b1

V L L x = · a = · (a − G) C 1 C

OSCs 19-18 Analog ICs; Jieh-Tsorng Wu The van der Pol Approximation

For near-sinusoidal oscillations, >0 and → 0. a = 4 1 · 1 t v(t) √ cos √ 3b − − 1 1 + e (t t0)/ LC LC √ − − • At the start of oscillation, e (t t0)/ LC 1, we have √ √ t 4 a1 − V (t) = Aet/(2 LC) cos √ = AeT/2 cos TA= · e t0/(2 LC) LC 3b1

• In steady state, t →∞, a = 4 1 t = V (t) cos √ Vmax cos T 3b1 LC a = 4 1 = 4 · = = − Vmax Vx 1.15Vx 2V 3b1 3

OSCs 19-19 Analog ICs; Jieh-Tsorng Wu A CMOS SONY Oscillator

VDD

I LCG IS 2 Vo Io = − VDD 0 V Vo VB f(V) I V I = I − S M1B M2 o 2 V VIM VIM IS

k 4I 2I W = = S − 2 = S = I f (V ) V V VIM k µCox 4 k k L 1,2

OSCs 19-20 Analog ICs; Jieh-Tsorng Wu Diﬀerential CMOS SONY Oscillators

VDD VDD 2L LCGGL C C/2 G/2 I Vo I o o Vo

M1 M2 M1 M2

IS IS

k 4I W = = = = S − 2 = V Vo I Io I f (V ) V V k µCox 4 k L 1,2

OSCs 19-21 Analog ICs; Jieh-Tsorng Wu Single-Transistor Negative Resistance Generator

Ix Ix

V x Rx V C1 x

C2 Cx

Ix −I 1 I V g 1 1 V = I − x · g + x ⇒ x = m + + x x m 2 sC2 sC1 sC2 Ix s C1C2 sC1 sC2 g C C R = − m C = C C = 1 2 x 2 x 1 2 + ω C1C2 C1 C2

OSCs 19-22 Analog ICs; Jieh-Tsorng Wu Single-Transistor Negative-Resistance Oscillators

L L L L C1 C1 C1 C2 C2 C2 C2

C1 VDD VDD

VDD L L L VB V C2 B C1 C1

C1 C2

OSCs 19-23 Analog ICs; Jieh-Tsorng Wu Piezoelectric Crystals

+jX

Circuit Model ωa 0 ω RCL ωs

Co −jX

− − [R + (jωC) 1 + jωL](jωC ) 1 Z(jω) = o R + (jωC)−1 + jωL+ (jωC )−1 o ω ω L = 1 = 1 a = + C = 1 = s ωs √ ωa 1 Q LC ωs Co ωsRC R L(C Co)

OSCs 19-24 Analog ICs; Jieh-Tsorng Wu Piezoelectric Crystals

• = Ω = = = = Example: R 16.3 , C 0.009 pF, L 7.036 nH, Co 2.3 pF; thus fo 20 MHz, Q = 54245.

• The serial RLC can be transformed into a parallel circuit 1 1 X R = R 1 + Q2 X = X 1 + where X = ωL − Q = s p s p s 2 s ωC s R Qs

= At ω ωa, with Qs 1, we have

2 2 1 X Xp 1 X = R ≈ s ≈ = p p 2 ωaCo R R R(ωaCo)

• Circuits containing crystals are designed so that the frequency range of interest is

between ωs and ωa.

OSCs 19-25 Analog ICs; Jieh-Tsorng Wu Crystal Oscillators

Colpitts Oscillator Pierce Oscillator VDD L L VB

C2 C1

C2 C1 VDD

VDD

C1 C2 C1

OSCs 19-26 Analog ICs; Jieh-Tsorng Wu Relaxation Oscillators (Multivibrators)

Tab

1 f = State A State B o + + + Ta Tb Tab Tba T T 1 a b f ≈ o,max + Tab Tba Tba

• The two states are created by positive feedback.

• Ta and Tb are usually determined by the charging and discharging of timing capacitors, while Tab and Tba are the transient response of the circuit.

• Comparing with the frequency-tuned oscillators, the relaxation oscillators have wider tuning range, predictable waveforms, but poorer spectral purity.

OSCs 19-27 Analog ICs; Jieh-Tsorng Wu Constant-Current Charge/Discharge Oscillators

Schmitt Trigger VA VDD VA Vo I1 V Vo S D B Q R C D

VB T T D x I2 1 2

C · (V − V ) C · (V − V ) T = A B T = A B 1 I 2 I − I 1 2 1 1 I I f = = 1 1 − 1 o + · − T1 T2 C (VA VB) I2

OSCs 19-28 Analog ICs; Jieh-Tsorng Wu The Banu Oscillator VDD

Vx VDD C C Vy Vx Vy Vth Va Va IB Vb Vb

• = = · − Oscillation frequency is fo 1/(2T ) where T C (VDD Vth)/IB.

• Reference: Banu, M., “MOS Oscillators with Multi-Decade Tuning Range and GHz Maximum Speed,” JSSC, 12/1998, pp. 1386–1393.

OSCs 19-29 Analog ICs; Jieh-Tsorng Wu A CMOS Relaxation Oscillator

VDD VDD V 1 V 1 V 2 V 3 V DD

V x RC V DD 0 t

V o V DD T V 2 1

V i V 3 T 2 V x V DD

V + V = + + − −t/(RC) ⇒ = x DD V1(t) 0 (Vx VDD 0)e T1 RC ln Vx 2V − V V (t) = V + (V − V − V )e−t/(RC) ⇒ T = RC ln DD x 1 DD x DD DD 2 − VDD Vx

OSCs 19-30 Analog ICs; Jieh-Tsorng Wu A Emitter-Coupled Multivibrator

Q1 Off Q1 On VCC Q2 On Q2 Off V CC Vc1 D1 D2 T 1 V CC V BE(on) R1 R2 V CC Vc1 Q3 Q4 Vc2 Vc2 T 2 V CC V BE(on)

Q1 Q2 Ve1 V CC 2V BE(on)

Ve1 C Ve2

V Ve2 V CC 2V BE(on) I 1 x I 2 V i V BE(on)

Vx 0

V BE(on)

OSCs 19-31 Analog ICs; Jieh-Tsorng Wu A Emitter-Coupled Multivibrator

• Q1, Q2, Q3, and Q4 are never saturated.

• D1 and D2 act as voltage clamps. Thus the maximum voltage across R1 and R2 are

VBE(on).

• The relaxation times are

C · 2V C · 2V = BE(on) = BE(on) T1 T2 I1 I2

• = = If I1 I2 I, the frequency of oscillation is

1 1 I f = = · o + · T1 T2 4 C VBE(on)

OSCs 19-32 Analog ICs; Jieh-Tsorng Wu Fundamentals of Analog Filters

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Filters

Continuous Analog Filter Xi (t) Xo (t) H(s)

Sampled Data Filter Xi (t) Xo (t) H(z)

Digital Filter Xi (t) A/D D/A Xo (t) H(z)

Anti−Aliasing Reconstruction Filter Filter

Filters 20-2 Analog ICs; Jieh-Tsorng Wu Filters

Continuous-Time Analog Filters

• Diﬀerential equations.

• Laplace transforms. s = jω

Discrete-Time (Sampled-Data) Analog Filters

• Diﬀerence equations.

− • 1 = jωTs Z-transform; z is unit delay operator. z e ; Ts is sampling period.

Discrete-Time (Sampled-Data) Digital Filters

• Discrete-time systems.

• A/D introduces quantization noise.

Filters 20-3 Analog ICs; Jieh-Tsorng Wu Low-Pass Filter Speciﬁcations

|H(jω)| (dB) PB Ripple

SB Attenuation SB PB TB ω ωc ωs

Filters 20-4 Analog ICs; Jieh-Tsorng Wu High-Pass Filter Speciﬁcations

|H(jω)| (dB) PB Ripple

SB Attenuation SB PB

TB ω ωs ωc

Filters 20-5 Analog ICs; Jieh-Tsorng Wu Band-Pass Filter Speciﬁcations

|H(jω)| (dB)

SB L SB H

ω ωcL ωcH ωsL ωsH

Filters 20-6 Analog ICs; Jieh-Tsorng Wu Band-Reject Filter Speciﬁcations

|H(jω)| (dB)

PB L PB H

ω ωcL ωcH ωsL ωsH

Filters 20-7 Analog ICs; Jieh-Tsorng Wu Second-Order Filter (Biquadratic Function)

jω

a s2 + a s + a H(s) = 2 1 0 2 + + s b1s b0 a (s − z )(s − z ) = 2 1 2 σ − − (s p1)(s p2) s2 + (ω /Q )s + ω2 = K · z z z 2 + + 2 s (ωp/Qp)s ωp

= = | | = | | = = | | = | | ωp Pole Frequency p1 p2 ωz Zero Frequency z1 z2 ω ω = = p = = z Qp Pole Quality Factor Qz Zero Quality Factor 2Re(p1) 2Re(z1)

Filters 20-8 Analog ICs; Jieh-Tsorng Wu Second-Order Filter (Biquadratic Function)

• = ∗ = ∗ For complex poles and zeros, z2 z1 and p2 p1.

• = 2 2 ∞ = H(0) Kωz/ωp and H( ) K .

•| | ≈ H(jω) is maximum, at ω ωp.

• The sharpness of the maximum is determined by Qp.

•| | ≈ H(jω) is minimum, at ω ωz.

• The depth of the minimum is determined by Qz.

Filters 20-9 Analog ICs; Jieh-Tsorng Wu Second-Order Low-Pass (LP) Filter

jω |H(jω)|

K σ

ω ωM

2 Kωp H(s) = 2 + + 2 s (ωp/Qp)s ωp KQ = · − 2 = ωM ωp 1 1/(2Q ) M 1 − 1/(4Q2)

Filters 20-10 Analog ICs; Jieh-Tsorng Wu Second-Order High-Pass (HP) Filter

jω |H(jω)|

K σ

ω ωM

Ks2 H(s) = 2 + + 2 s (ωp/Qp)s ωp ω = p = KQ ωM M 1 − 1/(2Q2) 1 − 1/(4Q2)

Filters 20-11 Analog ICs; Jieh-Tsorng Wu Second-Order Band-Pass (BP) Filter

jω |H(jω)|

K σ √ K/ 2

ω ωp

K (ωp/Qp)s H(s) = 2 + + 2 s (ωp/Qp)s ωp

ωp 3 dB Bandwidth = Qp

Filters 20-12 Analog ICs; Jieh-Tsorng Wu Second-Order Band-Reject (BR) Filter — Low-Pass Notch (LPN)

jω |H(jω)|

σ K

ω ωM ωz

K (s2 + ω2) = z H(s) ωz >ωp 2 + + 2 s (ωp/Qp)s ωp

Filters 20-13 Analog ICs; Jieh-Tsorng Wu Second-Order Band-Reject (BR) Filter — High-Pass Notch (HPN)

jω |H(jω)|

M K σ

ω ωz ωM

K (s2 + ω2) = z H(s) ωz <ωp 2 + + 2 s (ωp/Qp)s ωp

Filters 20-14 Analog ICs; Jieh-Tsorng Wu Second-Order Band-Reject (BR) Filter — Symmetrical Notch

jω |H(jω)|

K σ √ K/ 2

= ω ωz ωp

K (s2 + ω2) = z = H(s) ωz ωp 2 + + 2 s (ωp/Qp)s ωp

ωp 3 dB Notch Width = Qp

Filters 20-15 Analog ICs; Jieh-Tsorng Wu Second-Order All-Pass (AP) Filter

jω

|H(jω)| ∠H(jω) 0

180

ω 360 ωp

Filters 20-16 Analog ICs; Jieh-Tsorng Wu Second-Order All-Pass (AP) Filter

2 − + 2 s (ωp/Qp)s ωp H(s) = K · |H(jω)| = K 2 + + 2 s (ωp/Qp)s ωp

ωn/Qp ω φ(ω ) = −2 tan−1 ω = n − 2 n ω 1 ωn p dφ(ω) 1 + ω2 = = − = = 2 · n Group Delay τ τn(ωn) ωpτ(ωn) dω Q − 2 2 + 2 p (1 ωn) (ωn/Qp) √ • = For Qp 1/ 3, the delay curve is maximally ﬂat. √ • ≈ ≈ − 2 For Qp > 1/ 3, τ has a peaking, τn,max 4Qp/ωp at ωn 1 1/(4Qp).

• For 2nd-order ﬁlters, 1 τ (ω ) = τ (ω ) n,(LP,HP,BP,BR) n 2 n,AP n

Filters 20-17 Analog ICs; Jieh-Tsorng Wu Maximally Flat (Butterworth) Filters

|H(jω)|2 jω

1/(1 + 2) σ 1 1

1/(1 + δ2) ω 1 ωs

1 |H(jω)|2 = + 2 2N 1 ω 2k + N − 1 Poles = s = −1/N · exp j π k = 1, 2, ··· ,N k 2N

Filters 20-18 Analog ICs; Jieh-Tsorng Wu Maximally Flat (Butterworth) Filters

The relationship between the ﬁlter order, N, and the steepness of the magnitude response is log δ − log N ≥ log ωs

• Good ﬂatness in passband.

• Poor phase linearity.

• Moderate attenuation slope steepness.

Filters 20-19 Analog ICs; Jieh-Tsorng Wu Equi-Ripple (Chebyshev) Filters

| |2 Chebyshev| |2 Inverse Chebyshev H1(jω) H2(jω)

1 1

1/(1 + 2) N=3

N=4

1/(1 + δ2) ω ω 1 ωs 1 ωs

= | |2 = 1 Chebyshev H1(jω) + 2 2 1 CN(ω) 2C2 (1/ω) = | |2 = N Inverse Chebyshev H2(jω) + 2 2 1 CN(1/ω)

Filters 20-20 Analog ICs; Jieh-Tsorng Wu Equi-Ripple (Chebyshev) Filters

The function CN is

= −1 ≤ CN(ω) cos[N cos (ω)] for ω 1 − = cosh[N cosh 1(ω)] for ω>1 = − 2ωCN−1(ω) CN−2(ω)

The relationship between the ﬁlter order, N, and the steepness of the magnitude response is − cosh 1(δ/) ln(2δ/) N ≥ ≈ −1 cosh ωs + 2 − ln ωs ωs 1

• Good steepness of the attenuation slope.

• Poorer phase linearity and passband ﬂatness than the Butterworth ﬁlters.

• Inverse Chebyshev ﬁlters have better phase and delay performance.

Filters 20-21 Analog ICs; Jieh-Tsorng Wu Elliptic (Cauer) Filters

|H(jω)|2

1 1/(1 + 2)

1/(1 + δ2) ω 1 ωs

1 |H(jω)|2 = + 2 2 1 RN(ω)

Filters 20-22 Analog ICs; Jieh-Tsorng Wu Elliptic (Cauer) Filters

The function RN is

N/2 ω2 − (ω /ω )2 = s zi RN(ω) k for N even 2 − 2 i=1 ω ωzi − (N1)/2 ω2 − (ω /ω )2 = kω s zi for N odd 2 − 2 i=1 ω ωzi

2 2 In the stopband, if RN(ω) 1,

δ 20 log ≈ 20 log |R (ω )| N s

• Best steepness of the attenuation slope.

• Poor phase linearity.

Filters 20-23 Analog ICs; Jieh-Tsorng Wu Comparison of the Classical Filter Responses

Comparing ﬁlters that satisfy the same δ and requirements:

• The Cauer ﬁlter has the lowest order, while the Butterworth ﬁlter has the highest order.

• The Butterworth ﬁlter has the best passband performance, and the inverse Chebyshev ﬁlter is a close second.

• The Cauer filter has the largest pole quality factor; next is the Chebyshev filter, followed by the inverse Chebyshev and the Butterworth filters.

• The Chebyshev filter has the worst group delay variation; next is the inverse Chebyshev filter, followed by the Butterworth and the Cauer filters.

• The Butterworth and the Chebyshev are all-pole filter, while the inverse Chebyshev and Cauer filters have finite transmission zeros.

• The inverse Chebyshev ﬁlters have low order, modest Q values, good delay performance, and minimal passband attenuation, making them most attractive.

Filters 20-24 Analog ICs; Jieh-Tsorng Wu Linear-Phase (Bessel-Thomson) Filters

|H(jω)|2

1 1/(1 + 2)

1/(1 + δ2) ω 1 ωs

b N (2N − i)! H(s) = o D(s) = b si b = i = 0, 1, ··· ,N− 1 D(s) i i 2N−ii!(N − i)! i=0

D(s) is related to Bessel polynomials.

= − + 2 D(s) (2N 1)DN−1 s DN−2

Filters 20-25 Analog ICs; Jieh-Tsorng Wu Linear-Phase (Bessel or Thomson) Filters

• Approximate the linear-phase response.

• Poor steepness of the attenuation slope.

• It is usually more efficient to use a Butterworth, Chebyshev or a Cauer filter cascaded with an all-pass filter to achieve required gain and linear-phase response.

Filters 20-26 Analog ICs; Jieh-Tsorng Wu All-Pass Filter (Delay Equalizer) Speciﬁcations

|H(jω)| (dB) jω PB

ω ωcL ωcH

H(jω) = |H(jω)|ejφ(ω) dφ(ω) Group Delay = τ(ω) = − dω

Filters 20-27 Analog ICs; Jieh-Tsorng Wu Frequency Transformations

Low-Pass to High-Pass Transformation 1 H (s) = H HP LP s

• For RC active ﬁlters, it is an RC-CR transformation.

Low-Pass to Band-Pass Transformation s2 + 1 H (s) = H Q · BP LP s

• = = − Q ωo/B is the quality factor, where ωo is the center frequency, B ωcH ωcL is the passband bandwidth.

• Transformation always results in symmetrical band-pass ﬁlters.

Filters 20-28 Analog ICs; Jieh-Tsorng Wu Frequency Transformations

Low-Pass to Band-Reject Transformation 1 s H (s) = H · BR LP Q s2 + 1

• = = − Q ωo/B is the quality factor, where ωo is the center frequency, B ωsH ωsL is the passband bandwidth.

• Transformation always results in symmetrical band-reject ﬁlters.

Frequency Scaling s H(s) = H( ) a

• = · = · = · So that ωc a ωc, ωs a ωs, ωo a ωo

Filters 20-29 Analog ICs; Jieh-Tsorng Wu High-Order Filters

Cascade Topology

In H1 H2 H3 H4 Out

Follow-the-Leader Feedback (FLF) Topology

F1 F2 F3 F4

In H1 H2 H3 H4 Out

Leapfrog (LF) Topology F2 F4

In H1 H2 H3 H4 H5 Out

F3 F5

Filters 20-30 Analog ICs; Jieh-Tsorng Wu High-Order Filters

Cascade Topology: = · · · H(s) H1 H2 H3 H4

Follow-the-Leader Feedback (FLF) Topology:

H H H H H(s) = 1 2 3 4 + + + + 1 F1H1 F2H1H2 F3H1H2H3 F4H1H2H3H4

Leapfrog Topology: H H H H H H(s) = 1 2 3 4 5 D(s)

= + + + + D(s) 1 F2H1H2 F3H2H3 F4H4H4 F5H4H5 + + + F2F4H1H2H3H4 F2F5H1H2H4H5 F3F5H2H3H4H5

Filters 20-31 Analog ICs; Jieh-Tsorng Wu LC Ladder Filters

R V Y2 Y4 Y(n-1) V S 1 2

I V 1 Z1 Z3 Z(n-2) Z(n) R S L

Lossless LC Network

A Fifth-Order Elliptic Low-Pass Filter R V V S 1 2

V R S L

Filters 20-32 Analog ICs; Jieh-Tsorng Wu LC Ladder Filters

When designed for maximum power transfer, the LC ladder ﬁlters are inherently insensitive to component variations, particularly in their passband.

|V |2 Input Power = P = |I (jω)|2Re{Z (jω)} = S Re{Z (jω)} 1 1 in | + |2 in RS Zin(jω) |V |2 |V |2 = = 1 S = = 2 Maximum Input Power P1,max Output Power P2 4 RS RL 2 4RS V2 N(s) 2 4RS V2 H(s) = · = |H(jω)| = · ≤ 1 RL VS D(s) RL VS R − Z (jω)2 R − Z (s) |H(jω)|2 = 1 − S in = 1 −|ρ(jω)|2 ρ(s) = ± S in + + RS Zin(jω) (RS Zin(s))

• ρ(s) is the reﬂection coeﬃcient.

Filters 20-33 Analog ICs; Jieh-Tsorng Wu Sensitivity

Let P is a function of x. The sensitivity of P with respect to x is deﬁned as:

∂P/P ∂(ln P ) P = = x · ∂P = Sx dx/x P ∂x ∂(ln x)

The semirelative sensitivity is deﬁned as

P = ∂P = · ∂P Qx x ∂x/x ∂x

• Some useful relationships:

P1P2 = P1 + P2 P1/P2 = P1 − P2 P = P · y Sx Sx Sx Sx Sx Sx Sx Sy Sx

Filters 20-34 Analog ICs; Jieh-Tsorng Wu Sensitivity

• ··· Let Y is a function of x1,x2, ,xn.

= ∂Y · + ∂Y · + ···+ ∂Y · dY dx1 dx2 dxn ∂x1 ∂x2 ∂xn dY dx dx dx = SY · 1 + SY · 2 + ···+ SY · n x1 x2 xn Y x1 x2 xn

• = · Let the forward gain T T1 T2,wehave

T ∂T ST = 2 · = 1 T2 T ∂T2 With negative feedback factor H,wehave

T T T ∂T 1 T = 1 2 ⇒ ST = 2 · = + T2 + 1 HT1T2 T ∂T2 1 HT1T2

The T sensitivity is reduced by the loop gain HT1T2

Filters 20-35 Analog ICs; Jieh-Tsorng Wu Transfer Function Sensitivity

Let the transfer function be

N(s) a sm + ···+ a s + a (s − z )(s − z ) ···(s − z ) H(s) = = m 1 0 = K · 1 i m n + ···+ + − − ··· − D(s) bns b1s b0 (s p1)(s p2) (s zn)

The sensitivity is

∂ ln N ∂ ln D SH = SN − SD = − x x x ∂ ln x ∂ ln x = K + ∂ { − + ···+ − − − + ···+ − } Sx x [ln(s z1) ln(s zm)] [ln(s p1) ln(s pn)] ∂x    x ∂z1 x ∂zm x ∂p1 x ∂pn = K −  ∂x + ···+ ∂x  +  ∂x + ···+ ∂x  Sx − − − − s z1 s zm s p1 s pn z z p p z S 1 z S m p S 1 p S n = K − 1 x + ···+ m x + 1 x + ···+ n x Sx − − − − s z1 s zm s p1 s pn

Filters 20-36 Analog ICs; Jieh-Tsorng Wu Transfer Function Sensitivity

• Any pole or zero shift inﬂuences H(s) most strongly in the neighborhood of that pole or zero.

• SH →∞at a jω-axis transmission zero z = jω . x i zi

• For frequencies s = jω in the neighborhood of pole with large quality factor, high sensitivities are expected.

• Sensitivities are normally largest at the passband corner.

Filters 20-37 Analog ICs; Jieh-Tsorng Wu Second-Order Filter Sensitivity

The Biquadratic function is

N(s) a (s − z )(s − z ) a s2 + a s + a H(s) = = 2 1 2 = 2 1 0 D(s) (s − p )(s − p ) 2 + + 2 1 2 s (ωp/Qp)s ωp 1 1 1 1 p = −ω − j 1 − p = p∗ = −ω + j 1 − 1 p 2Q 2 2 1 p 2Q 2 p 4Qp p 4Qp

The sensitivity of the poles are

Q Q p ∗ p ω S ω S p1 = p − x p2 = p1 = p + x Sx Sx j Sx Sx Sx j 2 − 2 − 4Qp 1 4Qp 1 • 2 − ≈ The pole is 4Qp 1 2Qp times more sensitive to variations in ωp than to variations in Qp.

Filters 20-38 Analog ICs; Jieh-Tsorng Wu Second-Order Filter Sensitivity

The transfer function can be expressed as H(jω) = |H(jω)|ejθ(ω), then

∂ ln H(jω) ∂ ln |H(jω)| ∂θ(ω) |H(jω)| SH(jω) = = + jx = S + jθ(ω)Sθ(ω) x ∂ ln x ∂ ln x ∂x x x

Consider only the eﬀects of poles on the passband of H(s) sω ω sω Q ω Q p + 2 p − p p sn + p − sn p 2ωp S S 2 S S x ∂D(s) Qp x Qp x Qp x Qp x SH(s)x = − = − = − D(s) ∂x s2 + (ω /Q )s + ω2 s2 + s /Q + 1 p p p n n p 2 2 ω 2 ωp ω Qp n + − − n 2 ωp 2 Qp 2 1 ωn Sx Sx 1 + + 1 − Qp Qp ω ωn Sx ωn Sx SH(jω) = − + j n x 2 2 2 2 − 2 + Qp − 2 + 1 ωn ωn/Qp 1 ωn ωn/Qp = s = ω sn ωn ωp ωp

Filters 20-39 Analog ICs; Jieh-Tsorng Wu Second-Order Filter Sensitivity

We have 2 − 2 + 2 2 2 1 ωn ωn/Qp ω /Q |H(jω)| = − · ωp + n p · Qp Sx Sx Sx − 2 2 + 2 − 2 2 + 2 1 ωn ωn/Qp 1 ωn ωn/Qp 2 2 1 + ω2 ω /Q 1 − ω2 ω /Q ∂θ(ω) n n p ω n n p Q θ(ω) = = · p + · p θ(ω)Sx x Sx Sx ∂x − 2 2 + 2 − 2 2 + 2 1 ωn ωn/Qp 1 ωn ωn/Qp

And

|H(jω)| |H| ω |H| Q S = S · S p + S · S p x ωp x Qp x 2 − 2 + 2 2 2 1 ωn ωn/Qp ω /Q ⇒ |H| = − |H| = n p Sω S p − 2 2 + 2 Qp − 2 2 + 2 1 ωn ωn/Qp 1 ωn ωn/Qp

Filters 20-40 Analog ICs; Jieh-Tsorng Wu Second-Order Filter Sensitivity

|H| |H| S S ωp Qp

Q { |H|}≈ p ≈ + 1 { |H|} = = max Sω at ωn 1 max S 1atωn 1 p + 2 Qp 1 1/Qp Qp

|H| Qp 1 min{S }≈− at ω ≈ 1 − ωp − n 2 1 1/Qp Qp

Filters 20-41 Analog ICs; Jieh-Tsorng Wu Second-Order Filter Sensitivity

• Small variations of ωp are far more important than small change in Qp.

• Since the errors increase with Q, low-Q ﬁlters are easier to design with less accurate components than high-Q ﬁlters.

• Sensitivities are strong functions of frequency, and the passband edges are very critical.

Filters 20-42 Analog ICs; Jieh-Tsorng Wu High-Order Filter Sensitivity

A 6th-order Butterworth bandpass ﬁlter • For cascade design,

= ··· H(s) H1(s)H2(s) Hn(s) H(s) = H(s) = Hj (s) S 1 and Sx Sx Hj (s)

The sensitivity of H(s)tox is as large as

sensitivity of sub-block Hj (s)tox.

• Feedback paths around low-order sections in a multiple-feedback (MF) ﬁlter topology can reduce sensitivities in the passband. In the stopbands, where feedback paths lose their eﬀectiveness, MF and cascade sensitivities are approximately the same.

Filters 20-43 Analog ICs; Jieh-Tsorng Wu Active-RC Filters

Jieh-Tsorng Wu

October 17, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Capacitor Integrators

Vo V 1 1 1 o = = = I I jωC + G jωC 1 − j G 1 RC ωC jωC 1 − j QI (ω) ωC Q (ω) = I G

The transfer function of an integrator can be expressed as

1 1 1 1 H(jω) = = = = + + F (jω) jIm[F (jω)] Re[F (jω)] jωτ q jωτ 1 − j 1 QI (ω) Im[F (jω)] ωτ Q (ω) = = I Re[F (jω)] q

• QI is the quality factor of the integrator.

• →∞ → For an ideal integrator, QI and q 0.

Active-RC Filters 21-2 Analog ICs; Jieh-Tsorng Wu Active-RC Inverting Integrators

C R V V V 1 1 i o o(s) = − · A(s) V sRC + 1 + 1 i 1 A(s) 1 sRC

= Let A(s) ωu/s, then

V 1 1 1 1 1 o(s) = − · ≈− · if ω + + + u Vi sRC 1 s/ωu 1/(ωuRC) sRC 1 s/ωu RC V 1 1 o(jω) = − = − − 2 + Vi jωRC ω RC/ωu jωτ q 2 ω = = −ω RC = − ωRC = ωτ = − u = −| | τ RC q QI A(jω) ωu |A(jω)| q ω

Active-RC Filters 21-3 Analog ICs; Jieh-Tsorng Wu Actively Compensated Inverting Integrator

C Vo 1 A (s) = − 2 V sRC + 1+sRC i + R 1 1/A 2(s) A1(s) Vi Vo 1 A1 ≈− sRC 1 − 1 + 1 − 1 + ··· + 1+sRC A2(s) A2(s) A3(s) A1(s) 2 2 = = Let A1(s) ωu1/s, and A2(s) ωu2/s,

V 1 o(jω) ≈− V 3 2 − i jωRC 1 − jω − ω2 + jω + ··· − ω RC jω ωu2 ω2 ω3 ωu1 u2 u2 1 ≈− jωRC 1 + 1 − ω2 + ω2RC 1 − ω2 − ωu2 ωu1RC ω2 ωu2 ω2 ωu1 u2 u2

Active-RC Filters 21-4 Analog ICs; Jieh-Tsorng Wu Actively Compensated Inverting Integrator

Thus ω2RC ω2 ω ωRC ω τ ≈ RC q = 1 − − u2 ≈ 1 − u2 2 ωu2 ωu1 |A (jω)| ωu1 ωu2 2 |A (jω)| ⇒ = ωτ = 2 QI q 1 − ωu2 ωu1

= = = If A1(s) A2(s) A(s) ωu/s, then

ω4RC ωRC τ ≈ RC q = − = − 3 | |3 ωu A(jω) 3 ⇒ = − ω = −| |3 QI A(jω) ωu

Active-RC Filters 21-5 Analog ICs; Jieh-Tsorng Wu Noninverting Integrator

C R1 C R1

R R1 R R1 Vi Vo Vi Vo A1 A2 A1 A2

= = Let A1 A2 A = = Let A1 A2 A

Vo 1 1 = · Vo 1 1 3 1 2 2 = · Vi sRC 1 + + + + 1 1 A sRCA A2 sRCA2 V sRC + + i 1 A sRCA 1 = −| | Q = − |A(jω)| QI A(jω) I 3

Active-RC Filters 21-6 Analog ICs; Jieh-Tsorng Wu Phase-Lead Noninverting Integrator

A2 R V 1 1 o(s) = R Vi 1 + 1 + 1 sRC + 1 2/A 2(s) A1(s) sR1CA1(s) Vi Vo A1

= = = If A1(s) A2(s) A(s) ωu/s, then

ω Q ≈ + u =+|A(jω)| I ω

Active-RC Filters 21-7 Analog ICs; Jieh-Tsorng Wu First-Order Filters

State-Variable Topology 1 Fully-Differential Active-RC Filter R2 + C1 α1s α0 1 V V i sτ o R1 C

Active-RC Filter Vi Vi Vo R2 C 1 C R1 Vi R1 C C V V 1 i o R2

V α s + α ±sC + G R ±sR C + 1 o = − 1 0 = − 1 1 = − 2 · 1 1 + + + Vi sτ 1 sC G2 R1 sR2C 1

Active-RC Filters 21-8 Analog ICs; Jieh-Tsorng Wu Single-Ampliﬁer 2nd-Order Filters —Sallen-Key LP Biquad

C1 C1

GG1 G2 a 1 G2 Vi Vo Vi Vo A A C2 C2

RB (1-a) G RB RA 1 RA

KG G 1 V 1 21+K/A H(s) = o = Vi s2C C + s C (G + G ) + C C 1 − K 1 + G G 1 2 2 1 2 1 2 1+K/A 1 2 R K = a · 1 + B a ≤ 1 RA

Active-RC Filters 21-9 Analog ICs; Jieh-Tsorng Wu Single-Ampliﬁer 2nd-Order Filters —Sallen-Key LP Biquad

= ∞ = = Let A and C1 C2 C, then

2 2 KG G /C ωp H(s) = 1 2 = K · 2 + + − + 2 2 + + 2 s s[G1 G2(2 k)]/C G1G2/C s sωp/Q ωp G G G G R ω2 = 1 2 Q = 1 2 K = a · 1 + B p 2 + − C G1 G2(2 K ) RA = = = If a 1, R1 R2 R,wehave

1 1 ω = Q = SQ = 3Q − 1 p RC 3 − K K

• Minimal use of opamp, at the expense of more passive components.

• Sensitive to parasitic capacitors.

• Widely used to realize the on-chip anti-aliasing and reconstruction ﬁlters.

Active-RC Filters 21-10 Analog ICs; Jieh-Tsorng Wu Single-Ampliﬁer 2nd-Order Filters —Sallen-Key LP Biquad

======Let a 1, R1 R2 R, C1 C2 C, A ωu/s,

ω2 1 2 − p1+K/A ωp(1 K/A) H(s) = K · ≈ K · 1 2 2 + − − + 2 s2 + sω 3 − K + ω s sωp 3 K (1 K/A) ωp p 1+K/A p 2 − 2 − ωp(1 sK/ωu) ωp (1 K/ωu) ⇒ H(s) ≈ K · = K · 2 + + − + 2 2 + + 2 s (1 ) sωp(3 K ) ωp s sωp/Q ωp ω = p ≈ − = − = + ≈ + = + ωp √ ωp 1 ωp ∆ωp Q Q 1 Q 1 Q ∆Q 1 + 2 2 2 ωp K = K 2 = | | ωu A(jωp)

• H (s) has an additional positive zero at ωu/K .

• The Sallen-Key biquad is a good low-Q LP ﬁlter with small ωu-caused deviations.

Active-RC Filters 21-11 Analog ICs; Jieh-Tsorng Wu State-Variable Second-Order Filters

1/Q

K 1 1 VV i sτ sτ l Vh Vb

V s2 s2 h =+K · = K · V 2 + + 2 2 + + 2 i s s/(Qτ) 1/τ s sωp/Q ωp sω Vb s/τ p 1 1 = −K · = −K · ω = √ = V 2 + + 2 2 + + 2 p i s s/(Qτ) 1/τ s sωp/Q ωp τ1τ2 τ 2 2 V 1/τ ωp l = −K · = −K · V 2 + + 2 2 + + 2 i s s/(Qτ) 1/τ s sωp/Q ωp

Active-RC Filters 21-12 Analog ICs; Jieh-Tsorng Wu State-Variable Second-Order Filters

For integrators with ﬁnite quality factors, let

− 1 →− 1 + 1 → + 1 + + sτ τ(sα1 σ1) sτ τ(sα2 σ2)

The new ωp and Q are 2 ωp 1 σ σ σ ω 2 = 1 + · 2 + 1 2 p α α Q ω 2 1 2 p ωp ω = p · Q Q α σ +α σ ωp α + Q · 2 1 1 2 2 ωp

Active-RC Filters 21-13 Analog ICs; Jieh-Tsorng Wu Tow-Thomas (TT) Biquad

RQ C Rx

R/K C RRx Vi Vl A1 A2 A3

2 V ωps V ωp 1 b = −K · l = −K · ω = V 2 + + 2 V 2 + + 2 RC i s sωp/Q ωp i s sωp/Q ωp

The sensitivities for any passive component x are

ωp = − Q ≤ Sx 1/2 Sx 1

Active-RC Filters 21-14 Analog ICs; Jieh-Tsorng Wu Tow-Thomas (TT) Biquad

= = = Let A1 ωu1/s, A2 ωu2/s, and A3 ωu3/s, then 2 1 1 ωp 1 ω − →− α = 1 + 1 + K + σ = − + 1 1 sτ τ(sα1 σ1) ωu1 Q ωu1 2 2 1 1 ωp ω ω + → + α = 1 + σ = − − 2 + 2 2 sτ τ(sα2 σ2) ωu2 ωu2 ωu3

Assuming matched opamps and ωp ωu,wehave

ω − ω ∆ω + ω + p p = p ≈−2 K · p = −2 K · 1 | | ωp ωp 2 ωu 2 A(jωp) Q ≈ 1 ← ω Q Enhancement Q 1 − 4Q · p ωu

Active-RC Filters 21-15 Analog ICs; Jieh-Tsorng Wu Ackerberg-Mossberg (AM) Biquad

Rx C Rx RQ A3

R/K C R Vi Vl A1 A2

= = = Let A1 ωu1/s, A2 ωu2/s, and A3 ωu3/s, then

− 1 →− 1 + 1 → + 1 + + sτ τ(sα1 σ1) sτ τ(sα2 σ2)

Active-RC Filters 21-16 Analog ICs; Jieh-Tsorng Wu Ackerberg-Mossberg (AM) Biquad where ω 2 ω 2 2 = + p + + 1 = − ω = + p =+ 2ω − ω α1 1 1 K σ1 α2 1 σ2 ωu1 Q ωu1 ωu2 ωu3 ωu2

If Q 1, we have

ω − ω ∆ω ω ω 1 + ∆ω /ω p p = p ≈−1 + p + p Q ≈ p p (1 K ) ω ωp ωp 2 ωu1 ωu2 Q 1 + p + Q · D ωu2 2 2 + 2ωp ωp ωp ωp ωp(1 K ) 2 1 D = − − − + − ωu3 ωu1 ωu2 ωu1ωu2 ωu1 ωu3 ωu2

For matched opamps, we have

ω 1 − 1 + K p Q 2 ωu ≈ Q ω ω 2 1 + p + QK p ωu ωu

Active-RC Filters 21-17 Analog ICs; Jieh-Tsorng Wu Arbitrary Transmission Zeros by Summing

1/Q

K 1 Vb 1 V V i sτ sτ l Vh a2 a1 a0 Vo

2 2 2 V −a · Ksω − a · Kω a s + s(ω /Q)[a − a (KQ)] + ω [a − a K ] o = + 1 p 2 p = 0 p 0 1 p 0 2 a0 V 2 + + 2 2 + + 2 i s sωp/Q ωp s sωp/Q ωp

Active-RC Filters 21-18 Analog ICs; Jieh-Tsorng Wu Arbitrary Transmission Zeros by Voltage Feedforward

Rx C Rx RQ A3

R/K C R Vi Vo2 A1 A2

aC Vo1 R/c

R/b

2 2 V as + sω (K − b) + cω o1 = − p p V 2 + + 2 i s sωp/Q ωp

Active-RC Filters 21-19 Analog ICs; Jieh-Tsorng Wu High-Order Filter Using Cascade Topology

Vo,1 Vo,2 Vi T1(s) T2(s) Tn(s) Vo

|t(jω)| jω Passband M

ω ωmin ωmax ωL ωU

Active-RC Filters 21-20 Analog ICs; Jieh-Tsorng Wu High-Order Filter Using Cascade Topology

• Each stage is a biquad, i.e,

a s2 + a s + a = · 2,i 1,i 0,i = · | | = Ti (s) ki ki ti (s) ti (jωp,i ) 1 2 + + 2 s sωp,i /Qp,i ωp,i

| | = ki is deﬁned as gain constant, such that ti (jωp,i ) 1.

• No interaction between stages, therefore

V (s) n n H(s) = o = T (s) · T (s) · T (s) ···= T (s) = k t (s) V (s) 1 2 3 i i i i i=1 i=1

• Easy to tune.

• Sensitive to component variation in the passband for high-order ﬁlter, e.g., order > 8.

Active-RC Filters 21-21 Analog ICs; Jieh-Tsorng Wu High-Order Filter Using Cascade Topology

To maximize dynamic range want

| | ≤ ∞ | |→ ≤ ≤ max Vo,i

• Vo,max is the maximum undistorted signal level, which is limited by power supply or by the slew rate of the opamps.

• Large signal even outside the passband must not overload the opamps.

• Signal-to-noise ratio is of no interest in the stopband.

Active-RC Filters 21-22 Analog ICs; Jieh-Tsorng Wu Cascaded Filter Design Procedures

| | 1. Pole-Zero Pairing.Everyti (jω) should be as ﬂat as possible in the ω of interest, i.e., M(t ) max log i ← Minimize i = 1, ··· ,n m(ti )

• A good suboptimal solution is assigning each zero or zero pair to the closest pole.

| | | | 2. Section Ordering.EveryVo,i (jω) or Hi (jω) should be as ﬂat as possible in the ω of interest, i.e., M(H ) max log i ← Minimize i = 1, ··· ,n m(Hi ) • The section sequence in the order of increasing Qp is often close to the optimum.

• It is often desirable to have a low-pass or bandpass biquad as the ﬁrst section to minimize slew-rate problem.

• If possible, employ a high-pass or band-pass biquad as the last section to eliminate low-frequency noise and dc oﬀset.

Active-RC Filters 21-23 Analog ICs; Jieh-Tsorng Wu Cascaded Filter Design Procedures

3. Gain Assignment.EveryVo,i should be as large as possible, i.e.,

= = ···= M(Vo,1) M(Vo,2) M(Vo)

Since

i i i i i

H (s) = k t (s) = k t (s) K = k M = max t (jω) i i i i i i j i j j=1 j=1 j=1 j=1 j=1 → = → = = Filter Speciﬁcation H(s) Hn(s) K Kn M Mn

We have

· = · = · = ··· − Ki Mi Kn Mn K Mi1, ,n 1 M ⇒ = · M = i−1 = ··· − k1 K and ki i 2, ,n 1 M1 Mi

Active-RC Filters 21-24 Analog ICs; Jieh-Tsorng Wu Cascaded Filter Design Procedures

Active-RC Filters 21-25 Analog ICs; Jieh-Tsorng Wu High-Order Filter Using the Follow-the-Leader Feedback Topology

RF,n

RF,2

RF,1

RF,0

Ri Vi T1(s) T2(s) Tn(s)

V0 V1 V2 Vn

Ro,n RA

R o,2 Vo Ro,1

Ro,0

Active-RC Filters 21-26 Analog ICs; Jieh-Tsorng Wu High-Order Filter LC Ladder Simulation

R V Y2 Y4 Y(n-1) V S 1 2

I V 1 Z1 Z3 Z(n-2) Z(n) R S L

Lossless LC Network

A Fifth-Order Elliptic Low-Pass Filter R V V S 1 2

V R S L

Active-RC Filters 21-27 Analog ICs; Jieh-Tsorng Wu High-Order Filter LC Ladder Simulation

• Minimum passband sensitivity to component tolerances.

• Can be implemented with Ð Element substitution. Ð Operational simulation with signal-ﬂow graph.

• Requires more opamps than the cascade and MF methods.

Active-RC Filters 21-28 Analog ICs; Jieh-Tsorng Wu LC Ladder Simulation R Y 2 Y 4 Y n-1 S

V Z 1 Z 3 Z n-2 Z n R S L

I k-1 I k+1

V k-2 I k-2V k-1 V k I k V k+1 V k+2I k+2

Z k-2 Y k-1 Z k Y k+1 Z k+2

I k-1 I k+1 I k+3

Z k-2 Y k-1 Z k Y k+1 Z k+2

V V k-2V k k+2

Active-RC Filters 21-29 Analog ICs; Jieh-Tsorng Wu LC Ladder Simulation

I k-1 I k+1 I k+3

Z k-2 Y k-1Z k Y k+1 Z k+2

V V k-2V k k+2

Leapfrog (LF) Topology

Z k-2 Y k-1 Z k Y k+1

Active-RC Filters 21-30 Analog ICs; Jieh-Tsorng Wu An All-Pole Low-Pass Ladder Filter I I I 0 2 4 V V V V 1 3 5 out

R L2 L4 V S C1 C3 C5 I R in 6 L

V V V V 0 2 4 6

1/RS -1/(sC1 ) 1/(sL2) -1/(sC 3) 1/(sL4) -1/(sC 5) 1/RL

V V in out V V V 1 3 5

V 1/R V V in S 2 4

R R S L 1+sR C 1+sR C S 1 L 5

V V V 1 5 out

Active-RC Filters 21-31 Analog ICs; Jieh-Tsorng Wu An All-Pole Low-Pass Ladder Filter R 1 V 11V 1 S 2 4 V in

C 3 R C L L RC S 1 2 4 L5

V out V V V 1 111 3 1 5

• Component scaling can be done by maintaining the RC values.

• Use both lossless and lossy integrators.

• Combining the phase-lag Miller inverting integrator with the phase-lead noninverting integrator can reduce phase errors.

Active-RC Filters 21-32 Analog ICs; Jieh-Tsorng Wu Signal-Level Scaling in Ladder Filters

V0 V2 V’0 V’2 α1 1/α2 α3

T0(s) T1(s) T2(s) T3(s) T0(s) T1(s) T2(s) T3(s)

Vi Vo Vi 1/α1 α2 1/α3oV K0 V1 V3 K1 V’1 V’3

V = · = · ⇒ = · · j−1 Vj Hj (s) Vj−1 Vj αj Hj (s) Vj−1 Vj Vj αj Vj−1

• The signal level of Vj can be scaled by αj .

• Signal-level scaling is to maximize dynamic range. Want

| | = = ··· ∞ max Vj (jω) Vo,max for j 0, ,n 0 <ω<

• = = Scale Vj sequentially from j 1toj n.

Active-RC Filters 21-33 Analog ICs; Jieh-Tsorng Wu General Ladder Branches Series Branch Shunt Branch L I1 I3 4 V2

V1 V3 R0 L1 C2 L3 C3 C4 I2 R0 C1 L2

For the series branch 1 I = (V − V ) · Y (s) = (V − V ) · 2 1 3 1 3 + + 1 + 1 R0 sL1 sC + 1 2 sC3 sL4 For the shunt branch 1 V = (I − I ) · Z(s) = (I − I ) · 2 1 3 1 3 + + 1 + 1 G0 sC1 sL + 1 2 sL3 sC4

Active-RC Filters 21-34 Analog ICs; Jieh-Tsorng Wu General Ladder Branches by Active-RC Implementation

R=1 R=1 C3

R=1 R=1 C2

R=1 R=1 C1 Ra V1 R0 Rb V3 V2

V V 1 V = − 1 − 3 · 2 R R + + 1 + 1 a b G0 sC1 sC + 1 2 sC3 sC4

Active-RC Filters 21-35 Analog ICs; Jieh-Tsorng Wu Finite Transmission Zeros in the Series Branches

C2 C2 I0 I4 V1 V3 L2

1 1 11 C1 C3 V2 C 2 V0 V4

I2 I0 I4 V1 V3 C3 C2 C1 C2 L2 L2 C1 C2 C3 C2

V 1 V1 1 1 3 1 sCC2V3 s 2V1

= + + − = + − − − I0 sC1V1 (sC2 Y2)(V1 V3) s(C1 C2)V1 sC2V3 Y2(V1 V3) = + − − = − + − + I4 (sC2 Y2)(V1 V3) sC3V3 Y2(V1 V3) sC2V1 s(C2 C3)V3

Active-RC Filters 21-36 Analog ICs; Jieh-Tsorng Wu MOST-C and Gm-C Filters

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering MOSTs in the Triode Region

VG V VK = G VFB Flat-Band Voltage Allowalbe = ≈ V φ0 Surface Band Bending 2φf 0 Operating Range V V D S γ = Body Eﬀect Coeﬃcient ID VQ V W B VB k = µC ox L γ2 γ2 V = V + φ − + γ V − V + V ← Model Accuracy Consideration K FB 0 2 GB FB 4 Q ID 1 2 2 2 3 3 = (V − V − φ )(V − V ) − V − V − γ (V + φ )2 − (V + φ )2 k GB FB 0 DB SB 2 DB SB 3 DB 0 SB 0 = − − − − (VGB VFB φ0)VDS [f (VDB) f (VSB)]

1 2 2 3 1 2 2 3 f (V ) = V + γ(V + φ )2 = (V + V ) + γ(V + V + φ )2 XB 2 XB 3 XB 0 2 X 0 0B 3 X 0 0B 0

Gm-C Filters 22-2 Analog ICs; Jieh-Tsorng Wu MOSTs in the Triode Region

Using Taylor’s series 1 2 1 2 2 3 1 f (V ) ≈ V + V · V + V + γ(V + φ )2 + γ(V + φ )2 · V XB 2 0B 0B X 0 2 X 0 3 0B 0 0B 0 X 0

1 −1 2 1 −3 3 + γ(V + φ ) 2 · V − γ(V + φ ) 2 · V + ··· 4 0B 0 X 0 24 0B 0 X 0

We have

ID 1 = (V − V )V − g(V ) − g(V ) V = V + φ + γ(V + φ )2 k G0 T DS D0 S0 T FB 0 0B 0 = + − = − = − g(VX 0) ge(VX 0) go(VX 0) ge( VX 0) ge(VX 0) go( VX 0) ge(VX 0)

1 2 1 −1 2 g (V ) = · V + γ(V + φ ) 2 · V + ··· e X 0 2 X 0 4 0B 0 X 0

1 −3 3 g (V ) = − γ(V + φ ) 2 · V + ··· o X 0 24 0B 0 X 0

Gm-C Filters 22-3 Analog ICs; Jieh-Tsorng Wu MOSTs in the Triode Region

Thus = − = − × = × = − ID IL IN IL k(VG0 VT ) VDS G VDS IN k g(VD0) g(VS0)

• Both ge and go are independent of VG.

• − go(VD0) go(VS0) is very small comparing to IL (e.g., 0.1 percent of it or less).

• − ﬀ ge(VD0) ge(VS0) can be large and its e ect must be eliminated to obtain a linear resistor.

• If only IL is considered, the resistance between VD and VS is

I = D = − = W − G k(VG0 VT ) µCox (VG0 VT ) VDS L

Gm-C Filters 22-4 Analog ICs; Jieh-Tsorng Wu MOST-C Fully-Balanced Integrators

C C VG I R M1 1 Vi V o Vi1 Vo1 V0 Vi2 Vo2 M2 I2 VG C

V V V V =+ i + = − i + =+ o + = − o + Vi1 V0 Vi2 V0 Vo1 V0 Vo2 V0 2 2 2 2 V V V I = G × + i − g + i − g (0) − g + i − g (0) 1 2 e 2 e o 2 o V V V I = G × − i − g − i − g (0) − g − i − g (0) 2 2 e 2 e o 2 o V I − I = G × V − 2g i ≈ G × V G = k(V − V − V ) 1 2 i o 2 i G 0 T

Gm-C Filters 22-5 Analog ICs; Jieh-Tsorng Wu MOST-C Fully-Balanced Integrators

Therefore V (s) I (s) − I (s) o = 1 2 · − 1 = − G Vi (s) Vi (s) sC sC

• Even-order nonlinearities are eliminated.

• The common-mode voltage along the diﬀerential signal path must be maintained at

V0.

• Linearities around 50 dB have been achieved.

Gm-C Filters 22-6 Analog ICs; Jieh-Tsorng Wu Double MOST-C Diﬀerential Integrators

VGA M1 V =+ i + Vi1 V0 C 2 VGB Vi I1 V = − + V M3 i2 2 0 V V i1 o1 V =+ o + Vo1 V0 Vi2 Vo2 2 M4 I V 2 V = − o + V VGB o2 2 0 C G = k (V − V − V ) M2 A 1,2 GA 0 T = − − VGA GB k3,4 (VGB V0 VT ) V V V V I = G × + i − g + i − g (0) + G × − i − g − i − g (0) 1 A 2 2 B 2 2 V V V V I = G × − i − g − i − g (0) + G × + i − g + i − g (0) 2 A 2 2 B 2 2

Gm-C Filters 22-7 Analog ICs; Jieh-Tsorng Wu Double MOST-C Diﬀerential Integrators

We have V (s) I (s) − I (s) G − G − = − × o = 1 2 · − 1 = − A B I1 I2 (GA GB) Vi Vi (s) Vi (s) sC sC

• Both even-order and odd-order nonlinearities are eliminated.

• Diﬀerential signals are not required to be fully balanced.

• Around 10 dB linearity improvement over the two-transistor MOST-C integrators.

• Linearity performance is limited by the deviation of the above device model and mismatches among the MOSTs.

• Reference: Ismail, JSSC 2/88, pp. 183–194.

Gm-C Filters 22-8 Analog ICs; Jieh-Tsorng Wu R-MOST-C Diﬀerential Integrators

V CA R2 M1

V C CB R1 M3 V V i1 o1 V V i2 o2 M4 R1 V CB C M2 V R CA 2

Gm-C Filters 22-9 Analog ICs; Jieh-Tsorng Wu R-MOST-C Diﬀerential Integrators

V R /R o = − 2 1 Vi + RM1 + sC R2 1 1 R1 R2 RM2

• The dc gain is not adjustable.

• The integrator’s time constant can be varied by changing RM1 and RM2

• At low-frequencies, the linear resistors, R1 and R2, dominate the transfer function, thus reducing distortion. A linearity of 90 dB has been achieved.

• In the criss-cross version, M3 and M4 reduce the eﬀective dc gain and bandwidth of the integrator, enhance the unity-gain frequency sensitivity to component mismatches, and increase noises.

• Reference: U-K Moon, et al., JSSC 12/93, pp. 1254–1264.

Gm-C Filters 22-10 Analog ICs; Jieh-Tsorng Wu A MOST-C Tow-Thomas Biquad

VG MR

VG MRQ C VG VG C MR/K MR

Vi Vb Vl M M R/K C R VG VG C

MRQ VG

MR VG

Gm-C Filters 22-11 Analog ICs; Jieh-Tsorng Wu Transconductors

Ideal Model Nonideal Model Io Io

Io V G V V i m i i g Ci o

V G V I V i m i o i g Ci Io o Io

= × Io Gm Vi

Gm-C Filters 22-12 Analog ICs; Jieh-Tsorng Wu Transconductor Basic Circuits

Controlled Resistance Voltage Amplifier Lossless Integrator

Vi1 Gm1 Vi Gm1 Vo Gm3 Vo G m1 C Z i Vi2 Gm2

Vi Gm1 C Vo

Vi1 Gm1 Gm3 Vo 2C Gm1 Vi Gm1 Vo Z i Vi2 Gm2 2C

V (s) G = 1 = 1 · − o = − m Zi Vo (Gm1Vi1 Gm2Vi2) Gm1 Gm3 Vi (s) sC

Gm-C Filters 22-13 Analog ICs; Jieh-Tsorng Wu Gm-C Lossy Integrator

Vi Gm1 Gm2 Vo Gm1 Vo C V i C Gm2 GGm1 =m2 C Vo

VioGGm1 C m2 VVi Gm1

V (s) G o = − m1 + Vi (s) sC Gm2

• Since no feedback for the integrators, they can be wide-band.

• A transconductor’s output current should be linearly related to the input over the entire input voltage range.

Gm-C Filters 22-14 Analog ICs; Jieh-Tsorng Wu ﬀ Fully-Di erential Gm-C Integrators

2C Cp Cp

Vi Gm VoiVi Gm Vo V Gm Vo

C Cp 2C Cp C

V (s) G o = − m + Vi (s) s(C Cp/2)

• Can use only grounded capacitors.

• ﬀ The Cp can a ect the integration time constant.

• Partially nonlinear Cp can also cause linearity problems.

Gm-C Filters 22-15 Analog ICs; Jieh-Tsorng Wu Gm-C Opamp Integrators (Miller Integrators)

VDD VDD 2C

Io Cp

Vi Gm Vo VB 2C 2C VB Vo C Io p Io I 2C o VSS VSS V (s) G o = − m Vi (s) sC

• The eﬀects of parasitic capacitances are reduced.

• The Gm’s output stage can be simpliﬁed, since no large voltage swing is required.

• The lower impedances at the Gm’s output nodes make those nodes less sensitive to capacitive coupling of noise.

Gm-C Filters 22-16 Analog ICs; Jieh-Tsorng Wu Gyrators

I1 I2 Grounded Inductor V1 V V V 1 2 1 C L1

GGm2 m1 Model I1 I2 Floating Inductor

L2 V1 V2 V1 V2 C V1 V2 GGGGm2 m1 m1 m2 Gm1V 2 Gm2V1

C C L = L = 1 · 2 · Gm1 Gm2 Gm1 Gm2

Gm-C Filters 22-17 Analog ICs; Jieh-Tsorng Wu Gm-C Simulated Gyrators

Gyrator Simulated Grounded Inductor

V1 GGm2 m1 V2 V1 Gm2 Gm1 C

V1 GGm2 m1 V2 V1 Gm2Gm1 C

Simulated Floating Inductor

V1 GGGGm2m1 m1 m2 V2 C

V1 GGGGm2m1 C m1 m2 V2

Gm-C Filters 22-18 Analog ICs; Jieh-Tsorng Wu MOST Transconductors

Io1 Io2 Io1 Io2

1/2 1/2 Vi1 Vi2 Vi1 Vi2 1 1

Tuning Tuning 0.85 I 0.15 I VSS VSS

Gm-C Filters 22-19 Analog ICs; Jieh-Tsorng Wu MOST Transconductors

Adaptive Source Degeneration Bias Oﬀset Linearization

I I Io1 Io2 o1 o2

Vi1 Vi2

Vi1 Vi2 M1 M2 V B V B M3 M4 Tuning

VSS

Gmo/ Gm VSS 1 Let M1=M2=M3=M4,

1 I = k (V − V )2 D 2 GS T -1 0 1 = = − G/moVi IBias Io1 Io2 kVB (Vi1 Vi2)

Gm-C Filters 22-20 Analog ICs; Jieh-Tsorng Wu MOST Transconductors with Source Degeneration

Io1 Io2

Vi1 M3 M4 Vi2 Io1 Io2 M1 V M2 CA Vi1 M1 M2 Vi2 MA V’i1 V’i2 V V C Ia CB MA MB V’i1 V’i2 V’i1 V’i2 Ia Ib

VSS VSS Fully Balanced Type Double-MOST Type

Gm-C Filters 22-21 Analog ICs; Jieh-Tsorng Wu MOST Transconductors with Source Degeneration

Let V V V =+ i + V V = − i + V G = k(V − V − V ) i1 2 0 i2 2 0 C 0 t For the fully balanced diﬀerential transconductor V V V V I = G × V − g + i − g − i − g + i − g − i a i e 2 e 2 o 2 o 2 V I − I = 2I ≈ 2G × V − 2g + i ≈ 2G × V o1 o2 a i o 2 i

For the double-MOSFET diﬀerential transconductor V V V V I = G × V − g + i − g − i I = G × V − g + i − g − i a A i 2 2 b B i 2 2 − = − = − × Io1 Io2 2(Ia Ib) 2(GA GB) Vi

Gm-C Filters 22-22 Analog ICs; Jieh-Tsorng Wu BJT Transconductors

Io1 Io2 Io1 Io2

Vi1 Q1 Q2 Vi2 Vi1 Q1 Q2 Vi2

VEE VEE VEE

g m Multi-tanh Doublet Total Io1 Io2 Q2-Q4

Q1-Q3 4x1x 1x 4x Vi1 Q2 Q3 Vi2 Q1 Q4

V i VOS VOS VOS V = kT ln IS1 OS q I 2 VEE S

Gm-C Filters 22-23 Analog ICs; Jieh-Tsorng Wu Multi-Input Transconductors

VDD

M4 VB1 Io Va Gma M3

Vo M5 Vb Gmb M6 VB2 Io Io

Gma Gmb Vo

M7 Io M8 VB3 Va Vb M9 V = · + · M10 B4 Io Gma Va Gmb Vb

VSS

• Need only one output common-mode feedback.

• Reference: Edited by Y.P. Tsividis and J.O. Voorman, “Integrated Continuous-Time Filters”, IEEE Press, 1993.

Gm-C Filters 22-24 Analog ICs; Jieh-Tsorng Wu Transconductor’s Imperfections

Nonideal Model Io Vo Vi Gm1 Vo VV i g i g C Ci o Ci o C

G ω I = G (s) × V G (jω) = m ≈ G e−jφ φ = tan−1 o m i m + m ω 1 jω/ω2 2

For the Gm-C integrator

V G G g o = m × 1 = m = o ωo V + sC + g ωo 2 C i 1 s/ω2 o sC 1 + + g 1 + s ω2 o ωoω2

Gm-C Filters 22-25 Analog ICs; Jieh-Tsorng Wu ﬀ The E ect of Non-Zero go on Gyrators

Vi G m go L Vi 1 C go Vi Gm Gm R C s G go m

C g L = R = o 2 s 2 Gm Gm

Gm-C Filters 22-26 Analog ICs; Jieh-Tsorng Wu The Eﬀect of Phase Shift on Gyrators

Vi Gm Vi L C R 1 Vi Gm Gm p C Gm

If = −jφ = −1 ω ≈ ω Gm(jω) Gme φ tan 1 ω2 ω2 We have

2 2 C 1 2G 2G 2 L = ≈− m · φ ≈− m = − 2 R ωC ω C ω L Gm p 2 2

Gm-C Filters 22-27 Analog ICs; Jieh-Tsorng Wu Gm-C First-Order Filters

Vi2 + G α1s α0 1 m4 V V i sτ o Vi1 Gm1 Gm5 Vo Gm2 G C m3

Gm1 = Gm2 Gm1 Vi1 Gm3 Vo Gm3 ==Gm4 Gm5 V C i2

G V 1 sCG V + (G G V + G G V ) H(s) = − m1 i1 · G + G V · = − m4 i2 m1 m3 i1 m2 m4 i2 + m3 m4 i2 + · sC Gm2 Gm5 (sC Gm2) Gm5

• The output requires another buﬀer to prevent loading eﬀects.

• Use only grounded capacitors.

Gm-C Filters 22-28 Analog ICs; Jieh-Tsorng Wu Gm-C Second-Order Filters

Gm4 1/Q Vo3 Gm5 V Gm3 i3 K 1 1 V V i sτ sτ l Vh Vb

Vo1 Gm1 Vi1 Gm2 Vo2 G m4 C1 C2 V Vi2 = Vi3 = 0 i2 Gm1 Gm3 = Gm5 Vi1 Vb Gm2 Vl C1 C2

sC G G G V = 2 m1 V = − m1 m2 b 2 + + l 2 + + s C1C2 sC2Gm1 Gm2Gm4 s C1C2 sC2Gm1 Gm2Gm4

Gm-C Filters 22-29 Analog ICs; Jieh-Tsorng Wu Gm-C Second-Order Filters

The transfer functions are

= · − + Vo1 [1/D(s)] [sC2Gm1(Gm5Vi1 Gm4Vi3) Gm1Gm2Gm4Vi2] = · + − Vo2 [1/D(s)] [(sC1Gm2Gm5 Gm1Gm2Gm3)Vi2Gm1Gm2(Gm4Vi3 Gm5Vi1)] V = [1/D(s)] · [s2C C G V + s(C G G V − C G G V ) + G G G V ] o3 1 2 m4 i3 2 m1 m3 i1 1 m2 m4 i2 m1 m2 m4 i1 G G G G G = 2 + 1 m1 m3 + m1 m2 m4 D(s) C1C2Gm5 s s C1 Gm5 C1C2Gm5 = = If Vi1 Vi2 0, then

V sC G G o1 = = − 2 m1 m4 HBP(s) Vi3 D(s) V G G G o2 = = m1 m2 m4 HLP(s) Vi3 D(s) V s2C C G o3 = = 1 2 m4 HHP(s) Vi3 D(s)

Gm-C Filters 22-30 Analog ICs; Jieh-Tsorng Wu Gm-C Second-Order Filters

= = = If Vi1 Vi2 Vi3 Vi , then

V s2C C G + s(C G G − C G G ) + G G G o3 = 1 2 m4 2 m1 m3 1 m2 m4 m1 m2 m4 Vi D(s)

• = If C2Gm1Gm3 C1Gm2Gm4, it is a band-reject biquad.

• = = If C1Gm2Gm4 2C2Gm1Gm3 and Gm4 Gm5, it is an allpass biquad.

• There is one parasitic pole in the biquad.

Gm-C Filters 22-31 Analog ICs; Jieh-Tsorng Wu Gm-C First-Oder Filters Using Miller Integrators

+ 2CX 2CA α1s α0 1 V V i sτ o

Vi Gm1 Vo CX

Gm2 2CX 2CA Vi Gm1 Vo Gm2 CA

Gm-C Filters 22-32 Analog ICs; Jieh-Tsorng Wu Gm-C First-Oder Filters Using Miller Integrators

Without the Miller Integrator

s CX + Gm1 V α s + α C +C C +C o = 1 0 = A X A X + Vi s ωo + Gm2 s + CA CX α G = α (C + C ) G = ω (C + C ) C = C 1 where 0 ≤ α < 1 m1 0 A X m2 o A X X A − 1 1 α1

With the Miller Integrator

s CX + Gm1 V α s + α C C o = 1 0 = A A s + ω G Vi o s + m2 CA

• The use of feed-in capacitors can simplify design, but requires inputs of low source impedance.

Gm-C Filters 22-33 Analog ICs; Jieh-Tsorng Wu Gm-C Second-Oder Filters Using Miller Integrators

1 1/Q

α0 1 1 V V i sτ sτ o + α1 α2s

2CA 2CB

Gm1 Gm2 Vo

2CA 2CB

2CX

Vi Gm4 Vi Gm5 Gm3

2CX

Gm-C Filters 22-34 Analog ICs; Jieh-Tsorng Wu Gm-C Second-Oder Filters Using Miller Integrators

The transfer function is

2 C G G G 2 s X + s m5 + m2 m4 V α s + α s + α C C C C o = 2 1 o = B B A B ω Vi s2 + p + ω2 s2 + s Gm3 + Gm1Gm2 Q p CB CACB

Thus = CX α2CB and

ω C α C = = = p B = 0 A = Gm1 ωpCA Gm2 ωpCB Gm3 Gm4 Gm5 α1CB Q ωp

Gm-C Filters 22-35 Analog ICs; Jieh-Tsorng Wu Ladder Filter Using Simulated Gyrators

C2 Vo

R L2 V SR i C1 C3 L

Single-Ended Implementation C2 V Vi o

Gmi GGGGGGmS m2 m1 m1 m2 mL C

C1 C3

Fully Differential Implementation C2

Vi GGGmi mSm2 GGm1 m1 GGm2 mL Vo

C1C C3

Gm-C Filters 22-36 Analog ICs; Jieh-Tsorng Wu Ladder Filter Using Simulated Gyrators

• Inductors are replaced with Gm-C gyrators.

• Floating capacitors are required.

• Finite go of the transconductors results in lossy inductors and capacitor, i.e., Q degradation; while phase shift causes Q enhancement.

• The Q-control automatic tuning circuits may be required.

Gm-C Filters 22-37 Analog ICs; Jieh-Tsorng Wu Ladder Filter Using Signal-Flow Graph

I I I 0 2 4 V V V V 1 3 5 out

R L2 L4 V S C1 C3 C5 I R in 6 L

V V V V 0 2 4 6

1/RS -1/(sC1 ) 1/(sL2) -1/(sC 3) 1/(sL4) -1/(sC 5) 1/RL

V V in out V V V 1 3 5

V V V V 0 2 4 6 GmL GmS C1 C2 C3 C4 C5

V V V V V in 1 3 5 out

Gm-C Filters 22-38 Analog ICs; Jieh-Tsorng Wu Ladder Filter Using Signal-Flow Graph

• Floating capacitors are not necessary.

• Finite go of the transconductors results in lossy inductors and capacitor, i.e., Q degradation; while phase shift causes Q enhancement.

• Signal-level scaling is possible.

Gm-C Filters 22-39 Analog ICs; Jieh-Tsorng Wu Gm-C Simulation of Ladder Branches (I) Series Branch Shunt Branch L I1 I3 4V2

V1 V3 R0 LC1 2 L3 C3 C4 I2 R0 C1 L2

V1 V1 Gmi1

C2 V3 Gm0 Gmi2 C1

C3 C4

Gm-C Filters 22-40 Analog ICs; Jieh-Tsorng Wu Gm-C Simulation of Ladder Branches (II)

V1 V1 Gmi1

V3 Gm0 C2 Gmi2 C1

Gm-C Filters 22-41 Analog ICs; Jieh-Tsorng Wu Gm-C Simulation of Ladder Branches

The branch characteristics are 1 I = (V − V ) · Y (s) = (V − V ) · 2 1 3 1 3 + + 1 + 1 R0 sL1 sC + 1 2 sC3 sL4 1 V = (I − I ) · Z(s) = (I − I ) · 2 1 3 1 3 + + 1 + 1 G0 sC1 sL + 1 2 sL3 sC4

The Gm-C circuit’s transfer function is 1 V = (G · V − G · V ) · 2 mi1 1 mi2 3 + + 1 + 1 Gm0 sC1 sC + 1 2 sC3 sC4

• Method 2 usually uses more transconductors than method 1, but may have advantages in terms of sensitivity to and compensation for parasitic eﬀects.

• For better matching, use identical transconductors whenever possible.

Gm-C Filters 22-42 Analog ICs; Jieh-Tsorng Wu Gm-C Resonators

V o

I i C1L R

V i G V m1 o C1 G m4 G G m2 m3

Gm-C Filters 22-43 Analog ICs; Jieh-Tsorng Wu Gm-C Resonators

• The inductor L is simulated by Gm2, Gm3, and C2. The resistor R is simulated by Gm4.

• The resonant frequency and the quality factor are 1 G G C G G ω = = m2 m3 Q = ω RC = 1 × m2 m3 o LC C C o 1 C 2 1 1 2 2 Gm4

The voltage gain at the resonant frequency is

v G = o = = m1 Avo Gm1R vi Gm4

• Reference: Silva-Martinez, et al., JSSC 12/92, pp. 1843–1853.

Gm-C Filters 22-44 Analog ICs; Jieh-Tsorng Wu Gm-C Quadrature Oscillators

G m1 V o V G V o m2 LCGLDG C1 C2 GG m3 m4

• The combination of Gm1, Gm2 and C1 simulates an inductor. • = The oscillation frequency is ωo Gm1Gm2/(C1C2).

• = The oscillation condition is Gm4 Gm3. In many cases, Gm3 and Gm4 are not required.

• The nonlinear resistor is used to control the output amplitude.

• Reference: Rodriguez-Vazquez, Transactions on Circuits and Systems, 2/90, pp. 198–211.

Gm-C Filters 22-45 Analog ICs; Jieh-Tsorng Wu On-Chip Tuning Strategies

S in Filter to be Tuned (Slave) S out

Ucntrl

Reference Circuit (Master) Indirect Tuning S ref LPF Control Circuit

S in Filter A to be Tuned S out

Ucntrl

Filter B to be Tuned Direct Tuning

S ref LPF Control Circuit

Gm-C Filters 22-46 Analog ICs; Jieh-Tsorng Wu Separate Frequency and Q Control

S in Filter to be Tuned S out

UF UQ

Ref Ckt 1 Ref Ckt 2

LPF Control Ckt Control Ckt LPF

Freq Tuning Loop Q Tuning Loop S rf S rQ

Gm-C Filters 22-47 Analog ICs; Jieh-Tsorng Wu Gm Tuning

Rext VR C 1 Gm VC VR Gm VR VC Rext C1

• VC is automatically adjusted so that

= 1 Gm Rext

• C1 is an integrating capacitor used to maintain loop stability.

Gm-C Filters 22-48 Analog ICs; Jieh-Tsorng Wu Frequency Tuning Using Switched Capacitors

C 11m

2 2 1 CI = = Gm fsCm Req V R R Gm 1 G V ⇒ m = F fs Cm C1

N I B I B CI 1 1 NI · · = I C B B 1 m 2 G R R m eq Gm 1 V F G ⇒ m = 2 1 Nfs C1 Cm

Gm-C Filters 22-49 Analog ICs; Jieh-Tsorng Wu Frequency Tuning Using Response Detection

Ca Cb Ra Rb

MOST-C Filter

Tuning System C V Peak 1 R Detector

V F Peak Detector R1 V 2 + R2 Vr sin(ωr t θ)

Gm-C Filters 22-50 Analog ICs; Jieh-Tsorng Wu Frequency Tuning Using Response Detection

For this amplitude-response detection scheme

1 R V = V · V = V · 2 1 r 2 r + ωr RC R1 R2

= The feedback adjusts VF so that V1 V2, thus 1 R R · C = · 1 + 1 ωr R2

• The above tuning system is a magnitude locked loop (MLL).

• Usually use ωrRC 1 to place ωr in the ﬁlter stopband.

• Phase-response detection scheme can also be used.

• The reference circuit can be any ﬁlter.

Gm-C Filters 22-51 Analog ICs; Jieh-Tsorng Wu Frequency Tuning Using Phase-Locked Loop

Gm-C Main Filter Variable-Frequency Oscillator

G m G m f o G C m C C

V F

f ref Phase-Freq Low-Pass Detector Filter

Gm-C Filters 22-52 Analog ICs; Jieh-Tsorng Wu Frequency Tuning Using Phase-Locked Loop

The phase-locked loop (PLL) forces

1 G G f = f = · m ⇒ m = 2πf ref o 2π C C ref

• For best matching between the reference VFO and the main ﬁlter, it is best to choose

fref at the upper passband edge. However, the reference signal may leak into the main ﬁlter’s output.

• If fref moves away from the upper passband edge, the matching will be poorer, but an improved immunity to the reference signal results.

• If the VFO is sensitive to supply variation, any power-supply noise can inject jitter into

VF .

Gm-C Filters 22-53 Analog ICs; Jieh-Tsorng Wu Q-Factor Tuning Using MLL

Slave V i V o Filter

ω s = p Hbq(s) Bandpass Peak 2 + ωp + 2 s s ωp Biquad Det Qp

V = ref Vref A sin ωr t V Q Peak Det Q d

• = = = = At s jωr jωp, the MLL forces Hbq(jωp) Qp Qd .

• For high Q biquad, mismatch between ωr and ωp results in large Q-tuning error.

• Distortion in Vref can also cause error.

Gm-C Filters 22-54 Analog ICs; Jieh-Tsorng Wu Q-Factor Tuning Using LMS

Slave V i V o Filter

ω s = p Hbq(s) ω 2 + p + 2 s s ωp Bandpass Qp Biquad 1 = Vref A sin ωr t V ref Q d V Q

dV (t) Q = µ · V (t) − V (t) · V (t) dt ref bq bq

The modiﬁed continuous-time least-mean-squares (LMS) algorithm will force − · = · − 2 = Vref(t) Vbq(t) Vbq(t) Vref(t) Vbq(t) Vbq(t) 0

Gm-C Filters 22-55 Analog ICs; Jieh-Tsorng Wu Q-Factor Tuning Using LMS

= If ωr ωp,

Q Q = p · = · = p · Vbq(t) A sin ωrt B sin ωrtB A Qd Qd A · B B · B LMS ⇒ = ⇒ A = B ⇒ Q = Q 2 2 p d

= If ωr ωp,

Q Q = p · + = · + = p · Vbq(t) cos φ A sin (ωrt φ) B sin (ωrt φ) B cos φ A Qd Qd A · B · cos φ B · B LMS ⇒ = ⇒ A cos φ = B ⇒ Q = Q 2 2 p d

• Insensitive to mismatch between ωr and ωp.

Gm-C Filters 22-56 Analog ICs; Jieh-Tsorng Wu Q-Factor Tuning Using LMS

• Require no peak detector.

• The scheme is also insensitive to Vref waveform shape.

• Square wave can be used for Vref(t).

• Reference: J.-M. Stevenson, et al., An Accurate Quality Factor Tuning Scheme for IF and High-Q Continuous-Time Filters, JSSC 12/1998, pp. 1970–1978.

Gm-C Filters 22-57 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Filters

Jieh-Tsorng Wu

October 23, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Switched-Capacitor Equivalent Resistor

fs V1 V2 φφ1 2 Ts C VV1 2 φ1 C Req φ2 V1 V2

Ieq

C · V − C · V = ∆Q = 1 2 = · − · = 1 Ieq C (V1 V2) fs Ts ∆t Ts fs

1 Ieq G = = = C · f eq − s Req V1 V2

SC Filters 23-2 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Integrators

C2 C2

R1 fs Vi Vo Vi Vo

V G C o = − 1 = −1 · eq1 = −1 · · 1 fs Vi sR1C2 s C2 s C2

• Consist of analog switches, capacitors and opamps.

• Discrete-time (or sampled-data) analog ﬁlters.

• Time constant is determined by capacitance ratio and switching frequency.

SC Filters 23-3 Analog ICs; Jieh-Tsorng Wu SC Integrator Analysis

T C2 s φ1 Q 2 1 2 φ2 Vi Vo Q n-1 n n+1 1 C1 n-1/2 n+1/2

a φ1 CLK φ1 C Va 1 1 Vi z Vo C2

φ2 a φ2

V (z) C −1 o = − 1 × z − −1 Vi (z) C2 1 z

SC Filters 23-4 Analog ICs; Jieh-Tsorng Wu SC Integrator Analysis

= = = At cycle n, i.e., t nTs,wehaveQ1(n) C1Vi (n) and Q2(n) C2Vo(n) + = + At cycle n 1/2, i.e., t (n 1/2)Ts,

+ = + = − = − Q1(n 1/2) 0 Q2(n 1/2) Q2(n) Q1(n) C2Vo(n) C1Vi (n)

+ = + At cycle n 1, i.e., t (n 1)Ts,

+ = + + = + = + = − Q1(n 1) C1Vi (n 1) Q2(n 1) C2Vo(n 1) Q2(n 1/2) C2Vo(n) C1Vi (n)

Thus, the time-domain diﬀerence equation is

+ = − C2Vo(n 1) C2Vo(n) C1Vi (n)

In the z-domain

− V (z) C 1 C z 1 zC V (z) = C V (z) − C V (z) ⇒ o = − 1 × = − 1 × 2 o 2 o 1 i − − −1 Vi (z) C2 z 1 C2 1 z

SC Filters 23-5 Analog ICs; Jieh-Tsorng Wu SC Diﬀerential Integrators

C2 C2

Q R 2 1 1 2 Vi1 Vo VVi1 o

Vi2 Q C R1 1 1 C2 1 2 Vi2

→ = − 1 − RC Integrator Vo(s) (Vi1 Vi2) sR1C2 − C z 1 SC Integrator → V (z) = − 1 × × [V (z) − V (z)] o −1 i1 i2 C2 1 − z

SC Filters 23-6 Analog ICs; Jieh-Tsorng Wu Eﬀects of Parasitic Capacitances

Cp3 Cp4 C2

1 2 Va Vi1 Vo A Cp1 C1 Cp2 1 2 Vi2

−1 C Cp1 z V (z) = − 1[V (z) − V (z)] − V (z) × o i1 i2 i1 −1 C2 C2 1 − z

SC Filters 23-7 Analog ICs; Jieh-Tsorng Wu Eﬀects of Parasitic Capacitances

• = ∞ Among the parasitic capacitors, only Cp1 contribute charge to C2 if A .

• = − · Consider a ﬁnite value of A, then Vo A Va, and

C [V (n) − V (n)] + C [V (n) − V (n)] + C V + C V (n) 1 i1 i2 2 a o p1 i1 p3 a = C + C + C V (n + 1) + C [V (n + 1) − V (n + 1)] 1 p1 p3 a 2 a o C − −C1 [V (z) − V (z)] − p1 V (z) × z 1 C2 i1 i2 C2 i1 ⇒ V (z) = o C C C 1 + 1 1 + C1 + p1 + p3 − z−1 1 + 1 1 + p3 A C2 C2 C2 A C2

• Must keep Cp1 C1 and Cp1,p3 C2. – Connect the top plates of the capacitors to the opamp’s input. – Let the bottom plates of the capacitors always be driven.

SC Filters 23-8 Analog ICs; Jieh-Tsorng Wu Parasitics-Insensitive SC Integrators

2 1 Vo φ1

φ2 C1 2 1 n-1n n+1 Vi2 Vi1 n-1/2 n+1/2 − C1 −V + z 1V C2 i1 i2 V (z) = o C C C 1 + 1 1 + C1 + p1 + p3 − z−1 1 + 1 1 + p3 A C2 C2 C2 A C2

• Insensitive to parasitics if A →∞.

• The two inputs have diﬀerent delays.

SC Filters 23-9 Analog ICs; Jieh-Tsorng Wu Fully Diﬀerential SC Integrators

2 1 Vi2 Vi1

C1 C 2 = − 2 1 Vi1 Vi1+ Vi1− V o V = V − V VCMI 21 i2 i2+ i2− Vo = − Vo Vo+ Vo− C2 C1 2 1 Vi2 Vi1 − C 1 z 1 V (z) = 1 × − · V + · V o −1 i1 −1 i2 C2 1 − z 1 − z

• ﬀ VCMI and VCMO can be di erent.

SC Filters 23-10 Analog ICs; Jieh-Tsorng Wu MOST Analog Switches

C2 MOST Switch Model

Ron C a 111 Vi Vo Vi Vo Vi Vo C C a 22

C = 1 2 Ron 1 a µCox(W/L)Vov 1 VDD C1 VDD Vi Vo Ts a VSS 22 VSS

1 mT VCMI VCMI VCMI s

For good settling, want = 5C mTs > 5RonC µCox(W/L)Vov

SC Filters 23-11 Analog ICs; Jieh-Tsorng Wu MOST Analog Switches

• When turning oﬀ the switch, the switching error is

αQ αW LC V ∆V = CH = ox ov C C

The maximum clock rate is m µ∆V f < · s α 5L2 • Realize switches connected to VSS or near VSS with nMOSTs.

• Realize switches connected to VDD or near VDD with pMOSTs.

• Tur n oﬀ the switches near the virtual ground node of the opamps ﬁrst.

• The thermal noise is proportional to kT/C.

• There are also noises from the power supplies.

SC Filters 23-12 Analog ICs; Jieh-Tsorng Wu Eﬀects of Opamp’s Finite DC Gain

C 2 = ∞ If Ao , then

C V (n) = −kV (n) + V (n − 1) 1 1 1 o i o Vi Vo k H(z) = − 1 − z−1 22 Ao C k = 1 C2

= If Ao 1/µ is ﬁnite, then

kα V (n) = −kαV (n) + βV (n − 1) H(z) = − o i o 1 − βz−1 1 α = ≈ 1 − (1 + k)µ = 1 + ∆α ∆α = −(1 + k)µ 1 1 + (1 + k)µ 1 + µ β = ≈ 1 − kµ = 1 + ∆β ∆β = −kµ 1 1 + (1 + k)µ

SC Filters 23-13 Analog ICs; Jieh-Tsorng Wu Eﬀects of Opamp’s Finite DC Gain

The transfer function H(z) in s-domain is

jωT k jθ(ω) H(e s) ≈− × [1 + m(ω)]e −1 1 − z = jωT z e s ∆β 1C 1 m(ω) ≈ ∆α − ≈− 1 + 1 · 2 2C2 Ao ∆β 1 1 C 1 1 C 1 1 θ(ω) ≈− · ≈ · 1 · · ≈ 1 · · 2 2 tan(ωTs/2) C2 Ao tan(ωTs/2) C2 Ao ωTs

• jωi Ts = At the unit-gain frequency ωi , where H(e ) 1, we have

− ≈ ≈ m(ωi ) θ(ωi ) 1/A o if ωi Ts/2 1

• In most applications, the magnitude error m(ω) has negligible eﬀect, but the phase error θ(ω) can be detrimental in narrowband (high-Q) ﬁlters.

SC Filters 23-14 Analog ICs; Jieh-Tsorng Wu Eﬀects of Opamp’s DC Oﬀset

C 1 1 1 Vi Vo

22 VOS

C 1 C 1 V (z) = − 1 · V (z) + 1 · V + V o −1 i −1 OS OS C2 1 − z C2 1 − z

• The VOS to Vo transfer function is also an integration.

• When the entire ﬁlter is considered, the VOS may cause ﬁnite dc level shift in this and other integrators.

SC Filters 23-15 Analog ICs; Jieh-Tsorng Wu An Oﬀset Auto-Zeroing Scheme

3 C C 1 1 1 3 3 Vi Vo

232 VOS

φ1

φ2

φ3

• ﬀ During the φ3 auto-zeroing mode, opamp’s o set voltage is stored in C3.

SC Filters 23-16 Analog ICs; Jieh-Tsorng Wu Eﬀects of Opamp’s Finite Settling Time

T 1 φ C2 1 φ2 C 1 1 1 Vi Vo A 22 Vo t settle t slew

• = = = Let tslew 0, A(s) ωu/s, T1 Ts/2, ωi is the unit-gain frequency of the integrator, = and ωi Ts 1. At ω ωi , the magnitude error and phase error of the integrator are

− ≈ ≈− ωuTs/2 m(ωi ) θ(ωi ) ωi Tse

• ≥ · Want ωu 5 ωs. However, to avoid unnecessary noise aliasing, ωu should not be too much larger than necessary.

SC Filters 23-17 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS

12 C C’ φ1 1 1 2 Vi Vo φ2 A 22 o t1 t2 t3 VOS

= = φ1 1 C2 φ2 1 C2

C1 C’2 C1 C’2 Vo Vo

VOS VOS

SC Filters 23-18 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS

ﬀ Consider the VOS e ect only. Let

= = ∞ = − − Vi 0 Ao and ∆VOS(t) VOS(t) VOS(t Ts/2)

= At t t2 C = + + + 2 Vo(t2) Vo(t1) VOS(t2) 1 ∆VOS(t2) C2 = At t t3 C V (t ) = V (t ) − V (t ) + 1 + 1 ∆V (t ) o 3 o 2 OS 2 C OS 3 2 C = + + + 1 Vo(t1) ∆VOS(t2) 1 ∆VOS(t3) C2

SC Filters 23-19 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS

= = φ1 1 C2 φ2 1 C2

C C’ C C’ 1 221 Va Vi Vo Vo Va Ao Ao

ﬀ = Consider the ﬁnite dc gain e ect only. Let VOS 0, and

C C = 1 = 1 = 2 = + = + Ao k j 1 (1 k)µ2 (1 j)µ µ C2 C2 = At t t2 ≈ − − = − + + 2 Vo(t2) Vo(t1) j(1 2)Vo(t1) 1 jµ (1 j)µ Vo(t1)

• − Note that Va is reset from µVo(t1)to0.

SC Filters 23-20 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS

= = At t t3, assuming Vi 0, then

V (t ) = V (t ) + [µV (t ) + V ] + kV = −A [V − µV (t )] o 3 o 2 o 2 a a o a o 2 1 ⇒ V (t ) = 1 + V (t ) ≈ 1 + µ − (1 + k)µ2 V (t ) o 3 + + o 2 o 2 1 k Ao

Including Vi ,wehave ≈− − + + − + 2 Vo(t3) k(1 1)Vi (t3) 1 µ (1 k)µ Vo(t2) ≈− − + + − − 2 k(1 1)Vi (t3) 1 (1 j)µ kµ Vo(t1)

SC Filters 23-21 Analog ICs; Jieh-Tsorng Wu An SC Integrator with CDS

= = ﬀ If j C2/C2 1, the output di erence equation becomes

V (n) = −k(1 + ∆α)V (n) + (1 + ∆β)V (n − 1) o i o C 1 ∆α = −(1 + k)µ = − 1 + 1 · C2 Ao C 1 ∆β = −kµ2 = − 1 · C 2 2 Ao

• Reference: W. Ki, el. al., “Oﬀset-Compensated Switched-Capacitor Integrators,” ISCAS, 1990, pp. 2829Ð2832.

SC Filters 23-22 Analog ICs; Jieh-Tsorng Wu Discrete-Time Signal Processing

x (t) x(n) y(n) y (t) y (t) c d c

Analog Discrete Analog Sampling Time DAC Prefilter Postfilter Processing

Ts x (t) c Xc(jΩ) A

t Ω 0 Ts 3Ts 0 Ω Ω 2Ω 2Ts b s s jω x(n) X e A Ts

n ω 0 123 0 2π 4π

SC Filters 23-23 Analog ICs; Jieh-Tsorng Wu Continuous-Time Signals

The Laplace transform and the continuous-time Fourier transform (CTFT) are

∞ ∞ = −st = −jΩt Xc(s) xc(t)e dt Xc(jΩ) xc(t)e dt −∞ −∞

If the region of convergence of Xc(s) includes the imaginary axis, then

= | Xc(jΩ) Xc(s) s=jΩ

Sampling Theorem: To avoid aliasing, want

= = 2π Ωs > 2Ωb Ωs 2πfs Ts

• Ωb is the bandwidth of xc(t), Ωs is the sampling frequency, and 2Ωb is called the Nyquist rate.

SC Filters 23-24 Analog ICs; Jieh-Tsorng Wu Discrete-Time Signals

In discrete-time domain, the z transform is

∞ X (z) = x(n)z−n n=−∞

The discrete-time Fourier transform (DTFT) is

∞ X ejω = x(n)e−jωn n=−∞

If the region of convergence of X (z) includes the unit circle, then jω = | X e X (z) z=ejω

SC Filters 23-25 Analog ICs; Jieh-Tsorng Wu s-to-z Transformation

Want to approximate Hc(s) with H(z).

1 sTs z = e s = · ln z ⇒ H(z) = H (s)| = ≈ H (s)| = c s (1/Ts)lnz c s T (z) Ts

Transformation error of an Integrator can be written as

1 1 1 jφ(Ω) H (s) = = ⇒ H(z)| jΩT = · [1 − (Ω)] · e c s jΩ e s jΩ

BE 1/2 BL s to z -1 Vi Vo Vi z FE

SC Filters 23-26 Analog ICs; Jieh-Tsorng Wu s-to-z Transformation

Backward Euler (BE) Transformation

1 1 1 ΩT /2 ΩT s = · 1 − z−1 ⇒ = T · = 1 − s φ =+ s s s − −1 2 Ts 1 z sin(ΩTs/2)

Forward Euler (FE) Transformation

− − 1 1 − z 1 1 z 1 ΩT /2 ΩT s = · ⇒ = T · = 1 − s φ = − s −1 s s − −1 2 Ts z 1 z sin(ΩTs/2)

Lossless Discrete (LD) Transformation

− −1 −1/2 ΩT /2 = 1 · 1 z ⇒ 1 = · z = − s = s Ts 1 φ 0 −1/2 s − −1 Ts z 1 z sin(ΩTs/2)

SC Filters 23-27 Analog ICs; Jieh-Tsorng Wu Bilinear s-to-z Transformation

The transformation is

− − 2 1 − z 1 1 T 1 + z 1 ΩT /2 s = · ⇒ = s · = 1 − s φ = 0 + −1 s 2 − −1 Ts 1 z 1 z tan(ΩTs/2) let z = ejω, then

2 ejω − 1 2 ω 2 ω s = · = · j tan = jΩ Ω = tan jω Ts e + 1 Ts 2 Ts 2

• The unit circle in the z-plane is mapped to the jΩ axis in the s-plane.

SC Filters 23-28 Analog ICs; Jieh-Tsorng Wu Hc(s) to H(z) Design Procedures for Bilinear Transformation

|H(z = ejΩTs)|

0 Ω Ωp Ωs/2 Ωs Ω Ωz |H(s = jΩ )| c

Ω 0 Ω p Ωz Ωc

SC Filters 23-29 Analog ICs; Jieh-Tsorng Wu Hc(s) to H(z) Design Procedures for Bilinear Transformation

• Prewarp the ﬁlter speciﬁcations from Ω to Ω .

Ω T Ω T Ω T = 2 p s = 2 c s = 2 z s Ωp tan Ωc tan Ωz tan Ts 2 Ts 2 Ts 2

• Find Hc(s ).

• The H(z) is obtained by

− 2 1 − z 1 H(z) = H s = · c −1 Ts 1 + z

SC Filters 23-30 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Filter Systems

Xi(t) Xo(t)

Anti-Aliasing Reconstruction Filter Filter Sampled Data Filter (Limits BW) (Smooths output)

• Discrete-time (or sampled-data) analog ﬁlters.

• Filters consist of analog switches, capacitors and opamps.

• Filter response is determined by ratios of capacitance.

SC Filters 23-31 Analog ICs; Jieh-Tsorng Wu Design Constraints

• Switched-C “resistor” cannot be the only feedback around an opamp. Since the path is not continuous, it won’t stabilize the opamp.

• No ﬂoating node. Otherwise charge can accumulate.

• Capacitor bottom plate must always be driven from a low impedance (voltage sources or ground).

• Connect non-inverting opamp input to a dc bias. Otherwise response is sensitive to parasitic capacitances.

SC Filters 23-32 Analog ICs; Jieh-Tsorng Wu Periodic Time-Variance in Biphase SC Filters

n n+1/2 n+1 C φ1 C 1 1 2 1 0 φ2 Vi1 Vo 2 1 1 1 1 Vi1 Vo C 1 2 1 2 1 1 2 Vi2 Vi2 Vo 22 0 Vo

The circuit is periodic time-variant if 1 V 1[n · T ] = V 2 n + · T o s o 2 s

SC Filters 23-33 Analog ICs; Jieh-Tsorng Wu Periodic Time-Invariance in Biphase SC Filters

n n+1/2 n+1 C φ1 C 2 1 1 1 0 φ2 Vi1 Vo 1 2 1 1 1 Vi1 Vo C 122 1 1 1 2 Vi2 Vi2 Vo 22 0 Vo

The circuit is periodic time-invariant if 1 V 1[n · T ] = V 2 n + · T o s o 2 s

• SC ﬁlters are more robust when designed to be time-invariant.

SC Filters 23-34 Analog ICs; Jieh-Tsorng Wu Active Switched-Capacitor Integrators

C 1 Vi1 C1 C1 1 1 1 1 1 Vi1 Vo 2 2 1 1 1 1 1 2 Vi2 C2 z Vo 2 C 1 Vo 1-z C2 1 2 1 Vi2 1 1 Vi3 C3 (1-z ) 12

φ1 C 1 3 1 1 φ2 Vi3 n n+1/2 n+1

1 = 1 · − 1 + −1 1 − − −1 1 Vo C1V C2z V C3 1 z V C 1 − z−1 i1 i2 i3 2 = 1 · −1/2 Vo Vo z

SC Filters 23-35 Analog ICs; Jieh-Tsorng Wu Active Switched-Capacitor Integrators

• 1 1 − Vi1 to Vo is a Backward Euler ( BE) integrator.

• 1 2 − Vi1 to Vo is a Lossless Discrete ( LD) integrator.

• 1 1 + Vi2 to Vo is a Forward Euler ( FE) integrator.

• 2 1 + Vi2 to Vo is a Lossless Discrete ( LD) integrator.

SC Filters 23-36 Analog ICs; Jieh-Tsorng Wu SC First-Order Filters

1 1 Vi CA1 CB1

+ α1s α0 1 V V i sτ o 1 1 11 1 Vi CA2()1-z Vo C 1 1-z

C 1 B1 1 C 1 A1 1 1 22 Vi 22 1 1 C Vo

2 2 CA2 V 1 11 o Vi

C C C −1 1 −1 A1 ± A2 ∓ A2 z V (s) α s + α V C ± C (1 − z ) C C C o = − 1 0 o = − A1 A2 = − + 1 + − −1 C Vi (s) sτ 1 V CB1 C(1 z ) B1 + − −1 i C 1 z

SC Filters 23-37 Analog ICs; Jieh-Tsorng Wu Switch Sharing

C 1 B1 1 C 1 A1 1 1 22 Vi 22 1 1 C Vo

2 2 CA2 V 1 11 o Vi

C B1 1 C 1 A1 1 2 Vi 1 2 1 C Vo

1 2 2 CA2 V 1 1 o Vi 2

SC Filters 23-38 Analog ICs; Jieh-Tsorng Wu Bilinear SC First-Order Filters

C B1 1

2 1 1 C Vo C 1 A1 1 2 1 2 − Vi Vo V 1 C + C z 1 o = − A1 A1 2 2 1 C + C(1 − z−1) Vi B1 1 − Vi CA1 + CA1 z 1 = − C C 1 CB1 + 1 − z−1 Vi CA1 CB1 C

1 1 11 1 Vi CA1 z Vo C 1 1-z

SC Filters 23-39 Analog ICs; Jieh-Tsorng Wu SC Second-Order Filters

1/Q

K 1 1 V V i sτ sτ l Vh Vb 1

C C B2 2 B1 1 C 1 A1 1 2 Vi 2 C1 C2

CA2 CK2 2 1 2 1 1 Vo 1 221

C C −1 C C −2 1 A1 K 2 z − A2 K 2 z V C C C C o = 1 2 1 2 1 CB1 CB2 CK 2 CB1 −1 −2 Vi + 1 + · − − 2 z + z C1 C1 C2 C1

SC Filters 23-40 Analog ICs; Jieh-Tsorng Wu SC Second-Order Filters

C B2 1

C 2 B1 1 C 1 A1 1 2 Vi 2 C1 C2

CA2 CK2 2 1 2 1 1 Vo 1 221

CB2

1 Vi CA1 CB1

1 1 1 1 11 1 CA2 z CK2 z Vo C1 C1 1 1-z 2 1-z

SC Filters 23-41 Analog ICs; Jieh-Tsorng Wu A Low-Q SC Biquad

K4 1 1

22 K6 1 1

C1 = 1 C2 = 1 K1 K5 1 1 1 2 1 1 Vi Vo 22 12

K2 1 1

V (z) (K + K )z2 + (K K − K − 2K )z + K a z2 + a z1 + a H(z) = o = − 2 3 1 5 2 3 3 = − 2 1 0 + 2 + − − + 2 + + Vi (z) (1 K6)z (K4K5 K6 2)z 1 b2z b1z 1

SC Filters 23-42 Analog ICs; Jieh-Tsorng Wu A Low-Q SC Biquad

We have

= = − = + + = − = + + K3 a0 K2 a2 a0 K1K5 a0 a1 a2 K6 b2 1 K4K5 b2 b1 1

• Additional constraint can be made by = = = + + K5 1orK4 K5 b2 b1 1

= jΩTs = + Let z e cos(ΩTs) j sin(ΩTs), and ΩT ΩT ΩT ΩT z1/2 = cos s + j sin s z−1/2 = cos s − j sin s 2 2 2 2

Then + + + 2 K1K5 jK2 sin(ΩTs) (4K3 2K2) sin (ΩTs/2) H ejΩTs = − + + + 2 K4K5 jK6 sin(ΩTs) (4 2K6) sin (ΩTs/2)

SC Filters 23-43 Analog ICs; Jieh-Tsorng Wu A Low-Q SC Biquad

Assume ΩTs 1, we have

+ + + 2 2 + + K1K5 jK2(ΩTs) (K3 K2/2)(ΩTs) α2s α1s α0 H ejΩTs ≈− = − + + + 2 2 ωp 2 K4K5 jK6(ΩTs) (1 K6/2)(ΩTs) s + · s + ω Qp p

= Let K4 K5, then ω T = ≈ ≈ p s K4 K5 ωpTs K6 Qp

• Usually, ωpTs 1.

• The largest capacitors are the integrating capacitors, C1 and C2.

• If Qp < 1, the smallest capacitors are K4 and K5.

• If Qp > 1, the smallest capacitors is K6.

SC Filters 23-44 Analog ICs; Jieh-Tsorng Wu A High-Q SC Biquad

K1 K4 1 1 1 1 1 Vi 22 22

C=1 = 1 C2 1 K2 K5 2 1 1 Vo 12

V (z) K z2 + (K K + K K − 2K )z + (K − K K ) a z2 + a z1 + a H(z) = o = − 3 1 5 2 5 3 3 2 5 = − 2 1 0 2 + + − + − 2 + + Vi (z) z (K4K5 K5K6 2)z (1 K5K6) z b1z b0

SC Filters 23-45 Analog ICs; Jieh-Tsorng Wu A High-Q SC Biquad

We have

= + + = − = = + + = − K1K5 a0 a1 a2 K2K5 a2 a0 K3 a2 K4K5 1 b1 b0 K5K6 1 b0

• Additional constraint can be made by = = + + K4 K5 1 b1 b0

• Less capacitance spread.

In general,

• For the SC biquad, it is important that the two-integrator loop have a single delay around the loop. A delay-free loop may have an excessive settling time behavior, while two delays around the loop cause diﬃculties in designing high-Q circuit.

SC Filters 23-46 Analog ICs; Jieh-Tsorng Wu Time-Staggered SC Stages Cascaded SC Stages

1 1

2 2

1 1 2 1 1 1 2 1

2 2 1 2 2 2 1 2

1 1

Staggered Cascaded Stages

1 2

2 1

1 1 2 1 2 212

2 2 1 2 11 21

1 2

SC Filters 23-47 Analog ICs; Jieh-Tsorng Wu Capacitor Scaling Q3 21 1 2 C V1 A

C1 C3 Qi Vo Q4 21 1 2 V2

C2 C4

For each switching cycle = + Qi C1V1 C2V2 Q = − i ∆Vo CA = = Q3 C3Vo Q4 C4Vo

SC Filters 23-48 Analog ICs; Jieh-Tsorng Wu Output Capacitor Scaling

= = = If CA kCA, C3 kC3, C4 kC4, C1 and C2 unchanged, then

= + = Qi C1V1 C2V2 Qi

Q Q ∆V ∆V = − i = − i = o o kC k CA A V Q = C V = kC o = Q Q = Q 3 3 o 3 k 3 4 4

• If the values of all capacitors (including feedback capacitors) connected or switched to the output terminal of an opamp in an SCF are multiplied by the same constant k, then the output voltage of this opamp will be divided by k; all other opamp output voltages remain unchanged. This follows since the described changes leave all charges ﬂowing to and from the aﬀected opamp unchanged.

• The output capacitor scaling technique can be used to achieve optimum scaling for maximum dynamic range.

SC Filters 23-49 Analog ICs; Jieh-Tsorng Wu Input Capacitor Scaling

= = = If CA kCA, C1 kC1, C2 kC2, C3 and C4 unchanged, then

= + = + = Qi C1V1 C2V2 kC1V1 kC2V2 kQi

Q kQ ∆V = − i = − i = ∆V o kC o CA A = = = = Q3 C3Vo C3Vo Q3 Q4 Q4

• If the values of all capacitors (including feedback capacitors) connected or switched to the inverting input terminal of an opamp are multiplied by the same constant, then all voltages in the SCF remain unchanged. This is true since all voltages are aﬀected only by the ratios of these capacitances.

• The input capacitor scaling technique can be used to achieve optimum scaling for minimum capacitance.

SC Filters 23-50 Analog ICs; Jieh-Tsorng Wu An All-Pole Low-Pass Ladder Filter I I I 0 2 4 V V V V 1 3 5 out

R L2 L4 V S C1 C3 C5 I R in 6 L

V V V V 0 2 4 6

1/RS -1/(sC1 ) 1/(sL2) -1/(sC 3) 1/(sL4) -1/(sC 5) 1/RL

V V in out V V V 1 3 5

V 1/R V V in S 2 4

R R S L 1+sR C 1+sR C S 1 L 5

V V V 1 5 out

SC Filters 23-51 Analog ICs; Jieh-Tsorng Wu An All-Pole Low-Pass SC Ladder Filter

R 1 V 11V 1 S 2 4 V in

C 3 R C L L RC S 1 2 4 L5

V out V V V 1 111 3 1 5 1 2 V in V V C 2 4 S 2 C 2 C 2 C 2 C 2

1 1 1 1 1 C 3 CCC C C C S 1 24L 5

1 2 12 1 V out CCC C 2 1 21 2 V V V 1 3 5

SC Filters 23-52 Analog ICs; Jieh-Tsorng Wu SC Ladder Filter Using Signal-Flow Graph

Inverting BE Integrator Noninverting FE Integrator C = 1 C = 1

K K 11111 1 1 2 1 1 Vi Vo Vi Vo 22 2 1

− 1 z 1 H (z) = −K · H (z) =+K · BE 1 − z−1 FE 1 − z−1

• HBE(z) is a Backward-Euler (BE) integrator. HFE(z) is a Forward-Euler (FE) integrator.

• The phase errors of the integrators are cancelled in the ladder topology, while the magnitude errors can cause deviations in the frequency response when ωTs 1is no longer true.

• The SC ladder ﬁlters are inherently time-staggering.

SC Filters 23-53 Analog ICs; Jieh-Tsorng Wu SC Ladder Filters Design Methodology

It is possible to realize the SC ladder ﬁlters with exact frequency response, using only the BE and FE integrators. The design procedures involves bilinear transformation prewarping and frequency-dependent impedance scaling.

− s T z1/2 − z 1/2 sT λ = s = = tanh s 2 z1/2 + z−1/2 2

1 sT 1 sT γ = z1/2 − z−1/2 = sinh s µ = z1/2 + z−1/2 = cosh s 2 2 2 2 γ ⇒ λ = µ2 − γ2 = 1 z1/2 = µ + γ µ

• λ ↔ z is the bilinear (BL) transformation.

• γ ↔ z is the lossless discrete (LD) transformation.

• The design goal is to implement H z = esTs with H(γ). H(γ) can then be realized with SC integrators.

SC Filters 23-54 Analog ICs; Jieh-Tsorng Wu SC Ladder Filters Design Procedures

1. Prewarp the ﬁlter speciﬁcations from ω to ω with bilinear transformation.

2 ωT ω = tan s Ts 2

= 2. Find H(s ). Renormalize H(s ) into H(λ) by setting s Ts/2 λ.

3. Realized H(λ) as an LC ladder ﬁlter in λ domain.

4. Scale the impedance level,

Y (γ) = µY (λ) Z(γ) = Z(λ)/µ

to obtain the γ-domain LC ladder circuit.

5. Implement the γ-domain circuit with SC circuits.

SC Filters 23-55 Analog ICs; Jieh-Tsorng Wu Nyquist-Rate Digital-to-Analog Converters

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering A/D and D/A Interfaces

x(t) x(n) y(n) y(t) A/D Digital D/A Interface Processor Interface

Analog World

Analog-to-Digital Interface

x(t) x(n) Low-Pass Sampling Quantizer Decoder Filter Circuit

fs Digital-to-Analog Interface

y(n) y(t) D/A Inverse-Sinc / Low-Pass Deglitcher Converter Filter

fs fs

DACs 24-2 Analog ICs; Jieh-Tsorng Wu Continuous-to-Discrete Conversion

x (t) x(n) y(n) y (t) y (t) c d c

Analog Discrete Analog Sampling Time DAC Prefilter Postfilter Processing

Ts x (t) c Xc(jΩ) A

t Ω 0 Ts 3Ts 0 Ω Ω 2Ω 2Ts b s s jω x(n) X e A Ts

n ω 0 123 0 2π 4π

DACs 24-3 Analog ICs; Jieh-Tsorng Wu Discrete-to-Continuous Conversion

yd (t) Yd (jΩ) A

t Ω T 3T s 2T s 0 s Ωs 2Ωs

yc (t) Yc(jΩ) A

t Ω 0 T 3T s 2T s 0 s Ωs 2Ωs

1 sinc π Ω Ωs Ω 0 Ωs 2Ωs

DACs 24-4 Analog ICs; Jieh-Tsorng Wu Discrete-to-Continuous Conversion

The digital-to-analog converter (DAC) usually performs the discrete-to-continuous sample-and-hold translation, i.e.,

∞ 1if0

The continuous-time Fourier transform (CTFT) of yd (t) can be expressed as = | × = jω × Yd (jΩ) Yd (z) = jΩTs Hda(jΩ) Yd e = Hda(jΩ) z e ω ΩTs

The discrete-to-continuous sample-and-hold transfer function is

− sTs 1 − e − Ω = = jπΩ/Ωs · · Hda(s) Hda(jΩ) e Ts sinc π s Ωs = = 2π = sin x Ωs 2πfs sinc(x) Ts x

DACs 24-5 Analog ICs; Jieh-Tsorng Wu Imperfections in Discrete-to-Continuous Conversion

The D/A conversion of y(n) can be expressed as:

∞ = · − + yd (t) yˆ(n) C[t nTs ] n=−∞

• The y(n) → yˆ(n) conversion may contains gain error, oﬀset, and nonlinearity.

• C(t) has transient behavior. Its pulse width can be larger than Ts.

• C(t) may contain y(n) dependency. – A return-to-zero C(t) can reduce the y(n) dependency.

• The timing jitter can be random or deterministic.

DACs 24-6 Analog ICs; Jieh-Tsorng Wu D/A Transfer Characteristic

(Digital Input) Ao A bN-1 b1 b0 FS

A = FS AFS Full-Scale Output D/A 2 A ∆ = LSB = Step Size = FS 2N 0 D A in o 000 100 111 (Analog Output)

= × Ao ∆ Din = × N−1 + ···+ 1 + 0 ∆ bN−12 b12 b02 = × −1 + ···+ −(N−1) + −N AFS bN−12 b12 b02

• In some applications, relationship between Din and Ao can be nonlinear.

• ﬀ Din may use other coding scheme such as o set binary or 2’s complement.

DACs 24-7 Analog ICs; Jieh-Tsorng Wu D/A Transfer Characteristic

Nonmonotonic Offset Gain Error Ao Ao Ao

Ideal Ideal

Din AOS Din Din 0 0 0

AOS Oﬀset Error = A = A | = ∆ OS o Din 0 − − Ao,max AOS Ao,max AOS Gain Error = = · N − · − −N ∆ (2 1) AFS (1 2 )

DACs 24-8 Analog ICs; Jieh-Tsorng Wu D/A Nonlinearity

Ao Ao Ao

INL

DNL Large INL Low DNL DNL=-1LSB

0 Din 0 Din 0 Din

• Measure of deviation from straight line with oﬀset and gain error corrected.

• Diﬀerential nonlinearity (DNL): Maximum deviation of the analog output step from the ideal value of 1 LSB (= ∆).

• Integral nonlinearity (INL): Maximum deviation of the analog output from the ideal value.

DACs 24-9 Analog ICs; Jieh-Tsorng Wu D/A Performance Metrics — Static Characteristics

• Resolution: number of bits (N), analog 1 LSB step (∆).

• Oﬀset error.

• Gain error.

• Integral nonlinearity (INL).

• Diﬀerential nonlinearity (DNL).

• Monotonicity. – Monotonicity can be assumed if the DNL > −1 LSB.

• Stability. – Variation with time, temperature, and supply voltage.

DACs 24-10 Analog ICs; Jieh-Tsorng Wu D/A Performance Metrics — Dynamic Characteristics

• Sampling rate.

• Settling time. – Settling time is the time taken by the D/A output to settle within some speciﬁed ±1 error band (typically 2 LSB). – The settling time is primarily dominated by the settling of the MSB contribution.

• Glitch impulse area (glitch energy). – Glitches is the output transient spikes during the conversion process. – Glitches are caused by the unequal delays in switching various signal sources within the converter.

• Dynamic range: SNRmax, SFDR, SINAD.

DACs 24-11 Analog ICs; Jieh-Tsorng Wu Dynamic Range

y(t) Power Spectrum y(k) dBm/Hz Quantizer N-Bit x(k) y(t) N-Bit DAC SFDR fs

e(k)

fi 2fi 3fi f x(k) y(k) SINAD (dB) Ideal Probability Density Function (pdf)

Measured e dB /2 /2 0 Input Level Relative to Full Scale

DACs 24-12 Analog ICs; Jieh-Tsorng Wu Dynamic Range e(k)isaquantization noise due to the quantization process. 1 e(k) ≡ y(k) − x(k) Noise Power = P = e2pdf(e)de = ∆2 n 12

Let the input x(k) be a sinusoidal waveform

1 x(k) = A sin(2πf · kT ) Signal Power = P = A2 i s s 2 The signal-to-noise ratio of y(k)is

P A2 SNR ≡ s = 6 · 2 Pn ∆ = When the input’s amplitude A AFS/2, the SNR reaches its maximum value. 1 3 A = 2N∆P= · 22N∆2 SNR = 22N × = N × 6.02 dB + 1.76 dB FS s 8 max 2

DACs 24-13 Analog ICs; Jieh-Tsorng Wu Dynamic Range

• The ratio between fs and fi should be irrational.

• In the discrete-time domain, noise power of e(k) is assumed to be uniformly − + 2 distributed between Ωs/2 and Ωs/2. The power density is ∆ /(12Ωs).

• The spurious free dynamic range (SFDR) is the ratio of the fundamental signal = component to the largest distortion component when A AFS/2.

• The signal-to-noise plus distortion ratio (SINAD) is the ratio of power of the = fundamental signal to the total power of noise and distortion when A AFS/2.

• The total harmonic distortion (THD) is the ratio of the total power of the 2nd and higher harmonic components to the power of the fundamental signal.

• In ﬁnding the total noise power, the noise bandwidth need to be speciﬁed.

DACs 24-14 Analog ICs; Jieh-Tsorng Wu Resistor-String DACs with Digital Decoding

Din Vref N R • Inherently monotonic.

• DNL depend on local matching of neighboring R’s. R • INL depends on global matching of the R-string.

• No resistive load at . N Vo

• The worst-case time constant occurs a the 1 of 2 Decoder midpoint of the R-string. R • Large capacitive loading at Vo.

DACs 24-15 Analog ICs; Jieh-Tsorng Wu Folded R-String DACs with Digital Decoding

Vref Decoder M 1 of 2

Vo (MSBs) N-M 1 of 2 Decoder Din N-M N

DACs 24-16 Analog ICs; Jieh-Tsorng Wu R-String DACs with Binary-Tree Decoding

V ref bb bb bb 0 0 11 22 R

R • Require no digital decoder. R • Speed is limited by the delay through R Vo the resistor string as well as the delay through the switch network. R

DACs 24-17 Analog ICs; Jieh-Tsorng Wu Intermeshed Resistor-String DACs (One-Level Multiplexing)

Vref

DACs 24-18 Analog ICs; Jieh-Tsorng Wu Intermeshed Resistor-String DACs (Two-Level Multiplexing)

Vref

DACs 24-19 Analog ICs; Jieh-Tsorng Wu Binary-Weighted Current-Steering DACs

VB VB VB

N-1 N-2 0 2 I 22I I

bbN-1 N-2 b 0 = · · N−1 + · N−2 + ···+ · 1 + · 0 Io I bN−1 2 bN−2 2 b1 2 b0 2

DACs 24-20 Analog ICs; Jieh-Tsorng Wu Binary-Weighted Current-Steering DACs

• Fast.

• Monotonicity is not guaranteed.

• Potentially large glitches due to timing skews.

• Latches are often used to synchronize bN−1, bN−2,....

• Ro of the current sources can cause nonlinearity.

Io Glitch

t Din = 0111 Din = 1000

DACs 24-21 Analog ICs; Jieh-Tsorng Wu Binary-Weighted R-2R Networks

16 I 8 I4 I2 I1 I1 I 2R 2R 2R 2R

16 I R R R 2R

8I 4I 2I I I

VB x8 x4x2 x1 x1

2R 2R 2R 2R 2R RRR

VEE

• No wide-range scaling of resistors.

• BJT emitter-area scaling can be conﬁned to the ﬁrst few MSBs; and the voltage drops

in the emitter resistors should dominate the VBE(on) mismatches of the less signiﬁcant bits.

DACs 24-22 Analog ICs; Jieh-Tsorng Wu Equally-Weighted Current-Steering DACs

VVB VB B

I I I

12 2N-1 N Din Binary- to-Thermometer Decoder

• Inherently monotonic.

• Glitches are reduced. Synchronizing latches may be still required.

DACs 24-23 Analog ICs; Jieh-Tsorng Wu The Matrix Floorplan

N LSBs Din Column Decoder MSBs M Cj Cj Io

Local Ri Decoder Row Decoder

• M − N−M − Rj is a 2 1 thermometer code, and Cj is a 2 1 thermometer code. • = + · One example of the local decoding is S Ri+1 Ri Cj .

• INL may exhibit the gradient of the unit cell’s variations.

• INL can be dithered by jumping selection of unit cells.

DACs 24-24 Analog ICs; Jieh-Tsorng Wu A Current Cell Example

I I Cj CLK o1 o2

V SEL 1 V1 M1 M2 R i Local Va R Decoder i+1 SEL V2 V2 VB1 M3 t

VSS

• The current switch MOSTs, M1 and M2, are in the triode region when fully turned on.

• To minimize voltage ﬂuctuation at Va, the inverters are sized so that the cross-over voltage of the V1 and V2 transient waveforms can turn on both M1 and M2.

• Reference: C-H Lin and K Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” JSSC, 12/1998, pp. 1948–1958.

DACs 24-25 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution DACs

1 Vo N-1 2 1 0 2 C 222C C C C Cp

bN-1 bb201 b

Vref 1

N 2 C

Vo N-1 2 1 0 2 C 2 C 2 C 2 C

bbN-1 b2 10b

Vref

DACs 24-26 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution DACs

= During φ1 1, = Cap Bottom Plate @ GND Vo 0 = During φ2 1, N−1 1 → Cap Bottom Plate @V C b = ref V = V × × b 2i i 0 → Cap Bottom Plate @GND o ref 2NC + C i p i=0

• Binary-weighted or equally-weighted capacitor array.

• Cp is top plate parasitic capacitance, and introduces a gain error.

• ﬀ Opamp can be used to provide voltage gain and mitigate the e ects of Cp.

• DACs at resolutions of 10 bits or above usually requires some kind of trimming or calibration.

DACs 24-27 Analog ICs; Jieh-Tsorng Wu Segmented DAC Architecture

Din N−1 M−1 L−1 N i i+L j D = b 2 = b + 2 + b 2 M AM in i i L j M-Bit DAC i=0 i=0 j=0 M−1 L−1 L AL = × i = × j L-Bit DAC AM ∆M bi+L2 AL ∆L bj 2 i=0 j=0 A = + = L × o N M L∆M 2 ∆L

M−1 L−1 N−1 = + = × i+L + × j = × i Ao AM AL ∆L bi+L2 ∆L bj 2 ∆L bi 2 i=0 j=0 i=0

• ± The M-DAC need to have ∆L/2 accuracy.

• Signal path delay mismatch between the M-DAC and the L-DAC can cause glitch.

• Can have more than two segments.

DACs 24-28 Analog ICs; Jieh-Tsorng Wu A 10-Bit Segmented Current-Steering DAC

B4-B6 B0-B3 B4-B6

Column Decoder Column Decoder

B7-B9 B7-B9 8 x 8 8 x 8 Row Decoder Row Decoder

Column Decoder Column Decoder

B4-B6 B4-B6

DACs 24-29 Analog ICs; Jieh-Tsorng Wu A 10-Bit Segmented Current-Steering DAC

• Segmented 6-2-2 architecture with common-centroid layout.

• Each current cell in the matrix contains 4 LSB current.

• Reference: J. Bastos, et. al., “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,” JSSC 12/1998, pp. 1959–1969.

DACs 24-30 Analog ICs; Jieh-Tsorng Wu A Segmented Current-Steering DAC

VB VB VB

III VC 4X2X 1X 1X

M L M-DAC Thermometer Decoder L-DAC Binary Decoder N Din

• Greatly reduces area for large N while ensuring monotonicity (at least for MSBs).

• The L-DAC can be a binary-weighted DAC if its glitches can be tolerated.

• Reference: H. Schouwenaar, et al., JSSC 12/88, pp. 1290–1297.

DACs 24-31 Analog ICs; Jieh-Tsorng Wu Dynamically-Matched Current Sources

Out Io Iref Calibration I Switch Array ref

C C C C s s s s M1 S1 C VSS s I I ref B1 Out VSS Out

Iref Operation M3 M4 Iref

VB2 MC1 Cbr Cbr M1 S1 C M1 M2 VB1 s MS1 MS1D IB1 VSS VSS

DACs 24-32 Analog ICs; Jieh-Tsorng Wu Dynamically-Matched Current Sources

• The bias voltage for the current sources is stored in each individual Cs. The voltage on Cs is refreshed periodically by means of calibration.

• A spare current source can be added to facilitate uninterrupted operation.

• Cs can be just the Cgs of M1.

• The switching error of MS1 as well as gm1 must be minimized.

• By adding M2 with a constant current, gm1 can be reduced.

• 16-bit resolution can be achieved using this technique.

• Reference: D. Groeneveld, et al., JSSC 12/89, pp. 1517–1522.

DACs 24-33 Analog ICs; Jieh-Tsorng Wu A Segmented Charge-Redistribution DAC

L-DAC M-DAC VxoV 2 1 0 2 C 2 C 2 C C CC

bj bi L M

Vref Vref

− − N1 V L 1 D = b 2i N = M + LV= ref · b 2j in i x 2L j i=0 j=0   M−1 M−1 L−1 N−1 Vref i 1 Vref  i+L j  Vref i V = · b + 2 + · V = · b + 2 + b 2 = · b 2 o 2M i L 2M x 2M+L i L j 2N i i=0 i=0 j=0 i=0

DACs 24-34 Analog ICs; Jieh-Tsorng Wu A Capacitor-Resistor Hybrid DAC

M 2 C M-DAC Vo M-1 2 100 2 C 2 C 2 C 2 C 2 C M bi

Vref L-DAC

L bj Vref

M−1 L−1 N−1 Vref i 1 Vref j Vref i V = × b + 2 + × × b 2 = × b 2 N = M + L o 2M i L 2M 2L j 2N i i=0 j=0 i=0

DACs 24-35 Analog ICs; Jieh-Tsorng Wu A Resistor-Capacitor Hybrid DAC

L 2 C L-DAC Vo L-1 210 2 C 2 C 2 C 2 C L bj

V2 V1 M-DAC

M bi Vref

M−1 i Vref V = ∆ × b + 2 V = V + ∆ ∆M = N = M + L 1 M i L 2 1 M 2M i=0

DACs 24-36 Analog ICs; Jieh-Tsorng Wu A Resistor-Capacitor Hybrid DAC

= During φ1 1, = Cap Bottom Plate @ GND Vo 0 = During φ2 1, → = 1 Cap Bottom Plate @V2 bi → 0 Cap Bottom Plate @V1 L−1 M−1 L−1 N−1 ∆M j Vref i Vref j Vref i V = V + × b 2 = × b + 2 + × b 2 = × b 2 o 1 2L j 2M i L 2M+L j 2N i j=0 i=0 j=0 i=0

• The capacitor array interpolates the voltages between V1 and V2.

• Reference: J.-W. Yang, et al., JSSC 10/89, pp. 1458–1461.

DACs 24-37 Analog ICs; Jieh-Tsorng Wu Nyquist-Rate Analog-to-Digital Converters

Jieh-Tsorng Wu

November 13, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering A/D and D/A Interfaces

x(t) x(n) y(n) y(t) A/D Digital D/A Interface Processor Interface

Analog World

Analog-to-Digital Interface

x(t) x(n) Low-Pass Sampling Quantizer Decoder Filter Circuit

fs Digital-to-Analog Interface

y(n) y(t) D/A Inverse-Sinc / Low-Pass Deglitcher Converter Filter

fs fs

ADCs 25-2 Analog ICs; Jieh-Tsorng Wu Continuous-to-Discrete Conversion

x (t) x(n) y(n) y (t) y (t) c d c

Analog Discrete Analog Sampling Time DAC Prefilter Postfilter Processing

Ts x (t) c Xc(jΩ) A

t Ω 0 Ts 3Ts 0 Ω Ω 2Ω 2Ts b s s jω x(n) X e A Ts

n ω 0 123 0 2π 4π

ADCs 25-3 Analog ICs; Jieh-Tsorng Wu A/D Quantization Characteristic

Do (Analog Input) 111 Ai 100

Quantizer Ai 000 A / 2 A FS FS b b b N-1 1 0 Quantization Error Q (Digital Output) 1/2 Ai 1/2

− N1 1 A = ∆ × b 2i − ∆ i,tran i 2 i=0 A A = Full-Scale Output ∆ = LSB = Step Size = FS FS 2N

ADCs 25-4 Analog ICs; Jieh-Tsorng Wu Imperfections in A/D Quantization Characteristic

Offset Gain Error Nonlinearity D D D ooIdeal o Ideal Ideal

Ai Ai Ai

• Diﬀerential nonlinearity (DNL): Maximum deviation in step width (width between transitions) from the ideal value of 1 LSB (= ∆).

• Integral nonlinearity (INL): Maximum deviation of the step midpoints from the ideal step midpoints. Or the maximum deviation of the transition points from ideal.

• If DNL = −1 LSB ⇒ missing code.

ADCs 25-5 Analog ICs; Jieh-Tsorng Wu Quantization Noise

x(k) N-Bit x(t) y(k) Probability Density Function (pdf) Quantizer fs

e(k)

e /2 /2 x(k) y(k) e(k)isaquantization noise due to the quantization process. 1 e(k) ≡ y(k) − x(k) Noise Power = P = e2pdf(e)de = ∆2 n 12

ADCs 25-6 Analog ICs; Jieh-Tsorng Wu Quantization Noise

Let the input x(k) be a sinusoidal waveform

1 x(k) = A sin(2πf · kT ) Signal Power = P = A2 i s s 2 The signal-to-noise ratio of y(k)is

P A2 SNR ≡ s = 6 · 2 Pn ∆ = When the input’s amplitude A AFS/2, the SNR reaches its maximum value.

1 3 A = 2N∆P= · 22N∆2 SNR = 22N × = N × 6.02 dB + 1.76 dB FS s 8 max 2 • The ratio between fs and fi should be irrational.

• In the discrete-time domain, noise power of e(k) is assumed to be uniformly − + 2 distributed between Ωs/2 and Ωs/2. The power density is ∆ /(12Ωs).

ADCs 25-7 Analog ICs; Jieh-Tsorng Wu Sampling-Time Uncertainty (Aperture Jitter)

x(t) x(k) t fs

kTs

= + = 1 x(k) x (kTs ∆t) Ts fs

For a full-scale sinusoidal input

1 x(t) = A sin(2πf t) A = 2N∆ 2 FS i FS dx 1 1 1 ∆V ≈ × ∆t < A · πf × ∆t < ∆ ⇒ ∆t < · FS i N dt 2 2 2πfi

ADCs 25-8 Analog ICs; Jieh-Tsorng Wu Sampling-Time Uncertainty (Aperture Jitter)

= 1 Let x(t) 2AFS sin (2πfi t) and ∆t be a random variable, then dx(t) = + ≈ 1 + × x(k) x (kTs ∆t) AFS sin(2πfi kTs) ∆t 2 dt = t kTs 1 ≈ A sin(2πf kT ) + A πf cos(2πf kT ) × ∆t 2 FS i s FS i i s 1 1 x2(k) = A2 + A2 π2f 2 × ∆t2 = P + P 8 FS 2 FS i s n

The signal-to-noise ratio of x(k)is

P = s = 1 = − · SNR 20 log (2πfi ∆trms) dB Pn 2 2 · 2 4π fi ∆t

• = = = If fi 1 MHz, N 14, SNR 86 dB, want ∆trms < 8.0 psec.

• = = = If fi 100 MHz, N 10, SNR 62 dB, want ∆trms < 1.26 psec.

ADCs 25-9 Analog ICs; Jieh-Tsorng Wu DFT Nonlinearity Test of ADCs

x(k) N-Bit y(k) x(t) DFT Quantizer fs SINAD (dB)

y(t) Power Spectrum 10 Bit dBm/Hz 60

9 Bit 55 SFDR

50 8 Bit

fi 2fi 3fi f 45

40 -25 -20-15 -10 -5 0 Input Level Relative to Full Scale (dB)

ADCs 25-10 Analog ICs; Jieh-Tsorng Wu DFT Nonlinearity Test of ADCs

• The ratio between fs and fi should be irrational.

• In the discrete-time domain, noise power of e(k) is assumed to be uniformly − + 2 distributed between Ωs/2 and Ωs/2. The power density is ∆ /(12Ωs).

• The spurious free dynamic range (SFDR) is the ratio of the fundamental signal = component to the largest distortion component when A AFS/2.

• The signal-to-noise plus distortion ratio (SINAD) is the ratio of power of the = fundamental signal to the total power of noise and distortion when A AFS/2.

• In ﬁnding the total noise power, the noise bandwidth need to be speciﬁed.

ADCs 25-11 Analog ICs; Jieh-Tsorng Wu Code Density Test of ADCs

H(i)

x(k) N-Bit y(k) x(t) Histogram Quantizer fs Do x(t) t

W(i)

ADCs 25-12 Analog ICs; Jieh-Tsorng Wu Code Density Test of ADCs

Let Nt be the total number of samples, H(i) the number of counts in the i-th Do, and P (i) the ideal probability for the i-the Do.Wehave

W (i) H(i) = − · 1 = · 1 Ai+1,tran Ai,tran ∆ ∆ Nt P (i)

• For high precision, sinusoidal waveform is usually for the input. The probability density p(V )forA sin(ωt)is 1 p(V ) = π A2 − V 2

• To test a 12-bit ADC, for 99 percent conﬁdence and 0.10 bit precision, 4.2 million samples are needed.

• Reference: Doernberg, JSSC 12/84, pp. 820–827.

ADCs 25-13 Analog ICs; Jieh-Tsorng Wu Serial (Integrating) Architectures S2

C1 Do R1 Vi V ref S1 Control Vx Counter Logic

fc Vx T1 T2 t

Vi Vref RC RC

ADCs 25-14 Analog ICs; Jieh-Tsorng Wu Serial (Integrating) Architectures

The output is D V o = = · i T2 T1 fc Vref

• Linear search of possible subregions.

• Integrating types: single slope, dual slope, quad-slope.

• Low conversion rate. Requires 2 × 2N clock cycles for a full-scale conversion.

• The input is integrated in the T1 period, resulting in a ﬁler transfer function of sin(πT1f ) |H(f )| = πT1f

ADCs 25-15 Analog ICs; Jieh-Tsorng Wu Parallel (Flash) Architectures

Vref

1 2 2N-2 2N-1

N ( 2 -1 ) - to - N Encoder

ADCs 25-16 Analog ICs; Jieh-Tsorng Wu Parallel (Flash) Architectures

• All subregions are examined simultaneously. One comparator per subregion.

• Using 2N −1 comparators, the input is simultaneously compared with 2N −1 reference voltages derived from resistor string.

• High speed. Requires only one comparison cycle per conversion.

• Large size and power dissipation for large N.

• Design issues: input capacitive loading, clock jitter and dispersion, slew-dependent sampling point, nonlinear input capacitance, resistor-string dc and ac bowing, substrate and power-supply noises, kickback noises, sparkles in thermometer code.

• Gray encoding is often used as an intermediate step between thermometer and binary codes.

ADCs 25-17 Analog ICs; Jieh-Tsorng Wu Successive Approximation Architectures

VDA Vi VFS

VDA V i

Vref DAC 1/2 3/4 5/8 7/16

Control CLK N-1 N-3 Logic b =1 b=1 N-2 N-4 N b =0 b =1

ADCs 25-18 Analog ICs; Jieh-Tsorng Wu Successive Approximation Architectures

• Binary search of possible subregions.

• Fraction of VFS corresponding to each bit is successively (starting with MSB) added to fraction corresponding to already determined bits and sum is compared to input.

• N comparisons per conversion.

• Requires a high-speed DAC with precision on the order of the converter itself.

• Excellent trade-oﬀ between accuracy and speed.

ADCs 25-19 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution ADC

S x Vx

22N-1 C 22C 1C 20C 20C C C C C C N-1 2 1 0A 0B

SN-1S 2S 1S 0AS 0B

MSB LSB 1 Vref Vref 2 V Si i

N−1 = i + + = N Ctot 2 Ci C0A C0B 2 C i=1

ADCs 25-20 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution ADCs

Sample Mode

• → = Sx GND. Vx 0.

• ··· → S0A,S0B,S1,S2, ,SN−1,Si Vi .

Hold Mode

• Sx open.

• ··· → S0A,S1,S2, ,SN−1 GND.

• →−1 ﬀ 1 S0B 2Vref, sets transition o set to 2∆.

C V 1 V V V = −V − 0B · ref = −V − · ref ∆ = ref x i i N N Ctot 2 2 2 2

ADCs 25-21 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution ADCs

Redistribution Mode

• → Si Vref.

• Test bits one at a time in succession, beginning with bN−1.

Bit bN−1 Test

• → SN−1 Vref

1V C − 1 V V V = −V − ref + N 1 · V = −V − · ref + ref x i N ref i N 2 2 Ctot 2 2 2

• = → If Vx < 0, bN−1 1, SN−1 Vref. = → If Vx > 0, bN−1 0, SN−1 GND.

ADCs 25-22 Analog ICs; Jieh-Tsorng Wu Charge-Redistribution ADCs

= − − ··· Bit bi Test, i N 2,N 3, , 0

• → Si Vref   − − 1V V N1 C 1 V V N1 V = −V − ref + ref b 2j + i · V = −V − · ref + ref  b 2j + 2i  x i 2 2N 2N j C ref i 2 2N 2N j j=i+1 tot j=i+1

• = → If Vx < 0, bi 1, Si Vref. = → If Vx > 0, bi 0, Si GND.

ﬀ The e ect of parasitic capacitance, CP

• = · Ctot The voltage on the summing node becomes V V + . x x Ctot Cp • ﬀ Cp has no e ect on the A/D quantization characteristic, if the comparator is ideal. • CP does attenuate Vx, thus requiring higher comparator gain.

ADCs 25-23 Analog ICs; Jieh-Tsorng Wu C-R ADCs Using Input Oﬀset Storage Technique

A VOS

Capacitor Array

• ﬀ ﬀ Non-zero comparator o set can be cancelled by referencing Vx to the o set, rather than GND during sampling.

ADCs 25-24 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs

Sx M-DAC Vx

2M-1 21 20 20 CM-1 C1 C0 C0C Data Register

EN-i

Successive Calibration Approximation Control Control

L-DAC Calibration DAC Do

Calibration Basic Concept V CC< x AB Vx CC= AB t CCCC ABAB

VVref ref CC> AB (a) Initialize (b) Switch

ADCs 25-25 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs

• The error voltage Vx, thus the capacitor mismatch, can be digitized by the Calibration DAC.

• ··· During the calibration, the capacitor mismatches in CM−1,CM−2, ,C0 are measured sequentially, and stored in the data register.

• During the normal operation, the calibration DAC generate a correction voltage that compensates the error voltage caused by the mismatches in the capacitor array

• The binary-weighted capacitor array has an accuracy of about 10 bits. With self- calibration, 16-bit resolution is possible.

• Reference: H-S Lee, JSSC 12/84, pp. 813–819.

ADCs 25-26 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs

Let = + + ···+ + + + Ctot CM−1 CM−2 C1 C0 C0C Cp

Capacitor CM−1 calibration 1 C = C − ≡ C + ∆C − A M 1 2 tot M 1 1 C = C − + ···+ C + C + C = C − ∆C − B M 2 1 0 0C 2 tot M 1 C − C 2∆C − = − · A B = − · M 1 Vx Vref Vref Ctot Ctot • Using the C-DAC to digitize Vx, we obtain Dx. • Store EM−1 in the data register as ∆C = 1 = − · M−1 EM−1 Dx Vref 2 Ctot

ADCs 25-27 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs

Capacitor CM−2 calibration

1 C = C − ≡ C + ∆C − A M 2 4 tot M 2 1 C = C − + ···+ C + C + C = C − ∆C − − ∆C − B M 3 1 0 0C 4 tot M 1 M 2 C − C ∆C − + 2∆C − = − · A B = − · M 1 M 1 Vx Vref Vref Ctot Ctot

• Using the C-DAC to digitize Vx, we obtain Dx.

• Store EM−2 in the data register as

∆C = 1 − = − · M−2 EM−2 Dx EM−1 Vref 2 Ctot

ADCs 25-28 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs

= − − ··· Capacitor Ci calibration, i M 2,M 3,

1 C ≡ C + ∆C A 2M−i tot i − 1 M1 C = C − ∆C − ∆C B 2M−i tot j i j=i+1 − M 1 ∆C + 2∆C = − · j=i+1 j i Vx Vref Ctot • Using the C-DAC to digitize Vx, we obtain Dx.

• Store Ei in the data register as   − 1 M1 ∆C E = D − E  = −V · i i 2 x j ref C j=i+1 tot

ADCs 25-29 Analog ICs; Jieh-Tsorng Wu Self-Calibrating Charge-Redistribution ADCs

During normal operation, the Vx generated by the M-DAC is M−1 Ci V = V b + · x ref i L C 0 tot

The Vx is corrected by the C-DAC as M−1 M−1 M−1 c Ci ∆Ci V = V + (b + · E ) = V b + · − V b + · x x i L i ref i L C ref i L C i=0 0 tot i=0 tot M−1 − Ci ∆Ci = V b + · ref i L C i=0 tot M−1 Vref i = b + · 2 2M i L i=0

ADCs 25-30 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward (Subranging) Architectures

Aj Aj+1 Gj

da ADC DAC Aj (Dj)

Aj+1 MSBs LSBs Stage Stage Stage A i 1 2 P

D D D 0 1 2 P

Encoder Aj 0

ad ad ad Do A (-1) A (+1) A (+2)

ADCs 25-31 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward (Subranging) Architectures

The relationship between Aj and Aj+1 is A + = − da · ⇒ = da + j 1 Aj+1 Aj Aj (Dj ) Gj Aj Aj (Dj ) Gj

The input Ai can be expressed as

da da da A A A A + A = Ada + 2 + 3 + ···+ P + P 1 i 1 ··· ··· G1 G1G2 G1G2 GP −1 G1G2 GP

• da ··· If Aj (Dj ) and Gj are known, Ai can be computed from D1,D2, ,DP .

• = ··· The term, Q AP +1/(G1G2 GP ), is the conversion error (quantization error).

• ad ﬀ Aj has no e ect on the A/D result.

• Gj may include sample-and-hole function for pipeline or cyclic operation.

ADCs 25-32 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward (Subranging) Architectures

ﬀ If the Gj ampliﬁer has dc o set, i.e., A + = − da − os · ⇒ = da + os + j 1 Aj+1 Aj Aj (Dj ) Aj Gj Aj Aj (Dj ) Aj Gj

The input Ai can be expressed as

da da da A A A A + A = Ada + 2 + 3 + ···+ P + P 1 + Aos i 1 ··· ··· G1 G1G2 G1G2 GP −1 G1G2 GP

The entire system has an dc oﬀset of

Aos Aos Aos Aos = Aos + 2 + 3 + ···+ P 1 ··· G1 G1G2 G1G2 GP −1

• Ref: E. Soenen and R. Geiger, “An Architecture and An Algorithm for Fully Digital Correction of Monolithic Pipelined ADC’s,” IEEE CAS II, pp. 143–153, March 1995.

ADCs 25-33 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward Minimal Design

G = 2 A j+1 G = 4 A j+1 +1 +1

+1/2 +1/2

0 0

-1/2 -1/2 A j A j -1 -1 ADC DAC ADC DAC -1 0 +1 -10 +1

2 A + 1 G = G = G = ···= G = integer ∆A = Q = P 1 < 1 2 P ··· P G G1G2 GP G ﬀ = = 1 = × E ective Number of Bit N log2 P log2 G Qmax

• There are M = G − 1 comparators in the ADC. G is preferred to be power of 2.

• + ﬀ + ﬀ Dj has M 1di erent values, and the DAC has corresponding M 1di erent output values.

ADCs 25-34 Analog ICs; Jieh-Tsorng Wu Over-Range in the Minimal Design

Assume nonideal ADC, DAC, and G, as ˆad = ad + ad ˆda = da + da ˆ = × + g Aj Aj j Aj Aj j Gj Gj 1 j

Then we have = − da + ad − da · ˆ = − da · + Aj+1 Aj Aj (Dj ) (j j ) Gj Aj Aj (Dj ) Gj OR

The over range, OR, is = − da g + ad − da · ˆ ≤ g + ad − da · ˆ OR Aj Aj (Dj ) j Gj (j j ) Gj j (j j ) Gj

• Nonideal ADC, DAC, and G, can cause Aj+1 in minimal design stretching over the nominal input range of the j + 1 stage.

ADCs 25-35 Analog ICs; Jieh-Tsorng Wu Quantized-Feedforward Redundant Design

Minimal+2 A j+1 Minimal+1 A j+1 +1 +3/4 +1/2 +1/4 0 -1/4 -1/2 A A j -3/4 j -1 -1 0+1 -1 0 +1 ADC DAC ADC DAC

• To increase the nominal input range, one can increase M, the number of comparators in the ADCs, and the corresponding output levels in the DACs.

• The minimal+2 design provides an over-range capability of ±∆A. The minimal+1 design provides an over-range capability of ±∆A/2.

• It is also possible to avoid the over-range phenomenon by decreasing Gj .

ADCs 25-36 Analog ICs; Jieh-Tsorng Wu Digital Encoding for the Quantized-Feedforward Architecture

Stage AA2 Stage 3 Stage Stage A AP+1 i 1 2 2 P

D1 D2 D3 DP

Table Table Table Table

C1 C2 C3 CP d d D G1 G2 o

Ada Ada Ada A = Ada + 2 + 3 + ···+ P + Q i 1 ··· G1 G1G2 G1G2 GP −1 − · d d ··· d (Ai Q) G G G − 1 2 P 1 d d d d d d G G G G G ···G − = Ada Gd + Ada 1 Gd + Ada 1 2 Gd + ···+ Ada 1 2 P 1 1 1 2 2 3 3 P ··· G1 G1G2 G1G2 GP −1

ADCs 25-37 Analog ICs; Jieh-Tsorng Wu Digital Encoding for the Quantized-Feedforward Architecture

Let d d ··· d G1 G2 Gj−1 C = Ada(D ) · j j j ··· G1G2 Gj−1 The digital output can be obtained by = d + d + ···+ d + Do (C1) G1 C2 G2 CP −1 GP −1 CP

• Nonlinear A/D conversion occurs, if

d d ··· d G1 G2 Gj−1 C = Aˆda(D ) · j j j ˆ ˆ ··· ˆ G1G2 Gj−1

ADCs 25-38 Analog ICs; Jieh-Tsorng Wu A Radix-2 1.5 Bit SC Pipeline Stage

2 1 Cf Conversioin Phase 1 1 f Vj Vj+1 C 0.25V 0.25 V r r Vj Vj+1 g 1 gC C 2 Vr xDj Conversion Phase 2

f Encoder D j = −1, 0, +1 C Vj+1 A j+1 Vr xDj 0.5 V 1 g L r C C 0.25 Vr

00 A j

0.25 Vr

0.5 Vr 1 0 ADC D j DAC 0.25 Vr 0.25 Vr Minimal+1 0.75 Vr 0.75 Vr

ADCs 25-39 Analog ICs; Jieh-Tsorng Wu A Radix-2 1.5 Bit SC Pipeline Stage

During phase 2 g g V = + C − × = + C − r × Vj+1 Vj (Vj Vr Dj ) 1 Vj Dj Cf Cf 1 + Cf /Cg V = 2 × V − r × D if Cf = Cg j 2 j

• ± The full range of the input/output is 0.5Vr .

• ± The pipeline stage has input over-range capability of 0.25Vr.

ADCs 25-40 Analog ICs; Jieh-Tsorng Wu Multi-Bit Switched-Capacitor Pipeline Stage

2 1 Cf 1 Vj Vj+1

1 g0 C Comparator 0 2 Bank Vr x D j 1 g1 C 1 2 Vr x D j D j

= 0 · 0 + 1 · 1 + ··· K · K −1 k ∈{− + } Dj Dj 2 Dj 2 Dj 2 Dj 1, 0, 1 − Cf Cg0 Cg1 Cg(K 1) = = = ···= = C 20 20 21 2N−1 g0 + g1 + ···+ g(K −1) C C C K Vr V + = G × V − ∆V × D G = 1 + = 2 ∆V = j 1 j j j j Cf 2K

ADCs 25-41 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Pipelined ADCs

The SC stage has a voltage gain of

Cg G = 1 + Cg = Cg0 + Cg1 + Cg2 + ··· Cf

The settling time requirement can be expressed as Cf + CL Cg Ci Cf + CL Ci T = 1 + + · ln 2y+1 ⇒ G = G + · (y + 1) ln 2 s f f m f Gm C C Ts C

Other constraints are

Total Power ∝ G + G + ···+ G m,1 m,2 m,P 1 1 1 Total Input Referred Thermal Noise Power = P ∼ kT + + ··· θ s 2 s 2 s C1 (G1) C2 (G1G2) C3

ADCs 25-42 Analog ICs; Jieh-Tsorng Wu Switched-Capacitor Pipelined ADCs

• Gm is the opamp’s transconductance.

• Ci is the opamp’s input capacitance.

• s = f + g Cj Cj Cj is the j-stage sampling capacitances.

• L s + C includes Cj+1 and input loading of the comparator bank in the j 1 stage.

• y (bits) is the resolution requirement of the j stage.

• = s s Use capacitor scaling, α Cj /Cj+1, total power dissipation can be minimized while ∼ maintaining noise performance. It can be shown that αopt G.

• Increasing G (and M) per stage generally reduces total power dissipation.

• Reference: D. Cline and P. Gray, “A Power Optimized 13-b 5Ms/s Pipelined ADC,” JSSC, March 1996, pp. 294–303.

ADCs 25-43 Analog ICs; Jieh-Tsorng Wu Single-Stage Calibration and Digital Correction

A A j 0 j+1 ADC 1 Z Gj

A c ADC 0 CAL da DAC Aj 1 Dz

Dc CAL

The signal Aj+1 is quantized the following Z-ADC with = ˆ · − ˆda − os = G · + os + Aj+1 Gj Aj A (Dj ) A Dz Q Q j j Gˆ

• G/Gˆ is the gain error, Qos is the oﬀset, and Q is the quantization error.

ADCs 25-44 Analog ICs; Jieh-Tsorng Wu Single-Stage Calibration and Digital Correction

ˆda During calibration, Aj is disabled and Aj (Dc) is quantized by measuring

ˆ · − os = G · + os + Gj Ac A Dz1 Q Q1 Gˆ ˆ · − ˆda − os = G · + os + Gj Ac A (Dc) A Dz2 Q Q2 j Gˆ

Subtracting the above two equations, we have

ˆ · ˆda = G · − + − = G · + c ∈{ } Gj A (Dc) (Dz1 Dz2) Q1 Q2 Dz(Dc) 2Q (Dc) Dc Dj j Gˆ Gˆ c Gj G 2Q (D ) D (D ) ⇒ Aˆda(D ) = · T (D ) + c T (D ) = z c D ∈{D } j c ˆ ˆ j c ˆ j c G c j Gj G Gj j

ADCs 25-45 Analog ICs; Jieh-Tsorng Wu Single-Stage Calibration and Digital Correction

The combined ADC with j-Stage and Z-ADC has the following characteristic:

c A + G G 2Q (D ) A + = ˆda + os + j 1 = j · + j + os + j 1 Aj A (Dj ) A Tj (Dj ) A j j Gˆ Gˆ Gˆ Gˆ j Gˆ j j j j os c + Gj G D Q 2Q (Dj ) Q = T (D ) + z + Aos + + ˆ ˆ j j G j ˆ ˆ Gj G j Gj Gj = G · + os + Dz Q Q Gˆ D G Gj G Digital Output = D = T (D ) + z Gain Error = = z j j G ˆ ˆ ˆ j G Gj G os c Q 2Q (Dj ) Q Oﬀset = Qos = Aos + Quantization Error = Q = + j ˆ ˆ ˆ Gj Gj Gj

• ˆda ˆ ﬀ Nonideal Aj and Gj have no e ect on the A/D linearity.

ADCs 25-46 Analog ICs; Jieh-Tsorng Wu Multi-Stage Calibration and Digital Correction

A Q i Stage A2 Stage Stage AP Stage AP+1 Stage x 1 2 P-1 P X

D1 D2 DP-1 DP Dx

Table Table Table Table Table

T1 T2 TP-1 TP Tx d d d D G1 GP-1 GP o

Assume the stage X ADC has a characteristic of

Gx os A + = · T + Q + Q P 1 ˆ x x x Gx

• Calibration is performed stage-by-stage, from Stage P to Stage 1.

ADCs 25-47 Analog ICs; Jieh-Tsorng Wu Multi-Stage Calibration and Digital Correction

Use the X ADC to calibrate stage P . Then, the P + X ADC can be expressed as os c + G G T Q 2Qx,P Qx A = P x T + x + Aos + x + P ˆ ˆ P G P ˆ ˆ GP Gx P GP GP

Use the P + X ADC to calibrate stage (P − 1). Then, the (P − 1) + P + X ADC can be expressed as G − G G T T = P 1 P x + P + x AP −1 TP −1 Gˆ − Gˆ Gˆ GP −1 GP −1GP P1 P x os os c + c + A Q 2Qx,P −1 2Qx,P Qx + Aos + P + x + P −1 ˆ ˆ ˆ ˆ ˆ GP −1 GP −1GP GP −1GP

Repeat the calibration procedures for stage (P − 2), (P − 3),...,2,and1.

ADCs 25-48 Analog ICs; Jieh-Tsorng Wu Multi-Stage Calibration and Digital Correction

The full calibrated ADC can be expressed as G T T T = T + 2 + ···+ P + x + os + Ai T1 QT QT ˆ G G G ···G − G G ···G GT 1 1 2 P 1 1 2 P where

G G G ···G G T = 1 2 P x ˆ ˆ ˆ ··· ˆ ˆ GT G1G2 GP Gx Aos Aos Qos Qos = Aos + 2 + ···+ P + x T 1 ˆ ˆ ˆ ··· ˆ ˆ ˆ + ··· ˆ G1 G1G2 GP −1 G1G2 GP c + c + ···+ c + 2Qx,1 2Qx,2 2Qx,P Qx (2P + 1) ×|Q | Q = ≤ x max T ˆ ˆ ··· ˆ ˆ ˆ ··· ˆ G1G2 GP G1G2 GP

ADCs 25-49 Analog ICs; Jieh-Tsorng Wu Multi-Stage Calibration and Digital Correction

• ˆ ﬀ os The scaling factor GT /GT and o set QT can be determined by quantizing two known = = input, e.g., Ai 0 and Ai Aref.

• The eﬀects of noise can be suppressed by averaging a number of successive measurements during calibration.

• ﬀ ˆda During j stage calibration, to avoid overloading the Aj+1 port, di erent Aj (Dc) ﬀ measurement may need di erent Ac value.

• On the circuit level, the eﬀectiveness of calibration is limited by noises, interferences,

nonlinear Gj , and ampliﬁer transient behavior.

ADCs 25-50 Analog ICs; Jieh-Tsorng Wu Calibration of A Radix-2 1.5 Bit SC Pipeline Stage

Calibration Phase 1 2 1 Cf f 1 C Vj Vj+1 Vc Vj+1 0.25Vr 0.25 Vr g C 1 g C 2 Calibration Phase 2 Vr xDj Cf Encoder D j = −1, 0, +1 Vj+1

Vr xDc g L C C

• ˆda = = = To calibrate Aj (Dj 1). Obtain Dz1 by letting Vc 0.25Vr and Dc 0, and obtain Dz2 = = = = − by letting Vc 0.25Vr and Dc 1. Then Tj (Dj 1) (Dz1 Dz2)/Gj .

• ˆda = − = − = To calibrate Aj (Dj 1). Obtain Dz1 by letting Vf 0.25Vr and Dc 0, and obtain = − = − = − = − Dz2 by letting Vc 0.25Vr and Dc 1. Then Tj (Dj 1) (Dz1 Dz2)/Gj .

ADCs 25-51 Analog ICs; Jieh-Tsorng Wu A Radix-2 Cyclic ADCs

Vj+1 Vj S/H x 2 Vi

VR VR Dj VR V + = 2 × V − D × V = 2 × V + D · D ∈{+1, −1} j 1 j j R j j 2 j

• = = Start with j 1 and V1 Vi .

• For each cycle, j is increased by 1.

ADCs 25-52 Analog ICs; Jieh-Tsorng Wu A Radix-2 Switched-Capacitor Cyclic ADC

C 2 S6 C C S1 1 6 Vi Dj A A 1 3 C = C = C = C = C S2 1 2 3 4 VR C5 S5 C3 = C5 2C ∈{ } C Dj 1, 0 S3 4

A2   N 1 V = V ×  D · 2−j −  i R j 2 j=1

ADCs 25-53 Analog ICs; Jieh-Tsorng Wu A Radix-2 Switched-Capacitor Cyclic ADC

Input Sampling (1) Input Sampling (2) C2

C1 C6 C1 C6 Vi D1 A1 A3 A1 A3

C5 C3 C5 C3

A2 A2

j-Cycle (2) j-Cycle (1) C2

C1 C6 C1 Vj+1 C6 Dj+1 A A A A Dj x VR 1 3 Dj x VR 1 3 C C5 4 C3 C5 C3

A2 A2

ADCs 25-54 Analog ICs; Jieh-Tsorng Wu A CMOS Subranging Flash ADC — Dingwall

Vi 1 1 VR 2 1 1

2 VK VK 1 1

M-ADC Comparator Bank

31313131

1 1 1 1 L-ADC Comparator Bank

ADCs 25-55 Analog ICs; Jieh-Tsorng Wu A CMOS Subranging Flash ADC — Dingwall

• Two-Stage quantized-feedforward architecture. M − = – The ﬁrst-stage M-ADC has 2 1 comparators, and G1 1. – The second-stage L-ADC has 2L − 1 comparators. = + – For minimal design, Do has N M L bits.

• The S/H and the subtractor function is embedded in every comparator. Require no additional subtractor or DAC.

• Comparators in both M-ADC and L-ADC need to have N-bit accuracy.

• The input range of the L-ADC can be extended to prevent over-loading. The accuracy requirement for the M-ADC can then be relaxed.

• Reference: A. Dingwall, et. al., “An 8-MHz CMOS Subranging 8-Bit A/D Converter,” JSSC 12/1985, pp. 1138–1143.

ADCs 25-56 Analog ICs; Jieh-Tsorng Wu A CMOS Subranging Flash ADC — Brandt

ADCs 25-57 Analog ICs; Jieh-Tsorng Wu Interpolated Diﬀerential Comparator Bank

ADCs 25-58 Analog ICs; Jieh-Tsorng Wu A CMOS Subranging Flash ADC — Brandt

• Two-stage quantized-feedforward diﬀerential architecture.

• − = − ↔ + − = ↔ + The voltage ranges are Cin+ Cin− [ 2 2] and Fin+ Fin− [0 2].

• The absolute-value processing reduces the number of switches in the AMUXs by half. In addition, the settling time of the AMUX outputs is also reduced due to the reduction in output voltage swing and output capacitive loading.

• The interpolation scheme can reduce the number of “taps” from the reference ladder and reduce the number of preampliﬁers. It also attenuates front-end sources of DNL, such as mismatches in the input sampling switches and resistor mismatch in the reference ladder.

• Reference: B. Brandt, et. al., “A 75-mW, 10-b 20-MSPS CMOS Subranging ADC,” JSSC 12/1999, pp. 1788–1795.

ADCs 25-59 Analog ICs; Jieh-Tsorng Wu Flash Quantization Architecture

01 234567 VRB VRT

Vi 012 3 4 5 6 7

V0 V2 V4 V6

N Thermometer-to-Binary Encoder Do

V0 V2 V4 V6 Thermometer Code 00000000 0 10000000 1 11000000 2 11100000 3 11110000 4 11111000 5 11111100 6 11111110 7 11111111 Vi

ADCs 25-60 Analog ICs; Jieh-Tsorng Wu Resistor-String Interpolation

0 1 2 3 4 5 6 7 VRB VRT

Vi 042 6

V0 V2 V4 V6

N Thermometer-to-Binary Encoder Do

V0 V2 V4 V6 Thermometer Code 00000000 0 10000000 1 11000000 2 11100000 3 11110000 4 11111000 5 11111100 6 11111110 7 11111111 Vi

ADCs 25-61 Analog ICs; Jieh-Tsorng Wu Folding

0 1234 5 6 7 8 VRB VRT

Vi 0 4 125 6 37

V0 V1 V2 V3

N Circular-to-Binary Encoder Do

V0 V1 V2 V3 Circular Code 0000 0 1000 1 1100 2 1110 3 1111 4 0111 5 0011 6 0001 7 0000 Vi

ADCs 25-62 Analog ICs; Jieh-Tsorng Wu Interpolation and Folding

• The number of latch comparators is reduced by folding, while the number of folding blocks is reduced by interpolation.

• The interpolation can reduce the input capacitances for Vi , VRT, and VRB, since the number of the preamplifers is reduced.

• The interpolation can improve the DNL, due to the redistribution of mismatch errors.

• The interpolation technique can also be used with other types of signals, such as currents and charges.

• The folding circuit need only to be accurate near the zero-crossing points.

ADCs 25-63 Analog ICs; Jieh-Tsorng Wu Averaging Preampliﬁers

VDD VDD VDD

R R R R

RRRR

I I I

VSS VSS VSS

• The outputs are connected by interpolating resistor string.

• Gain is determined by R × I.

• Speed is determined by R × C.

ADCs 25-64 Analog ICs; Jieh-Tsorng Wu Eﬀects of Averaging

Input and Reference R-String

Averaging R-String

I o

m = 5

Input Range

• Diﬀerential nonlinearity (DNL) improves with m. √ • Integral nonlinearity (INL) improves with m.

ADCs 25-65 Analog ICs; Jieh-Tsorng Wu Bending at the Edges Due to Averaging

Input and Reference R-String

Averaging R-String

Use Resistor-Ring to Mitigate Edge Effect

ADCs 25-66 Analog ICs; Jieh-Tsorng Wu Cascaded Folding

Input and Reference R-String

Averaging Resistor Ring and 3X Folding

M-ADC

• Too many folding in one stage can cause gain-loss.

• Require odd number of single-stage folding to maintain continuity.

ADCs 25-67 Analog ICs; Jieh-Tsorng Wu Diﬀerential Preampliﬁer

VDD

M3 M5M6 M4

= · 1 Adm gm1 − Vo gm3 gm5 g 1 M1 M2 A = m1 · cm + + 1 2g r g 3 g 5 Vi m1 o7 m m

VBN M7

VSS

• Additional common-mode feedback is not required.

ADCs 25-68 Analog ICs; Jieh-Tsorng Wu A CMOS 10-Bit Folding ADC — Bult

• Reference: K. Bult, et. all, “An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,” JSSC 12/1997, pp. 1887–1895.

ADCs 25-69 Analog ICs; Jieh-Tsorng Wu Time-Interleaved Architectures

Ai Tc

φ1 φ1 S/H φ2 S/H φ m S/H φ2

ADC ADC ADC 1 2 m φ m NN N N Do Multiplexer t

• The equivalent sampling rate is m/Tc.

• Clock phase as well as clock jitter need to satisfy N-bit accuracy.

• Any mismatch among the converter characteristics, including oﬀset and gain, can

appear as noises and/or spurious tones in Do.

ADCs 25-70 Analog ICs; Jieh-Tsorng Wu Oversampling Converters

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Sampling and Quantization

pdf of e(k) Quantizer x(k) x(t) D(z) y(k) e(k) f s /2 /2 N−Bit | D(f) | e(k) S e (f) x(k) D(z) y(k) f 0 f /2 f f f /2 s B B s e(k)isaquantization noise due to the quantization process. With an ideal quantizer with step size ∆, The pdf of e(k) is assumed to be uniformly distributed over −∆/2 and +∆/2. 1 e(k) ≡ y(k) − x(k) Noise Power = P = e2pdf(e)de = ∆2 n 12

Oversampling 26-2 Analog ICs; Jieh-Tsorng Wu Oversampling

Assume the noise e(k) is white and is independent of fs, then the noise spectral density is P = n = 1 2 × 1 Sn(f ) ∆ fs 12 fs For a full-scale sinusoidal input

1 1 1 x(k) = A sin(2πf · kT ) A = 2N∆ Signal Power = P = · A2 = · 22N∆2 2 i s s 8 8

Assume the bandwidth of x(k) is limited to fB. The oversampling ratio, OSR, is deﬁned as f OSR = s 2fB The noise at the output of D(z) ﬁlter is

+ fB 2f = · = 1 2 × B Pn Sn(f ) df ∆ − 12 fB fs

Oversampling 26-3 Analog ICs; Jieh-Tsorng Wu Oversampling

The signal-to-noise ratio of y(k) becomes

P f ≡ s = 3 × 2N × s = + · + SNRy,max 2 1.76 6.02 N 10 log(OSR) dB Pn 2 2fB

• Oversampling gives a SNR improvement of 3 dB/octave or 0.5 bit/octave.

• High-speed digital ﬁlters, D(z), are required.

• Oversampling also eases the anti-alias ﬁlter design for x(t).

• Oversampling does not improve linearity. Linear quantizers are still required.

• One-bit quantizers and one-bit DACs are inherently linear. Therefore, they are often used in oversampling converters.

Oversampling 26-4 Analog ICs; Jieh-Tsorng Wu First-Order ∆Σ Modulator

e(k)

y(k)u(k) y(k) 1 x(t) Integrator x(k) z

D/A

Y (z) Signal Transfer Function = S (z) = = z−1 TF X (z) Y (z) Noise Transfer Function = N (z) = = 1 − z−1 TF E(z)

The noise transfer function in frequency domain is πf − = | = × × jπf/fs NTF(f ) NTF(z) z=ej2πf/fs sin 2j e fs

• = = Noise power is small near f 0 and becomes large near f fs/2.

Oversampling 26-5 Analog ICs; Jieh-Tsorng Wu First-Order ∆Σ Modulator

The quantization noise power in the fB frequency band is

+ + fB fB 2 2 = | |2 = ∆ 1 πf · Pn Se(f ) NTF(f ) df 2 sin df − − 12 fB fB fs fs

If OSR 1, then ∆2 π2 2f 3 ∆2π2 1 P ≈ · B = n 3 12 3 fs 36 OSR P 9 SNR ≡ s = × 22N × OSR3 = −3.41 + 6.02 · N + 30 log(OSR) dB y,max 2 Pn 2π

• Oversampling gives a SNR improvement of 9 dB/octave or 1.5 bit/octave.

• The integrator’s output is u(k + 1) = x(k) − e(k). If x is a dc input and bounded by the | | | | = | | + full range of D/A, then e <∆/2 and u max x ∆/2.

Oversampling 26-6 Analog ICs; Jieh-Tsorng Wu First-Order ∆Σ Modulator with SC Circuit Implementation

C C A 1 1 2 V i y(n)

2 1

2 C 2, 1 2 V R

1, 2

• = One-bit ∆Σ modulator. VR ∆/2.

• ∈{+ − } The comparator latches on the falling edge of φ2. The output y(n) 1, 1 .

• C1 and C2 can be combined into one capacitor.

Oversampling 26-7 Analog ICs; Jieh-Tsorng Wu Circuit Considerations

For an ideal integrator H(z), we have

− z 1 H(z) 1 H(z) = S (z) = = z−1 N (z) = = 1 − z−1 1 − z−1 TF 1 + H(z) TF 1 + H(z)

• If the integrator includes a gain factor G, then

− − − z 1 Gz 1 1 − z 1 H(z) = G × S (z) = N (z) = 1 − z−1 TF 1 − (1 − G)z−1 TF 1 − (1 − G)z−1

– Small deviations of G from unity have little eﬀect on the overall performance, provided the net gain in the feedback loop is large. – 10% gain accuracy of G is tolerable.

Oversampling 26-8 Analog ICs; Jieh-Tsorng Wu Circuit Considerations

• If the opamp has a ﬁnite gain of Ao, then

− z 1 1 H(z) ≈ where β = 1 − −1 1 − βz Ao − − z 1 1 − βz 1 S (z) = N (z) = TF 1 + (1 − β)z−1 TF 1 + (1 − β)z−1

– NTF(f )isﬂatfor2πf /fs < 1/A o. – Want fB fs/(2πAo)orAo OSR/π. – Usually want Ao > 2OSR.

• Noises or harmonics arising from the quantizer’s nonlinearity are suppressed by

NTF(z), making the quantizer less critical.

• The linearity of the D/A is very important.

Oversampling 26-9 Analog ICs; Jieh-Tsorng Wu Second-Order ∆Σ Modulator u 1 2 y(k) x(k) z

1 z u 1

D/A

The transfer functions are

Y (z) Y (z) 2 S (z) = = z−1 N (z) = = 1 − z−1 TF X (z) TF E(z)

The noise transfer function in frequency domain is

2 | | = πf NTF(f ) 2 sin fs

Oversampling 26-10 Analog ICs; Jieh-Tsorng Wu Second-Order ∆Σ Modulator

If OSR 1, the quantization noise power is

2 4 ≈ ∆ π 1 Pn 60 OSR5

And

15 SNR = × 22N × OSR5 = −11.14 + 6.02 · N + 50 log(OSR) dB y,max 2π4

• Oversampling gives a SNR improvement of 15 dB/octave or 2.5 bit/octave.

Oversampling 26-11 Analog ICs; Jieh-Tsorng Wu Integration Range in a Second-Order ∆Σ Modulator

The outputs of the integrators are

+ = − + − + = − − − + − u1(k 1) x(k) e(k) e(k 1) u2(k 1) x(k 1) 2e(k 1) e(k 2)

For multi-bit quantization:

• For small |x|, e is bounded by ±∆/2.

• If |e| <∆/2, then

| |≤| | + | | + | − |≤| | + u1 x(k) e(k) e(k 1) x ∆ 3 |u |≤|x(k)| + 2|e(k = 1)| + |e(k − 2)|≤|x| + ∆ 2 2

Oversampling 26-12 Analog ICs; Jieh-Tsorng Wu Integration Range in a Second-Order ∆Σ Modulator

• One-bit quantization.

• D/A output levels are ±1.

• The integrators are bounded by

| | = | | + u1 max x 2 (5 −|x|)2 |u | = 2 max 8(1 −|x|)

• In practice, the ﬁrst accumulation is often clipped at ±2, and the second eﬀectively ±4.

Oversampling 26-13 Analog ICs; Jieh-Tsorng Wu Overloading in a Second-Order ∆Σ Modulator

• D/A levels are ±0.5, ±1.5, and ±2.5.

• ∆ is the same for all three cases.

• For large x, the input to the quantizer can be so large that |e| >∆/2. The excess noise can degrade the SNR of y.

• In the two-level case (1-bit quantization), the comparator is theoretically overloaded for all conditions, except zero input with zero initial conditions.

Oversampling 26-14 Analog ICs; Jieh-Tsorng Wu Oversampling ADCs

x (t) x(n) y(n) y (n) y (n) c p b

Anti− ∆Σ Digital Aliasing Sampling Low−Pass L Modulator Filter Filter

Decimation Filter f s

x (t) c Xc(jΩ)

t Ω 0 2T 6T s 4T s 0 Ω s b Ωs jω x(n) X e

n ω 0 123456 0 2π

Oversampling 26-15 Analog ICs; Jieh-Tsorng Wu Oversampling ADCs jω y(n) Y e

n ω 0 2π Y ejω yp (n) p

n ω 0 123456 0 2π jω y (n) Yb e b

n ω 0 1 2 3 0 2π 4π

Oversampling 26-16 Analog ICs; Jieh-Tsorng Wu Oversampling DACs

x (n) x (t) x(n) y(n) y (t) y (t) b p d c

Interpolation ∆Σ Digital L Low−Pass D/A Analog Modulator Filter Filter

f s jω x (n) Xb e b

n ω 0 1 2 3 2π 0 jω x (n) Xp e p

n ω 0 123456 0 2π 4π

Oversampling 26-17 Analog ICs; Jieh-Tsorng Wu Oversampling DACs jω x(n) X e

n ω 0 123456 0 2π y(n) Y ejω

n ω 0 2π

y (t) d Yd (jΩ)

t Ω 0 Ω Ω 0 2Ts 4Ts 6Ts b s

Oversampling 26-18 Analog ICs; Jieh-Tsorng Wu Oversampling DACs y(n) Y ejω

n ω 0 2π

y (t) d Yd (jΩ)

t Ω 0 Ω Ω 0 2Ts 4Ts 6Ts b s

y c (t) Yc(jΩ)

t Ω 0 0 Ω b Ωs

Oversampling 26-19 Analog ICs; Jieh-Tsorng Wu General Single-Stage ∆Σ Modulator

x(k) G(z) y(k)

F(z)

G(z) 1 Y (z) = · X (z) + · E(z) = S (z) · X (z) + N (z) · E(z) 1 + F (z)G(z) 1 + F (z)G(z) TF TF

• OSR is typically between 16 and 256.

• The loop gain, L(z) = F (z)G(z), need to be high in the band of interest.

• The poles L(z) are the zeros of NTF(z).

• + = Both STF(z) and NTF(z) generally share the same poles, the roots of 1 L(z) 0.

Oversampling 26-20 Analog ICs; Jieh-Tsorng Wu General Single-Stage Error-Feedback Coder

x(k) y(k)

N(z) − 1 e(k)

Y (z) = X (z) + N(z) · E(z)

• A slight coeﬃcient error can degrade noise-shaping signiﬁcantly.

• Not suitable for analog modulators, only appropriate for digital modulators.

Oversampling 26-21 Analog ICs; Jieh-Tsorng Wu Single-Stage High-Order Modulators

cc12

1 1 1 1 1 z z z z z x(k) 1 1 1 1 1 1 z 1 z 1 z 1 z 1 z

a 1234a a a a 5

y(k)

• An Nth-order noise-shaping modulator improves the SNR by (6N + 3) dB/octave, or equivalently, (N + 0.5) bits/octave.

Oversampling 26-22 Analog ICs; Jieh-Tsorng Wu Single-Stage High-Order Modulators

= = If c1 c2 0,

a a a L(z) = G(z) = 1 + 2 + 3 + ··· (z − 1)1 (z − 1)2 (z − 1)3 1 (z − 1)n N (z) = = S (z) = 1 − N (z) TF 1 + L(z) D(z) TF TF

• L(z) has all its poles at z = 1 (or f = 0).

• = = NTF(z) has all its zeros at z 1 (or f 0).

• Butterworth high-pass ﬁlters are often used for NTF(z).

• STF(z) contains peaking at high frequencies.

= = = If c1 0 and c2 0, the poles of L(z) can be moved away from z 1 along the unit circle.

Oversampling 26-23 Analog ICs; Jieh-Tsorng Wu Single-Stage High-Order Modulators x(k)

b 1 b 2 b 3 b 4 b 5

c 1 c 2

1 1 1 1 1 z z z z z 1 1 1 1 1 1 z 11z z 1 z 1 z

a 1 a 2 a 3 a 4 a 5 y(k)

Oversampling 26-24 Analog ICs; Jieh-Tsorng Wu Single-Stage High-Order Modulators

= = If c1 c2 0, a a a L(z) = 1 + 2 + 3 + ··· (z − 1)n−0 (z − 1)n−1 (z − 1)n−2 b b b G(z) = 1 + 2 + 3 + ··· (z − 1)n−0 (z − 1)n−1 (z − 1)n−2 2 1 (z − 1)n b + b (z − 1) + b (z − 1) + ··· N (z) = = S (z) = 1 2 3 TF 1 + L(z) D(z) TF D(z)

• The numerator of STF(z) is arbitrary, but has an order that is one less than D(z). • The STF(z) does not contain signiﬁcant peaking.

• Each integrator output contain signiﬁcant amounts of the input signal as well as ﬁltered quantization noise.

= = = If c1 0 and c2 0, the poles of L(z) can be moved away from z 1 along the unit circle.

Oversampling 26-25 Analog ICs; Jieh-Tsorng Wu Stability of Single-Stage High-Order Modulators

Quantizer Im(z) e(k)

x(k) G(z) α y(k) Re(z)

F(z)

αG(z) 1 Y (z) = · X (z) + · E(z) 1 + αG(z)F (z) 1 + αG(z)F (z)

• A modulator is called stable, if the input to the quantizer does not become overloaded, i.e., e(k) ≤±∆/2.

• All high-order modulators (N>2) are conditionally stable.

• Modulators with multi-bit quantizer and DAC exhibit improved stability.

Oversampling 26-26 Analog ICs; Jieh-Tsorng Wu Stability of Single-Stage High-Order Modulators

For single-stage modulators with one-bit quantizer and DAC:

• jω ≤ As a general rule of thumb, stability can be achieved by keeping NTF e 1.5.

• A modulator can be made more stable by placing the poles closer to the zeros in

NTF(z). But, the SNR is also degraded since the out-of-band gain of NTF(z) is also reduced.

• Stability is also related to the input signal level. Typically want 50Ð80% of ∆ for stable input range.

• “Signal overload” and “power on” may cause a conditionally stable modulator to oscillator. Need additional mechanism to detect instability and force the loop becoming stable.

Oversampling 26-27 Analog ICs; Jieh-Tsorng Wu Multi-Stage Cascaded Modulators

x(k) H (z) y (k) 1 1

D/A

Error y(k) Cancel e (k) 1 H (z) y (k) 2 2

D/A

= · + · = · + · Y1(z) S1(z) X (z) N1(z) E1(z) Y2(z) S2(z) E1(z) N2(z) E2(z)

Oversampling 26-28 Analog ICs; Jieh-Tsorng Wu Multi-Stage Cascaded Modulators

The error cancellation logic is

= · − · Y (z) S2(z) Y1(z) N1(z) Y2(z)

= = = · − · If S2(z) S2(z) and N1(z) N1(z), then Y (z) S1(z)S2(z) X (z) N1(z)N2(z) E2(z).

• Also called multi-stage noise shaping (MASH) architecture.

• Individual loop can be low-order and stable. The resulting noise shaping function ··· N1(z)N2(z) is high-order.

• Sensitive to mismatches between the analog and digital circuitry.

• For low-order loop, the ﬁnite opamp gain can cause noise leak-through.

• y(k) has more than one bit, thus complicates the output DAC design in D/A applications or the decimation ﬁlter design in A/D applications.

Oversampling 26-29 Analog ICs; Jieh-Tsorng Wu A Third-Order (1-1-1) Cascaded Modulators

y (k) 1 1 2 1 x(k) z z z y(k)

D/A q (k) 1 y (k) y (k) 2 4 1 2 z z 1 z

D/A q (k) 2 y (k) 3 1 z 1 z

D/A

Oversampling 26-30 Analog ICs; Jieh-Tsorng Wu A Third-Order (1-1-1) Cascaded Modulators

The outputs of the quantizers are = −1 + − −1 = − = −1 − Y1 z X 1 z E1 Q1 Y1 E1 z (X E1) = −1 + − −1 = − = −1 − Y2 z Q1 1 z E2 Q2 Y2 E2 z (Q1 E2) = −1 + − −1 = −2 − −2 + − −1 Y3 z Q2 1 z E3 z Q1 z E2 1 z E3

We have = −2 + − −1 = −2 + − −1 2 = −3 − −3 + − −1 2 Y4 z Y2 1 z Y3 z Q1 1 z E3 z X z E1 1 z E3 and = −3 + − −1 = −3 + − −1 3 Y z Y1 1 z Y4 z X 1 z E3

Oversampling 26-31 Analog ICs; Jieh-Tsorng Wu Idle Channel Tones (Pattern Noises)

For a 1st-order 1-bit modulator and ±∆ = ±1,

y(k) = sgn[u(k)] = u(k) + e(k) u(k + 1) = u(k) + x(k) − y(k)

If x(k) = 0 and u(0) = 0, then

y(k) = (+1, −1) ··· e(k) = (+1, 0) ···

If x(k) = 1/3 and u(0) = 0, then

y(k) = (+1, −1, +1) ··· e(k) = (+1, −1/3, +1/3) ···

If x(k) = 1/2 and u(0) = 0, then

y(k) = (+1, −1, +1, +1) ··· e(k) = (+1, −1/2, 0, +1/2) ···

Oversampling 26-32 Analog ICs; Jieh-Tsorng Wu Idle Channel Tones (Pattern Noises)

• In above examples, e is periodic and nowhere near white. Diﬀerent initial states just shift the sequence and the values of e.

• For bounded input |u| < 1, x is rational ⇔ y is periodic.

• Low-frequency tones cannot be ﬁltered out by the following decimation ﬁlter.

• Tones also exists in higher-order modulators. The tones might not lie at a single frequency but instead be short-term periodic patterns.

• Nearly all types of modulators can produce very high-powered tones near fs/2. Clock noise near this frequency can couple and demodulate these tones down into the baseband.

• For ac input, strong peaks and dips in the output noise power may be seen for certain input frequencies and amplitudes.

Oversampling 26-33 Analog ICs; Jieh-Tsorng Wu Noise-Shaped Dithering for Single-Stage Modulators d(k)

x(k) G(z) y(k)

F(z)

• d(k) is a pseudo-random noise. It is usually generated by a PN sequence generator.

• The power d(k) must be comparable to that of e(k). The pdf of d(k) usually spans more than ∆/2.

• d(k) may require 3Ð8 quantization levels for eﬀective dithering.

Oversampling 26-34 Analog ICs; Jieh-Tsorng Wu Noise-Shaped Dithering for Multi-Stage Cascaded Modulators

d (k) 1 1 1 z y (k) 1 1 1 x(k) z z y(k) 1 z

D/A

d (k) e (k) 2 1 y (k) 2 1 1 1 z 1 z 1 z

D/A

= −1 + − −1 2 + − −1 3 = −1 + − −1 + − −1 Y1 z X 1 z E1 1 z D1 Y2 z E1 1 z E2 1 z D2 = −1 − − −1 2 = −2 + −1 − −1 3 − − −1 3 Y z Y1 1 z Y2 z X z 1 z D1 1 z D2

Oversampling 26-35 Analog ICs; Jieh-Tsorng Wu Multi-Bit ∆Σ Modulator e(k) A/D Converter

x(k) G(z) y(k)

F(z) D/A

n(k) e(k) D/A Converter y(k) x(k) G(z) D/A y(t)

n(t)

F(z)

Oversampling 26-36 Analog ICs; Jieh-Tsorng Wu Multi-Bit ∆Σ Modulator

For the A/D converter

G(z) 1 F (z)G(z) Y (z) = X (z) + E(z) − N(z) 1 + F (z)G(z) 1 + F (z)G(z) 1 + F (z)G(z) ≈ + − STF(z)X (z) NTF(z)E(z) N(z)

• Out-of-band noise is reduced. Requirements for the analog circuitry are less severe.

• Since they have better stability, more aggressive noise transfer functions may be used.

• The DAC linearity errors are not shaped. The DAC must be nearly as linear as the complete converter.

Oversampling 26-37 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Dynamic Element Matching

Unit Elements M M v Randomizer Ao 2 Analog Output 1

v 01234

Oversampling 26-38 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Dynamic Element Matching

No Scrambling Random Scrambling

Signal Signal n

n freq freq

• For any value of v, the averaged error in Ao is zero.

• Whitens the mismatch noise.

• The randomizer may consists of a thermometer-type encoder, a random-number generator, and a switchbox. Butterﬂy structure is often used to simpliﬁed the switchbox design.

• Reference: Ian Galton, “A Rigorous Error Analysis of D/A Conversion with Dynamic Element Matching,” Tran. on Circuits and SystemsÐII, pp. 763Ð772, 12/95.

Oversampling 26-39 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Data-Weighted Averaging

M M DWA v(k) Ao Selector 2 Analog Output 1

v(1)=3 v(2)=4 v(3)=2 DWA Scrambling

Signal n

freq

Oversampling 26-40 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Data-Weighted Averaging

• Once every element in the array has been used, the cumulative error is zero. The errors induced by the use of each element are averaged out as soon as possible.

• Reference: R. Baird and T. Fiez, “Linearity Enhancement of Multibit ∆Σ A/D and D/A Converters Using Data Weighted Averaging,” Tran. on Circuits and SystemsÐII, pp. 753Ð762, 12/95.

Oversampling 26-41 Analog ICs; Jieh-Tsorng Wu Multi-Bit DAC — Noise-Shaped Scrambler

Swapper Cells Unit Elements

v(k) 3 Ao Therm. 2 Code Analog Output 1

• Each swapper tries to equalize the activity of each of its outputs. Each output from the scramble is a ﬁrst-order noise-shaped sequence.

• Reference: R. Adams, et al, “A 113dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling,” ISSCC, pp. 62Ð63, 2/98.

Oversampling 26-42 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC v

Element Selection Logic sy Vector su Quantizer

se min() H2 (z) − 1 sv sx

M de M Unit Elements Ao

Oversampling 26-43 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC

• The element selection logic (ESL) is a collection of M digital ∆Σ modulators, each

possessing a NTF(z) equal to H2(z), implemented with the error feedback structure and supplied with a common input.

• The vector quantizer uses information in the sy vector to select which v elements to enable. Want to minimize se = sv − sy.

• The sy = sx−min(sx)·[11 ···1] function is a shifting operation which set the minimum component in sy to zero. The purpose is to reduce the magnitude of sy vector, in a manner that does not disturb the noise-shaping property of the selection logic.

Oversampling 26-44 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC

= ··· Let de [e1,e2, ,eM] be the DAC error vector.

• By deﬁnition, de · [0]T = 0 and de · [1]T = 0, where [0] = [00 ···0] and [1] = [11 ···1].

• · + T = · T + · T de (sv1 sv2) de sv1 de sv2

T • de · svT + de · sv = 0

For the error-feedback structure, we have

= · + · SV(z) SU(z) [1] H2(z) SE(z)

Oversampling 26-45 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC

The vector quantizer obeys SV(z) · [1]T = V (z) The analog output is

= · + T Ao(z) SV(z) ([1] DE) = SV(z) · [1]T + SV(z) · DET = V (z) + SU(z) · [1] · DET + H (z) · SE(z) · DET 2 = + · T V (z) H2(z) SE(z) DE

Oversampling 26-46 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC — First-Order Example

= = − −1 M 4 H2(z) 1 z sv(k) = VQ[sy(k)] se(k) = sv(k) − sy(k) sx(k) = −se(k − 1)

k v(k) sy(k) sv(k) se(k) sx(k) 0 1 1, 1, 1, 1 1, 0, 0, 0 +0, −1, −1, −1 −0, +1, +1, +1 1 1 0, 1, 1, 1 0, 1, 0, 0 +0, +0, −1, −1 −0, −0, +1, +1 2 1 0, 0, 1, 1 0, 0, 1, 0 +0, +0, +0, −1 −0, −0, −0, +1 3 2 0, 0, 0, 1 1, 0, 0, 1 +1, +0, +0, +0 −1, −0, −0, −0 4 0 0, 1, 1, 1 0, 0, 0, 0 +0, −1, −1, −1 −0, +1, +1, +1 5 4 0, 1, 1, 1 1, 1, 1, 1 +1, +0, +0, +0 −1, −0, −0, −0 6 2 0, 1, 1, 1 0, 1, 1, 0 +0, +0, +0, −1 −0, −0, −0, +1

T • Since de · svT = −de · sv , we can add [1]tosy at any time.

• The ﬁrst-order algorithm is similar to the data-weighted averaging algorithm.

Oversampling 26-47 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC — Second-Order Example

= = − −1 2 M 4 H2(z) 1 z sv(k) = VQ[sy(k)] se(k) = sv(k) − sy(k) sx(k) = −2se(k − 1) + se(k − 2)

k v(k) sy(k) sv(k) se(k) sx(k) 0 1 1, 1, 1, 1 1, 0, 0, 0 +0, −1, −1, −1 −0, +2, +2, +2 1 1 0, 2, 2, 2 0, 1, 0, 0 +0, −1, −2, −2 −0, +1, +3, +3 2 1 0, 1, 3, 3 0, 0, 1, 0 +0, −1, −2, −3 −0, +1, +2, +4 3 2 0, 1, 2, 4 0, 0, 1, 1 +0, −1, −1, −3 −0, +1, +0, +3 4 0 0, 1, 0, 3 0, 0, 0, 0 +0, −1, +0, −3 −0, +1, −1, +3 5 4 1, 2, 0, 4 1, 1, 1, 1 +0, −1, +1, −3 −0, +1, −2, +3 6 2 2, 3, 0, 5 0, 1, 0, 1 −2, −2, +0, −4 +4, +3, +1, +5

Oversampling 26-48 Analog ICs; Jieh-Tsorng Wu General Mismatch-Shaping DAC — Second-Order Example

2 • = − −1 The element selection logic (ESL) is stable, i.e, se is bounded, for H2(z) 1 z , as long as v stays away from the extremes of its range.

• When a binary modulator is unstable with an NTF(z) equal to H2(z), the corresponding ESL algorithm must also be unstable.

• Adding dither to sy may be necessary to whiten the noise caused by a deterministic selection algorithm.

Oversampling 26-49 Analog ICs; Jieh-Tsorng Wu Multi-Bit Unit Elements

• If polarity reversal or repeated use of an unit element in one period is allowed, the components of sv need not be restricted to {0, 1}.

• Multi-bit can enhance the stability of the ESL in the same manner that multi-bit feedback enhances the stability of a regular ∆Σ modulator.

• The key circuit constraint is the need to ensure that each usage of an element results in the same error.

Oversampling 26-50 Analog ICs; Jieh-Tsorng Wu Decimation and Interpolation

Decimation Interpolation x(n) w(n) y(m) x(n) w(m) y(m)

h(n) M L h(n)

f s f s f s /M f s Lff s L s X ejω X ejω

ω ω 0 π 2π 0 π 2π W ejω W ejω

ω ω 0 π 2π 0 π 2π 2π /M /L /L Y ejω Y ejω

ω ω 0 π 2π 2M π 0 π/L 2π

Oversampling 26-51 Analog ICs; Jieh-Tsorng Wu Decimation and Interpolation

∞ Decimation Filter = y(m) = h(k)x(Mm − k) k=−∞ ∞ Interpolation Filter = y(m) = h(m − kL)x(k) k=−∞

• The processes of decimation and interpolation are in eﬀect duals.

• A ﬁlter deﬁned for one process can often be used for other if the same parameters are used.

• An architecture that is efficiently defined for one process can often be transposed for used as an efficient architecture in the dual process.

Oversampling 26-52 Analog ICs; Jieh-Tsorng Wu Multi-Stage Rate Conversion

x(n) y(m) LPF 64 2822.4 kHz N 44.1 kHz

1+ δ1 1− δ1

kHz δ 20 22.05 1411.2 2 ω 0 ω p ω s π

x(n) y(m) LPF LPF 32 2 2822.4 kHzN1 88.2 kHz N2 44.1 kHz

44.1 kHz kHz 20 66.15 1411.2 20 22.05

Oversampling 26-53 Analog ICs; Jieh-Tsorng Wu Multi-Stage Rate Conversion

• The order N of an equiripple FIR ﬁlter is

f (δ ,δ ) − g(δ ,δ )(∆ω)2 −10 log (δ δ ) − 13 N ≈ 1 2 1 2 ≈ 10 1 2 ∆ω 14.6∆ω = 2 + − − 2 + + f (δ1,δ2) (0.005309x1 0.07114x1 0.4761)x2 (0.00266x1 0.5941x1 0.4278) = + − g(δ1,δ2) 11.012 0.51244(x1 x2) − ωs ωp ∆ω = x = log δ x = log δ 2π 1 10 1 2 10 2

• = = = For the single-stage design, δ1 0.001, δ2 0.00001, then N 6250. For the = = = = two-stage design, δ1 0.001/2, δ2 0.00001, then N1 291 and N2 205.

• Practical considerations sometimes lead to the conclusion that a two-stage design is best.

• For most cases, the choice of 2 : 1 for the last stage is both the theoretically best option as well as the most practical one.

Oversampling 26-54 Analog ICs; Jieh-Tsorng Wu sinck Filters

1 2 M−1 x(n) 1 1 1 z z z f s y(m) M f s /M sinc 1

ω 0 2π/M 4π/M 8π/M π

x(n) sinc sinc sinc y(m) M f s 1 2k f s /M

x(n) y(m) f f /M s M s 1 1 M M z z z z

x(n) y(m) f s M 1 1 1 1 f /M z z z z s

Oversampling 26-55 Analog ICs; Jieh-Tsorng Wu sinck Filters

The sinc ﬁlter transfer function is

M −1 −M 1 1 1 − z H (z) = z−1 = 1 M M 1 − z−1 i=0 sin(ωM/2) sinc(ωM/2) sin(x) jω = 1 · = = H1 e sinc(x) M sin(ω/2) sinc(ω/2) x

The sinck ﬁlter transfer function is −M k k 1 1 − z 1 1 k H(z) = [H (z)]k = = · · 1 − z−M 1 Mk 1 − z−1 Mk 1 − z−1

• The integrator-diﬀerentiator architecture is inherently stable, when 2’s-complement arithmetic is used due to its wrap-around characteristic.

Oversampling 26-56 Analog ICs; Jieh-Tsorng Wu Phase-Locked Loops

Jieh-Tsorng Wu

July 16, 2002

E S A National Chiao-Tung University

1896 Department of Electronics Engineering Phase-Locked Loops (PLLs)

VFO Vc Ai Phase Loop Ao Detector Filter

= + = + = + · Ai g1 (ωi t θi ) Ao g2 (ωot θo) ωo ωoo Kc Vc

• g1 and g2 are periodic functions with 2π period.

• When the loop is locked, the frequency of the VCO is exactly equal to the average frequency of the input.

• The loop filter is a low-pass filter that suppresses high-frequency signal components in the phase difference.

PLLs 27-2 Analog ICs; Jieh-Tsorng Wu Phase-Locked Loops (PLLs)

Applications:

• Automatic frequency control.

• Frequency and phase demodulation.

• Data and clock recovery.

• Frequency synthesis.

References:

• Roland E. Best, “Phase-Locked Loops,”, 2nd Edition, McGraw-Hill, Inc., 1993.

• Dan H. Wolaver, “Phase-Locked Loop Circuit Design,” Prentice-Hall, Inc., 1991.

• Floyd M. Gardner, “Phaselock Techniques,” 2nd Edition, John Wiley & Sons, 1979.

PLLs 27-3 Analog ICs; Jieh-Tsorng Wu Basic Model

= − = + × Vd Kd (θi θo) ωo ωoo Ko Vc V V θ d c i F(s) θ PD Ko/s o

Phase Filter VFO Detector

When the PLL is locked,

= · − = = − Vd (s) Kd [θi (s) θo(s)] Kd θe(s) θe θi θo V (s) = F (s) · V (s) c d K ω dt = ω t + K V dt = ω t + θ ⇒ θ (s) = V (s) · o o oo o c oo o o c s

• θe is the phase error, Kd is the phase-detector gain factor, and Ko is the VCO gain factor.

PLLs 27-4 Analog ICs; Jieh-Tsorng Wu Basic Model

System equations are

K V = K · (θ − θ ) = K · θ V = F (s) · V θ = V · o d d i o d e c d o c s

The transfer functions are

θ K K F (s) o = o d = H(s) + θi s KoKd F (s) θ s e = = 1 − H(s) + θi s KoKd F (s) V sK F (s) s c = d = · H(s) + θi s KoKd F (s) Ko ∆ω V ⇒ = o = · c = − = − H(s) Ko ∆ωi ωi ωoo ∆ωo ωo ωoo ∆ωi ∆ωi

• H(s) is the closed-loop transfer function.

PLLs 27-5 Analog ICs; Jieh-Tsorng Wu Second-Order PLL — Active Lag-Lead Filter

R2 C

sτ + 1 R1 F (s) = − 2 sτ Vi Vo 1 = τ1 R1C = τ2 R2C

2ζω s + ω2 K K ω = n n = o d = n · H(s) ωn ζ τ2 2 + + 2 τ 2 s 2ζωns ωn 1

• ωn is the pole frequency of the loop.

• = ζ is the damping factor. Qp 1/(2ζ) is the pole quality factor.

PLLs 27-6 Analog ICs; Jieh-Tsorng Wu Second-Order PLL — Passive Lag-Lead Filter

R1 Vi Vo sτ + 1 F (s) = 2 sτ + 1 R2 1 = + τ1 (R1 R2)C C = τ2 R2C

− 2 + 2 s 2ζωn ωn/(KoKd ) ωn K K ω = = o d = n + 1 H(s) ωn ζ τ2 2 + + 2 τ 2 K K s 2ζωns ωn 1 o d

• = If R2 0, then ω ω2 = 1 = 1 = = n = n τ1 ωn KoKd ωLF ζ H(s) R C ω 2K K 2 + + 2 1 LF o d s 2ζωns ωn

PLLs 27-7 Analog ICs; Jieh-Tsorng Wu High-Gain Second-Order PLL Frequency Response

If KoKd τ2 1 in the passive ﬁlter, then

2ζω s + ω2 ≈ = n n Hpassive(s) Hactive(s) 2 + + 2 s 2ζωns ωn

And the −3 dB bandwidth of H(s)is 1/2 = 2 + + 2 + 2 + ω−3dB ωn 2ζ 1 (2ζ 1) 1

• Usually choose ωn <ωi /10 to remove the high-frequency components at ωi ,2ωi , . . . , existing in the phase detector’s output.

• The PD output’s high-frequency components can show up as spurious tones in the frequency spectrum of the PLL’s output.

PLLs 27-8 Analog ICs; Jieh-Tsorng Wu High-Gain Second-Order PLL Frequency Response

10 ζ = 5.0 5 ζ = 2.0 0

-5 ω ζ = 0.3

-10 | H ( j ) | (dB) | H ( ζ = 0.5

-15 ζ = 0.707

-20 0.1 1 10

Frequency (ω/ωn)

PLLs 27-9 Analog ICs; Jieh-Tsorng Wu Step Response of a Two-Pole System

Consider the following two-pole transfer function

ω2 = n = = − ± 2 − H(s) Poles s1,2 ζ ζ 1 ωn 2 + + 2 s 2ζωns ωn

• If ζ>1, the system is overdamped, and both poles are real. 1 1 − 1 − Step Response = 1 − e k1ωnt − e k2ωnt 2 ζ 2 − 1 k1 k2 = − 2 − = + 2 − k1 ζ ζ 1 k2 ζ ζ 1

• = − If ζ 1, the system is critically damped, and both poles are at ωn.

− − = − + ωnt ≈ − ωnt/(2ζ) 2 Step Response 1 (1 ωnt)e 1 e if 4ζ 1

PLLs 27-10 Analog ICs; Jieh-Tsorng Wu Step Response of a Two-Pole System

• If ζ<1, the system is underdamped. ζωn − Step Response = 1 − · sin ω t + cos ω t e ζωnt ω = 1 − ζ 2 · ω ω d d d n d √ 2 % Overshoot = 100e−π/ 1/ζ −1

Overshoot

Step Response Error Band

t √ • For PLL, choose ζ>1/ 2 = 0.707 to avoid excessive ringing.

PLLs 27-11 Analog ICs; Jieh-Tsorng Wu Phase Jitter

Probability Density

V N nt

θn θn

2 2 n 1 −θ /(2σ ) Vs c pdf = √ e n n 2πσn = + = + v(t) s(t) n(t) Vs sin(2πfot) n(t) = + n(t) nc(t) sin(2πfot) nt(t) cos(2πfot)

The phase jitter is n (t) n (t) θ (t) = tan t ≈ t n + Vs nc(t) Vs

PLLs 27-12 Analog ICs; Jieh-Tsorng Wu Phase Jitter

Assume that 1 1 n2 = · n2 + · n2 n2 = n2 2 c 2 t c t Then, we have 2 n n2 1 1 σ2 = θ2 = t = = · n n 2 2 2 SNR Vs Vs

• SNR is the signal-to-noise ratio, and can be expressed as

V 2/2 SNR ≡ s n2

PLLs 27-13 Analog ICs; Jieh-Tsorng Wu Phase Noise

Power Ps Spectral Density

L (fm)

Pssb

Freq fo

= + v(t) Vs sin [2πfot θn(t)]

PLLs 27-14 Analog ICs; Jieh-Tsorng Wu Phase Noise

• L The phase noise (fm), usually in dBc, is the ratio of the single-sideband (SSB) power in a 1-Hz bandwidth fm Hz away from the carrier to the total signal power, i.e.,

P L ≡ s (fm) Pssb

• Let S (f ) be the power spectral density of θ (t) in frequency domain, it can be shown θn n that ∞ S (f ) ≈ 2L(f ) and θ2 = S (f )df θn m m n θn 0

PLLs 27-15 Analog ICs; Jieh-Tsorng Wu PLL Noise Response

n θn,i vc θn,vf o

θi Kd F(s) Ko/s θo

Let θn,o be the phase noise in θo,wehave

S 2 θn,o KoKd F (s) 2 = = |H(jω)| S s + K K F (s) θn,i o d s=jω

S 2 θn,o s 2 = = |1 − H(jω)| S s + K K F (s) θn,vf o o d s=jω

2 2 Sθ K K n,o = o = [1 − H(jω)] · o + Sn s K K F (s) = jω vc o d s jω

PLLs 27-16 Analog ICs; Jieh-Tsorng Wu PLL Noise Response

Consider only a white noise S (f )inθ , θn,i i

∞ θ2 = S (f )|H(j2πf )|2df = S (f ) × B n,o θn,i θn,i L 0

BL is the noise bandwidth of H(j2πf ), i.e.,

∞ ≡ | |2 BL H(j2πf ) df 0

For the 2nd-order PLL with active lag-lead ﬁlter 1 1 B = ω ζ + L 2 n 4ζ

• = BL,min occurs at ζ 0.5.

• BL < 1.25BL,min for 0.25 <ζ<1.0.

PLLs 27-17 Analog ICs; Jieh-Tsorng Wu Phase Detection Using Analog Multiplier

V2 Vd

−1π 3 2 2π 2π θe −2π −3 1 2π 2π -π π

= + = + V1(t) V1 sin(ωt θ1) V2(t) V2 cos(ωt θ2) 1 V (t) = kV (t)V (t) = kV V [sin(θ − θ ) + sin(2ω + θ + θ )] d 1 2 2 1 2 1 2 1 2

PLLs 27-18 Analog ICs; Jieh-Tsorng Wu Phase Detection Using Analog Multiplier

The 2ω component will be ﬁltered out by the loop ﬁlter, hence consider the dc component only 1 V = kV V sin(θ − θ ) = K · sin(θ ) θ = θ − θ d 2 1 2 1 2 d e e 1 2

• Kd is the phase-detector gain factor, and θe is the phase error.

• ≈ If θe 1, vd Kd θe.

• ◦ = V1(t) and V2(t) are 90 out of phase when θe 0.

PLLs 27-19 Analog ICs; Jieh-Tsorng Wu PLL Tracking Performance — Hold-In Range

From the ﬁnal value theorem

s2θ (s) = = i lim θe(t) lim sθe(s) lim t→∞ → → + s 0 s 0 s KoKd F (s)

The hold-in range, ∆ωH, is the frequency range in which a PLL can maintain lock statically.

∆ω = + = · = 2 ⇒ = H ωi ωo ∆ωH θi (t) ∆ωH tθi (s) ∆ωH/s lim θe(t) t→∞ KoKd F (0)

• For a sinusoidal PD, the criterion becomes

∆ω = H ⇒ = lim sin θe(t) < 1 ∆ωH KoKd F (0) t→∞ KoKd F (0)

→∞ →∞ For a 2nd-order PLL with active ﬁlter, F (0) , thus ∆ωH .

PLLs 27-20 Analog ICs; Jieh-Tsorng Wu PLL Tracking Performance — Pull-Out Range

The pull-out range ∆ωPO is the frequency-step limit below which the PLL does not skip cycles but remains in lock.

• For a sinusoidal PD

= + ∆ωPO 1.8ωn(ζ 1) for 0.5 <ζ<1.4

PLLs 27-21 Analog ICs; Jieh-Tsorng Wu Noisy PLL Tracking Performance

Deﬁne the SNR of a PLL as ≡ 1 SNRL 2 2θn,o

• As a rule of thumb, SNRL > 6 dB is required for stable operation.

For low SNRL, the VFO phase occasionally slips one or more cycles as compared to the input. Deﬁne TAV as the average time between cycle slips.

• For a 1st-order loop T ≈ π e4SNRL, where B is the PLL noise bandwidth. AV 4BL L

• For a 2nd-order loop with ζ = 0.707 T ≈ 1 eπSNRL. AV BL

• The slips of a 1st-order loop are almost always single, isolated events.

• The slips in a 2nd-order loop tend to bunch in bursts.

PLLs 27-22 Analog ICs; Jieh-Tsorng Wu PLL Acquisition Behavior Loop Filter VFO Vi Phase F(s) Vo Detector

• The process of bringing a PLL into lock is called acquisition.

• Acquisition is inherently a nonlinear phenomenon.

• An nth-order PLL contains n integrators (VFO, capacitors, . . . ). With each integrator there is associated a state variable of the loop: phase, frequency, frequency rate, and so on. To force the loop into lock, it is necessary to bring each of the state variables close to the corresponding parameters of the input signal. Therefore, we should speak of phase acquisition, frequency acquisition, and so forth.

PLLs 27-23 Analog ICs; Jieh-Tsorng Wu Phase Acquisition of a First-Order Loop

ú θe ∆ω − sin θe VCO KoKd KoKd Vd Vi Phase Vo Detector

θe

= · = + · = − Vd Kd sin θe ωo ωoo Ko Vd θe θi θo t = − = − − − θe θi θo ωi t ωoot KoKd sin θedt θo(0) 0 dθ ⇒ e = θú = ∆ω − K K sin θ ∆ω = ω − ω dt e o d e i oo

• ú = The loop is locked when θe 0.

• There is no cycle skipping in the acquisition process.

PLLs 27-24 Analog ICs; Jieh-Tsorng Wu Phase Acquisition of a Second-Order Loop

The lock-in range, ∆ωL, is the frequency range over which the PLL can acquire lock without cycle slipping.

log |F (jf)|

By practical considerations, the lock- in process of a higher-order loop is so fast that it can be approximated by the phase acquisition process of a 1st- τ F (∞) = 2 = ∞ τ1 order loop with gain K KoKd F ( ). log f

• For a PLL with with sinusoidal PD,

= ≈ ∞ = = ≈ 1 Lock-In Range ∆ωL KoKd F ( ) 2ζωn Lock-In Time TL ωn

PLLs 27-25 Analog ICs; Jieh-Tsorng Wu Frequency Acquisition — The Pull-In Process

ωi

The pull-in range, ∆ωP ,isthe maximum initial frequency ωo ∆ω oﬀset for the pull-in process to occur.

Tp • For a 2nd-order PLL, 8 8 Pull-In Range = ∆ω ≈ ζω K K − ω2 ≈ ζω K K if K K ω P π n o d n π n o d o d n ∆ω2 Pull-In Time = T ≈ p 3 2ζωn

PLLs 27-26 Analog ICs; Jieh-Tsorng Wu Aided Frequency Acquisition — Frequency Sweeping

Vi Phase Loop Detector Filter

VFO

Lock Sweep Detector Generator

• Use sweep to bring the VFO close to the frequency of locking.

PLLs 27-27 Analog ICs; Jieh-Tsorng Wu Aided Frequency Acquisition — Loop Filter Switching

Low R

Vi Phase Detector High R VFO Loop Filter

Lock Detector Low R if unlocked; High R if locked

• The frequency pull-in can be painfully slow in a narrowband loop. Sometimes, a wider loop bandwidth is preferred.

PLLs 27-28 Analog ICs; Jieh-Tsorng Wu Aided Frequency Acquisition — Dual Loops

VLPi Phase Detector Filter 1

VFO

Frequency LP Detector Filter 2

• Contains a phase-locked loop (PLL) and a frequency-locked loop (FLL).

• The FLL should dominate during frequency acquisition.

• The PLL should dominant when the phase is locked.

PLLs 27-29 Analog ICs; Jieh-Tsorng Wu Digital Phase-Locked Loops (DPLLs) Loop Filter V V V d c i PD F(s) Vo VFO

1/N

Frequency Divider

To calculate loop dynamics, combine the VFO and the frequency divider as a new VFO.

ω ω K ω = ω + K · V ⇒ ω = = oo + o · V = ω + K · V o oo o d o N N N d oo o d ω K θ ω = oo K = o θ = o oo N o N o N • θi and θo are not available except during the rising and falling transitions.

PLLs 27-30 Analog ICs; Jieh-Tsorng Wu XOR Phase Detector

u1 u1 Q u2 u2 Q

u1 Averaged Q u2 Q

θe u2 −π −π 0 π π 2 2 Q

• The PD characteristic is strongly dependent on the duty-cycle of u1 and u2.

PLLs 27-31 Analog ICs; Jieh-Tsorng Wu Edge-Triggered Set-Reset Phase Detector

u1 u1 S Q u2 u2 R Q

Averaged Q u1

u2 Q

u1 θe −2π −π 0 π 2π u2 Q

Frequency Discrimination Capability

u1 u1

u2 u2 Q Q

PLLs 27-32 Analog ICs; Jieh-Tsorng Wu Edge-Triggered Set-Reset Phase Detector

• The PD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.

• If f1 f2 or f1 f2, the PD has frequency discrimination capability, which can improve frequency acquisition speed of the PLL.

• ≈ However, when f1 f2, the frequency-sensitive behavior is lost, and the PLL relys on the pull-in process for frequency acquisition.

PLLs 27-33 Analog ICs; Jieh-Tsorng Wu Sequential Phase-Frequency Detector (PFD)

u1 u1 1 D Q UP u2 R UP

R DN 1 DQ DN

u2 u1

u2 Averaged (UP-DW) UP

θe

−2π −π 0 π 2π

PLLs 27-34 Analog ICs; Jieh-Tsorng Wu Sequential Phase-Frequency Detector (PFD)

• The PFD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.

• ﬀ − The PFD can discriminate the frequency di erence for even the smallest f1 f2.

• A PLL with the PFD can have inﬁnite pull-in range. The frequency acquisition aid provided by the PFD is akin to frequency sweeping.

• When using the PFD, a missing transition or an extra one in either u1 or u2 can cause a large error signal to appear. The eﬀects will propagate for more than one cycle. Great caution is required to use the PFD in a noisy environment.

PLLs 27-35 Analog ICs; Jieh-Tsorng Wu Charge-Pump Phase-Locked Loops

IP PFD

Vi u1 UP Ie VFO Vc Vo u2 DN R C IP

= | | The “on” time of either UP or DN is tp θe /ωi for each period 1/fi of the input signal. The average error current Ie over a cycle is

t θ = × p = × e = = 2π Ie IP IP ωi 2πfi Ti 2π Ti

PLLs 27-36 Analog ICs; Jieh-Tsorng Wu Charge-Pump Phase-Locked Loops

The voltage Vc can be expressed as 1 I 1 V (s) = I (s) R + = θ (s) × P R + c e sC e 2π sC V (s) I c = = P + 1 Kd F (s) R θe(s) 2π sC The VFO has the following characteristic:

K ω = ω + K · V ⇔ f = f + K · V K = o o oo o c o oo o c o 2π Using the continuous-time approximation, we have

θ (s) 2 θ (s) e = = s o = = − He(s) H(s) 1 He(s) θ (s) 2 + + 2 θ (s) i s 2ζωns ωn i 1/2 I 1 1/2 ω = K × P ζ = K × (I R) × (RC) n o C 2 o P

PLLs 27-37 Analog ICs; Jieh-Tsorng Wu Charge-Pump Phase-Locked Loops

• The PLL behaves as a 2nd-order loop with active lag-lead ﬁlter.

• Discrete-time model can be used for more accurate analysis. Reference: Hein, z- Domain Model for Discrete-Time PLLs, Trans. CAS, 11/88, pp. 1393Ð1400.

• During the pump interval tp, a voltage step of IP R occurs at the VFO input. This granularity eﬀect may be intolerable in some systems.

• The voltage step IP R may overload the VFO, making the previous linear analysis invalid.

• ﬀ The granularity e ect can be mitigated with an additional capacitor Cp in parallel with the earlier RC network, thus forming a 3rd-order PLL.

• Reference: Floyd Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Commun., Nov. 1980, pp. 1849Ð1858.

PLLs 27-38 Analog ICs; Jieh-Tsorng Wu PFD and Charge-Pump Filter

I u1 P1 ∆Vc UP 1 D Q S1 R Vc θe R C Dead Zone 1 DQ S2 DN u2 IP2

• The dead zone is caused by the slowness of the S1 and S2 switches.

PLLs 27-39 Analog ICs; Jieh-Tsorng Wu PFD and Charge-Pump Filter

• When θe falls in the dead zone, the PFD’s conversion gain is decreased, causing a reduction in ωn and ζ, and the degradation of θo phase noise.

• The dead zone can be eliminated by allowing UP and DN to be activated simultaneously for a short time even if the phase diﬀerence is zero. Then, any ﬀ mismatch between IP 1 and IP 2 can cause a phase o set and consequently spurs in the output spectrum.

• The ﬁnite output impedance of the IP 1 and IP 2 current sources can also cause phase oﬀset.

• Charge sharing in the S1 and S2 switches can also cause glitches at Vc.

PLLs 27-40 Analog ICs; Jieh-Tsorng Wu PFD with Delayed Reset

Delay

PLLs 27-41 Analog ICs; Jieh-Tsorng Wu Third-Order Charge-Pump PLLs

| | IP L(jω) (dB)

UP Ie Vc

ωt ωp DN 0 ω R1 C2 ωz C1 IP

The loop ﬁlter transfer function is V (s) I 1 1 I sR C + 1 c = K F (s) = P R + = P × 1 1 d 1 + + θe(s) 2π sC1 sC2 2πs(C1 C2) sR1(C1 C2) 1 1 1 ω = ω = z p R1C1 R1(C1 C2)

PLLs 27-42 Analog ICs; Jieh-Tsorng Wu Third-Order Charge-Pump PLLs

The loop gain of the 3-order PLL is

K K I s/ω + 1 L(s) = o × K F (s) = o P × z s d 2 + + s (C1 C2) s/ωp 1

= = Let ωt/ωz α>1 and ωp/ωt β>1, then

K I C ω ≈ o P = K · I R · 1 t + o P 1 + (C1 C2)ωz C1 C2 1 α 1 R = · ω C = K I · C = K I · 1 K I t 1 o P 2 2 o P · 2 o P ωt β ωt

◦ • α = 4 and β = 4 gives a phase margin ≈ 60 .

PLLs 27-43 Analog ICs; Jieh-Tsorng Wu Multi-Path Charge-Pump Filter

Ie1 V c V a

V c V b Ie2 V a

V b ω Rb Cb ωz ωt ωp

θ θ I = I × e I = I × e e1 P 1 2π e1 P 2 2π

PLLs 27-44 Analog ICs; Jieh-Tsorng Wu Multi-Path Charge-Pump Filter

The loop ﬁlter transfer function is sR C + C · IP 2 + 1 V (s) I 1 I 1 I b b a IP 1 c = K F (s) = P 1 · + P 2 R = P 1 × θ (s) d 2π C 2π b sC 2πsC sR C + 1 e a b a b b I I 1 = + · P 2 ≈ · P 2 1 = Rb Cb Ca RbCa RbCb ωz IP 1 IP 1 ωp

The loop’s unity-gain frequency is

K I ≈ o P 1 = · ωt Ko IP 2Rb Caωz

• ωz, ωp, and ωt, can be set using smaller capacitors and resistors.

• Reference: J. Craninckx and M. Steyaert, A Fully Integrated CMOS DCS-1800 Frequency Synthesizer, JSSC, 12/98, pp. 2054Ð2065.

PLLs 27-45 Analog ICs; Jieh-Tsorng Wu