A Circuit-Based Approach for the Compensation of Self-Heating-Induced
Errors in Bipolar Integrated-Circuit Comparators
by
KYLE WEBB
A.B., Dartmouth College, 1997
B.E., Thayer School of Engineering, Dartmouth College, 1998
M.S., Oregon State University, 2005
A dissertation submitted to the Graduate Faculty of the
University of Colorado Colorado Springs
in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy
Department of Electrical and Computer Engineering
2013
ii
© Copyright By Kyle Webb 2013 All Rights Reserved iii
This dissertation for the Doctor of Philosophy degree by
Kyle Webb
has been approved for the
Department of Electrical and Computer Engineering
By
T.S. Kalkur, Chair
Andrew Ketsdever
Anatoliy Pinchuk
Heather Song
Charlie Wang
Date iv
ABSTRACT
Webb, Kyle (Ph.D., Engineering)
A Circuit-Based Approach for the Compensation of Self-Heating-Induced Errors in Bipolar
Integrated-Circuit Comparators
Dissertation directed by Professor T.S. Kalkur
Voltage comparator circuits are common integrated circuit (IC) building blocks found in
ICs used in a variety of applications, including test and measurement instruments, wireline communication systems, and data converters. High-performance comparators are often fabricated in high-bandwidth bipolar processes, which are typically very susceptible to the effects of self- heating. Self-heating in comparator circuits manifests itself as signal-dependent propagation delay variation, which appears at the comparator output as data-dependent jitter. For comparators used in applications where precise timing measurements of threshold crossings are sought, self- heating is an issue that must be addressed.
A circuit-based self-heating compensation scheme applicable to asynchronous comparator circuits has been designed, simulated, and implemented on a test chip fabricated in
IBM’s BiCMOS8HP SiGe HBT IC process. This compensation scheme differs from prior work addressing self-heating-induced errors in comparator circuits, in that it is applicable to asynchronous, i.e., non-clocked, comparator circuits. It also represents an improvement over simpler compensation schemes commonly applied to non-clocked comparators, in that it is insensitive to input signal swing and common-mode variation. The central element of the self- heating compensation circuitry is a power-to-voltage converter (PVC) circuit that enables the generation of a feedback signal to provide self-heating compensation.
Initial measurements of the test chip indicated that the comparator was over-compensated for the effects of self-heating. It is suspected that the excess compensation is due to differential v
thermal resistance mismatch between the amplifier transistors being compensated and those in the compensation circuitry. It is believed that the thermal resistance mismatch is due to the effects of different metal-layer interconnects for the two pairs of transistors. A work-around was identified to reduce compensation path gain below its minimum designed-for value, allowing the self- heating compensation circuitry to be calibrated, even in the presence of the unexpected thermal resistance mismatch. Measurements of the comparator, both with the compensation circuitry enabled and with it disabled, showed that the self-heating compensation circuitry presented here provides effective compensation of self-heating-induced timing errors over a wide range of input signal conditions.
vi
ACKNOWLEDGEMENTS
I am extremely grateful to the MOSIS Service for funding the fabrication of the test chip for this research through a MOSIS Educational Program Research grant. I would also like to thank Agilent Technologies in Colorado Springs for use of the test equipment for the characterization of the test chip. Thanks also to Jeff Riggs and Robert Greene at Spectrum
LASER in Colorado Springs for their help with the mounting of the test chip onto the printed circuit board.
Thanks also to Francisco Torres-Reyes and Sean Staples in the EAS IT department for their endless help keeping the Cadence toolset up and running. Finally, I’d like to thank my advisor, Professor T.S. Kalkur, as well as the College of Engineering and Applied Science, for their support of this research.
vii
TABLE OF CONTENTS
ABSTRACT ...... iv
ACKNOWLEDGEMENTS ...... vi
CHAPTER 1 ...... 1
Introduction and Motivation ...... 1
Comparators ...... 1
Self-Heating ...... 3
Contributions of this Research ...... 4
Organization of this Dissertation Proposal ...... 5
CHAPTER 2 ...... 7
Self-Heating ...... 7
Modeling Self-Heating Effects ...... 7
Accounting for Self-Heating in Simulation ...... 13
Compensating for Self-Heating Effects ...... 14
CHAPTER 3 ...... 16
Self-Heating Effects and Compensation in Analog Circuits ...... 16
Self-Heating in Linear Differential Pair Amplifiers ...... 16
Compensation of Self-Heating Effects in Linear Amplifiers ...... 23
CHAPTER 4 ...... 30
Self-Heating Effects and Compensation in Digital Circuits ...... 30
Self-Heating in Digital Differential Pair Amplifiers ...... 30
Compensation of Self-Heating Effects in Digital Circuits ...... 36
Assessing Self-Heating Effects and Compensation in Digital Circuits ...... 37 viii
CHAPTER 5 ...... 43
Self-Heating Effects and Compensation in Comparators ...... 43
Compensation of Self-Heating Effects in Comparators ...... 45
Prior Works Addressing Self-Heating in Comparators ...... 46
Feedback of a Self-Heating Compensation Signal ...... 49
Assessing the Effectiveness of Comparator Self-Heating Compensation ...... 56
CHAPTER 6 ...... 57
Test Chip Circuit Design...... 57
Top-Level Comparator Design ...... 58
Input Amplifier ...... 59
Output Amplifier ...... 61
Comparator Core ...... 62
Self-Heating Compensation Circuitry ...... 63
Calibration Procedure ...... 76
Power Supplies ...... 78
Layout ...... 80
Package ...... 83
CHAPTER 7 ...... 84
Simulation Results ...... 84
BiCMOS8HP HBT Self-Heating Model ...... 85
Simulation Setup ...... 86
Simulation Suite ...... 91
Simulation Results ...... 93
Simulations Accounting for Process Variation and Mismatch ...... 98 ix
CHAPTER 8 ...... 104
Measurement Results ...... 104
Measurement Setup ...... 104
Uncompensated Comparator ...... 108
Compensated Comparator – Initial Measurements ...... 111
Compensated Comparator – Reduced Gain ...... 116
CHAPTER 9 ...... 123
Conclusion and Future Work ...... 123
Future Work ...... 124
REFERENCES ...... 126
APPENDIX ...... 132
Circuit Schematics ...... 132
TopLevel ...... 132
Core ...... 133
FullComp ...... 134
VCSgen ...... 134
InputAmp50ohm ...... 135
CbInputAmp...... 136
InputOffsetNull ...... 136
InputAmpVCSgen ...... 137
Comp ...... 138
ThermCompTailSource ...... 139
PVC ...... 139
PVCmult...... 140 x
PVCamp ...... 141
VCSgenVthermNull ...... 142
VthermNull ...... 143
ThermCompEnable ...... 143
VthermVTA ...... 144
VthermVTAfixed ...... 145
VthermVTAvariable ...... 146
VthermCalCtrl ...... 146
VthermVTAgmFixed ...... 147
VthermVTAgmVariable ...... 148
HystVCSgen...... 149
OutputAmp50ohm ...... 150
LinAmp ...... 151
DiffPairAmp...... 152
IoPadEsd ...... 153
IoPadEsdCDM ...... 153
GndPadEsd ...... 154
VccPadEsd ...... 154
VeePadEsd ...... 155
EsdRCclamp...... 155
SupplyBypass ...... 156
CHAPTER 1
INTRODUCTION AND MOTIVATION
Integrated circuit (IC) voltage comparators are common building blocks in a wide variety of mixed-signal ICs and systems. Comparator circuits are used in applications such as test and measurement, data conversion, and communications. In many of these applications, performance can be improved by maintaining a stable timing delay relationship between input and output signals of the comparators. Self-heating of comparator transistors is one mechanism that works against stable comparator propagation delays. The research described here seeks to improve the performance of comparators used for a wide range of applications by providing a circuit-based approach for the compensation of self-heating effects in integrated circuit comparators.
Comparators
The function of a voltage comparator circuit is to generate a digital high or low output voltage based on the relative values of two input voltages. The two input voltages may be an AC signal and a, possibly adjustable, DC threshold voltage, or they may be the two phases of a differential signal. In the former case, the comparator output assumes one state – high or low – if the input signal is below the threshold voltage, and assumes the other state if the input signal is above the threshold voltage. In the latter case, the comparator output switches states when the differential input signal changes polarities. An adjustable threshold voltage can be accommodated in the latter case by adding DC offset to a differential input signal upstream from the comparator 2
input. A comparator, along with a differential input signal and its corresponding output signal, are illustrated schematically in Figure 1.1.
A comparator circuit compares the relative voltage on each of its inputs, or equivalently it detects the polarity, or sign, of its differential input signal. Mathematically, the comparator function can be represented as
(1.1) sgn
Figure 1.1. Schematic representation of a comparator, along with a representative input and output signal.
Comparators may be used to discern two related pieces of information regarding an input signal. First, the comparator determines whether an input signal is above or below a certain threshold voltage. Secondly, in many applications, comparators are used to precisely determine the timing of threshold voltage crossings by the input signal. Variation in the timing relationship between input signal threshold crossing and comparator output signal transition due to, for example, the nature of the input signal, noise, or interference will appear as jitter, inter-symbol interference (ISI), or duty-cycle distortion (DCD) at the comparator output. Comparators find use in a wide variety of circuits and systems, many of which require a very precise timing relationship between input threshold crossings and output transitions. It is the stability of this input-to-output timing relationship of comparator circuits that is the focus of this work.
Comparators find widespread use in data conversion circuits. Analog-to-digital converter
(ADC) ICs may contain hundreds of comparators. When used in high-speed data acquisition applications, ADCs are sensitive to sampling-time uncertainty, or jitter. Sampling jitter may result from many sources such as sample clock jitter, noise, or interference. Another source of sampling 3
jitter in ADCs is variation in delay through the comparators on the ADC, arising due to thermal differentials between the transistors that comprise the comparators as a result of self-heating of those devices. Sampling jitter due to variation in comparator propagation delay directly affects the effective number of bits (ENOB) of a converter, and may ultimately limit its maximum useable sample rate.
High-sample-rate ADCs are used extensively in electronic test and measurement instruments, such as oscilloscopes, high-speed digitizers, and logic analyzers. In these applications it is often necessary to time-align the acquired samples with some trigger event, such as the crossing of a voltage threshold, or trigger level, by the input signal. Such trigger events are typically detected by high-speed comparators. The propagation delay through these trigger comparators must be stable, or timing error in the sampled data will result. Logic analyzers use comparators as one-bit ADCs to digitize input signals. Any variation in delay through these comparators will result in timing errors in the acquired data.
Comparators or very similar circuits are also widely used in the transceiver circuits of high-bandwidth wireline serial communication links. The bandwidth of these links is typically limited by signal integrity issues related to the physical channel. Additional timing uncertainty due to variation in delay through comparators in the transceivers would further degrade the timing margin of the serial link, unacceptably reducing the useable bandwidth of the channel.
Self-Heating
Self-heating is a phenomenon in which the temperature of an electronic component is affected by the signal applied to or being amplified by that device. The temperature of a component will, in general, be a function of the power dissipated by that device. If a device’s power dissipation is a function of the signal applied to that device, then its temperature will be signal-dependent as well. For devices, such as transistors, whose parameters are temperature- dependent, self-heating can result in signal-dependent device characteristics. In the context of 4
nominally-matched transistors on an IC, signal-dependent mismatches can arise between devices due to the thermal differentials that result from self-heating.
Self-heating-induced mismatches may result in signal-dependent errors in the circuit output. The nature of these errors depends on the type of circuit affected by self-heating; they may be gain errors or timing errors depending on whether the circuit is analog, digital, or mixed- signal. For some applications, the errors introduced due to self-heating result in unacceptable performance degradation, and must be compensated for. There are many different methods that can be employed for the compensation of self-heating effects. Just as the effects of self-heating differ between analog and digital circuits, so too do the methods used to compensate for these effects. Though not well-documented, compensation of self-heating effects in purely analog or purely digital circuits is fairly straight-forward.
Self-heating compensation in comparator circuits presents a unique challenge due to the mixed-signal nature of comparator circuits. The output of a comparator is a digital signal, but the input signal may be either analog or digital in nature. The behavior of the circuits comprising the comparator, and therefore the appropriate method of compensating for the effects of self-heating in those circuits, is dependent on the characteristics of the input signal.
Contributions of this Research
This research has resulted in the design of circuitry that provides compensation for the effects of self-heating in bipolar integrated comparator circuits, and, more generally, in the differential pair amplifiers that comprise them, over a wide range of input signals and operating conditions. The self-heating compensation scheme developed here builds on existing techniques for compensating either purely linear or purely digital amplifiers, providing compensation for mixed-signal circuits, such as comparators, whose operating regions span both the analog and digital regimes. Unlike previous works addressing the compensation of self-heating in comparator circuits, which will be discussed in Chapter 5, the goal of this research has been to provide self- 5
heating compensation for comparators that may be used in non-clocked, asynchronous applications. That is, the compensation scheme designed here is not limited to clocked comparators used in sampling systems, though it is applicable to those comparators as well.
While the compensation circuitry resulting from this research has been designed for a particular IC process, the overall compensation circuit architecture is process independent, and is easily portable to other bipolar processes. Because a circuit-based, as opposed to a technology- or layout-based, approach to self-heating compensation was used, the resulting compensation circuitry enables IC designers, working in any bipolar IC process, to include self-heating compensation for their comparator circuits without the need to modify process parameters or the physical device geometries available in that particular process.
The results of this work will have an impact on the performance of bipolar ICs used in a wide range of applications. High-bandwidth comparators circuits with very stable propagation delay are essential components of many broadband data conversion, test and measurement, and communication ICs and systems. In many of these applications, performance improvements can be realized by accurately and robustly compensating for the effects of self-heating. Specifically, to name only a few of the applications that will benefit from this work, the self-heating compensation circuitry that has resulted from this research will enable the development of oscilloscopes and digitizers with lower trigger jitter, logic analyzers with lower sampling jitter,
ADCs with higher ENOB, and serial transceivers that extend the bandwidth of a given channel.
Organization of this Dissertation Proposal
The goal of this dissertation is to introduce the problem being addressed by this research, namely self-heating-induced errors in integrated circuit comparators, describe the approach taken to address this problem, detail the design of the self-heating compensation circuitry and self- heating-compensated comparator test chip, and to present findings from both circuit simulations and from evaluation of the test chip. Chapters 1 through 4 provide background information and a 6
general introduction to the phenomenon of self-heating in bipolar integrated circuits. Chapters 5 through 8 detail the specific problem of self-heating in comparator circuits, and how it has been addressed by this research.
Chapter 2 provides background information on the physical effects of self-heating on transistors in bipolar integrated circuits. The relevant thermally-dependent parameters, along with their effect on circuit performance are described. An equivalent transistor circuit model accounting for the relevant self-heating effects is presented. A general, high-level discussion of some various approaches to self-heating compensation is discussed as well.
Chapters 3 and 4 address the different ways in which self-heating manifests itself in analog and digital circuits, respectively. Compensation schemes appropriate for purely analog and purely digital circuits are described here as well. The focus of Chapter 5 is self-heating effects in comparator circuits, how these circuits differ from purely analog or purely digital circuits, and why compensation of self-heating effects in these circuits poses a particular challenge.
The design of the self-heating compensation circuitry and the comparator test chip is the topic of Chapter 6, and results from simulation of these circuits are presented in Chapter 7.
Results from measurements of the comparator test chip are detailed in Chapter 8, followed by a conclusion and suggestions for related future research in Chapter 9.
CHAPTER 2
SELF-HEATING
Modeling Self-Heating Effects
Self-heating is a phenomenon in which the temperature of an individual electronic component is affected by the signal applied to or being amplified by that device. As a transistor on an integrated circuit amplifies a signal, the power dissipation of that transistor changes, and its temperature changes accordingly. Many of the small- and large-signal characteristics of integrated circuit transistors are temperature dependent, and are therefore affected by self-heating
[1], [2], [3], [4]. The power dissipation of a bipolar transistor can be approximated as the product of collector current and collector-emitter voltage.
(2.1)
Figure 2.1. Power dissipation in a bipolar transistor is approximately given by the product of collector current and collector-emitter voltage.
As indicated by the use of lower-case and with upper-case subscripts, the collector current and collector-emitter voltage in (2.1) represent the total current and voltage, including both large- and small-signal components. Transistor temperature will be a function of power dissipation in the device as well as the device’s thermal impedance. A transistor on an IC has a 8
thermal impedance network defined by that devices thermal resistance, , and thermal capacitance, . The values of and are determined by process-dependent physical characteristics of the transistor, such as device geometries, substrate material, doping levels, and the existence and nature of any inter-device isolation, such as deep-trench isolation. A transistor’s thermal network and the relationship between power dissipation and local device temperature can be modeled as shown in Figure 2.2. The value of the current source is equal to power dissipation, given by (2.1). The device temperature is increased from its equilibrium temperature, , by an amount, , equal to the voltage developed across the thermal impedance network. Δ
Figure 2.2. Thermal impedance network of a bipolar transistor and its relation to the local device temperature.
The impedance of the thermal network is frequency-dependent, so the transistor temperature variation will be frequency-dependent as well. The transfer function relating power dissipation to increases in transistor temperature is the impedance of the thermal network, and can be expressed as
Δ (2.2) 1 which is a low-pass response with a thermal bandwidth of
1 (2.3) 2 9
Transistors’ thermal bandwidths are typically much lower than the bandwidths of the circuits in which the transistors are used. Thermal bandwidth is strongly process-dependent, though thermal bandwidths in the range of tens to hundreds of kHz are common.
Low-frequency self-heating is determined by a transistor’s thermal resistance, so any device or process features or characteristics that result in increased will exacerbate the effects of self-heating. One such process feature that has become commonplace in high-performance bipolar IC processes is trench isolation. A cross-section of a bipolar junction transistor (BJT) from an IC process utilizing deep-trench isolation is represented schematically in Figure 2.3.
Devices in such a process are surrounded by deep (relative to the depth of the active device) trenches, which are filled with an insulative dielectric material. The purpose of the trench isolation is to reduce substrate coupling, by providing electrical isolation between adjacent devices. The trenches also reduce parasitic capacitances between the collector and the substrate, increasing (transition frequency) of the transistors.
Figure 2.3. Schematic cross-sectional representation of a BJT in a process utilizing deep-trench isolation.
While improving electrical isolation between devices, the addition of trench isolation also has two thermal consequences that lead to increased self-heating: the thermal resistance of each individual device is increased, and the thermal isolation between neighboring devices is increased 10
as well. The latter effect is particularly significant for differential circuits, where problems arise not due simply to self-heating, but specifically due to differential self-heating. In silicon-on- insulator (SOI) processes, in which devices are effectively enclosed in dielectric boxes, the problems associated with self-heating become even more significant.
In addition to being process-dependent, the impedance of a transistor’s thermal network is also a function of the geometry of that device as well. The plot of Figure 2.4 shows how a transistor’s thermal resistance and capacitance vary with emitter length in one hetero-junction bipolar transistor (HBT) process utilizing trench isolation.
Figure 2.4. A transistor’s thermal resistance and capacitance as functions of emitter stripe length. This data comes from the simulation models for a representative 200GHz f T HBT process (IBM BiCMOS8HP).
This particular set of data was obtained through simulation for HBTs of varying
geometry in IBM’s BiCMOS8HP HBT process. The thermal capacitance of transistors in this
process is modeled as increasing linearly with emitter length, while the thermal resistance 11
exhibits an inverse relationship with . For this process, though the thermal device models vary thermal resistance and capacitance with device geometry, they predict a geometry-independent
thermal bandwidth that is a roughly constant 138.4 kHz.
For amplifiers in both analog and digital circuits, the key transistor parameter that is
affected by self-heating is base-emitter voltage, . The notation used here – a lower-case with upper-case subscript – denotes the inclusion of both small- and large signal components of the base-emitter voltage. BJT base emitter voltage, , is given by
(2.4) ln where is the Boltzmann constant, is the electron charge, is temperature, is the total collector current, and is the saturation current. This expression for can be rewritten as [5], [6]
(2.5) ln where is a temperature-independent constant, is the semiconductor band gap voltage, extrapolated to 0 K, and is a positive, process-dependent, temperature-independent constant. The temperature coefficient of the base-emitter voltage for constant collector current is the partial derivative of with respect to .
(2.6) ln The temperature coefficient given by (2.6) is negative, and, for typical IC processes, works out to be in the range of approximately . For IBM’s BiCMOS8HP HBT 1 /° … 2 /° process, the temperature coefficient for is approximately . 1.1 /° A dependent voltage source, used in conjunction with the transistor thermal impedance network shown in Figure 2.2, provides for a simple method of modeling variation due to self- 12
heating. This model is shown in Figure 2.5. The self-heating-induced offset voltage, , is applied at the base of the transistor by a voltage-controlled voltage source, whose value is given
by the local temperature rise, , scaled by a gain factor, , which is typically in the range of Δ . The thermal gain factor, represents the temperature coefficient of the 1 /° … 2 /° base emitter voltage. Note that the value of is positive here due to the polarity of the source in the model.
Figure 2.5. A simple transistor sub-circuit model to account for the temperature-dependent variations of the base-emitter voltage due to self-heating.
Modulation of the base-emitter voltage is modeled, using this approach, as an input-referred
offset voltage. Power dissipation in the transistor will, in general, be signal-dependent, in which
case the input-referred offset voltage will be signal-dependent as well. The bandwidth of the
offset voltage is the thermal bandwidth of the transistor, which is given by (2.3). The thermal
bandwidth is typically much lower than circuit bandwidths. The problems associated with self-
heating are due more to this discrepancy between thermal and signal bandwidths, as we will see,
than simply to the existence of the self-heating voltage, . Conceptually, the self-heating problems in BJT circuits can be represented with the
signal-flow diagram of Figure 2.6. The transistor used in the BJT circuit block shown in the
diagram may be used in either a linear or non-linear mode. The signal that is input to and filtered
by the thermal network is the time-varying transistor power dissipation signal. The power
dissipation signal is scaled, filtered and fed back to the input of the transistor circuit. 13
Figure 2.6. A conceptual block diagram representation of the mechanism by which self-heating affects BJT circuits. The BJT circuit may be linear or non-linear. The signal filtered by the thermal network is the power dissipation of the transistor.
Accounting for Self-Heating in Simulation
In order to accurately simulate the effects of self-heating in bipolar integrated circuits, the
transistor models used for simulation must include self-heating; that is they must model the
mechanism by which power dissipation affects local temperature, thereby affecting device
parameters, such as . The design kit models of many modern, high-performance bipolar IC processes (e.g. BiCMOS8HP) do include modeling of self-heating effects. Some of these use the first-order thermal impedance model shown in Figure 2.2, while others use higher-order (e.g. second- or third-order) thermal impedance networks.
If the available transistor models for the process in which a circuit is being designed do not include self-heating effects, a sub-circuit-based approach to modeling self-heating may be used. Such an approach would replace the transistors in a circuit, for which self-heating effects are of interest with a sub-circuit, like the one shown in Figure 2.5. A current source equal to device power dissipation would drive the thermal RC network, the voltage across which would be used to modulate the input-referred offset voltage source. The transistor in the sub-circuit model is modeled with the available design kit model that neglects self-heating. Regardless of the approach used to include self-heating effects in simulation, an important concern is the accuracy of the thermal impedance model and its relationship to device geometry. In following chapters it will be seen that, when relying on self-heating simulation models for the design of self-heating 14
compensation circuitry, steps can be taken to desensitize that design to inaccuracies in the thermal model.
Compensating for Self-Heating Effects
Assuming that the characteristics of the thermal network itself are out of the control of
the circuit designer, the approaches to reducing the effects of self-heating in BJT circuits can be
broadly classified into two categories. The first, and often simplest, approach is to reduce the
magnitude of the power signal, , thereby reducing the magnitude of the error signal at the input to the BJT circuit. This can be done through various power-balancing techniques, which
aim to maintain constant, signal-independent power dissipation in the transistors. An example of
an active power balancing scheme is given in [7], which describes the power balancing of output
emitter followers on an oscilloscope preamplifier IC. The collectors of the emitter followers are
driven with a level-shifted version of the signals at their bases, maintaining constant power
dissipation in the transistors and eliminating self-heating effects from the output signal. Similar
techniques can often be applied to differential pair amplifiers as well. However, for many types of
circuits (e.g. digital circuits), it is very often not possible to completely power balance the
transistors.
The second approach, illustrated conceptually in Figure 2.7, is to generate a self-heating
compensation signal to be fed back or fed forward and subtracted from the input or output signal.
It is the application of this second approach to comparator circuits that is the subject of this work.
This approach requires the generation of a compensation voltage proportional to the thermal
offset voltage of the transistors being compensated. This can be accomplished by modulating the
power of a compensation transistor proportionally to the device to be compensated. The
compensation voltage can then be derived from that transistor’s modulated voltage. Modulation of a compensation transistor’s power dissipation to be proportional to that of the transistor to be compensated requires the generation of a proportional-to-power signal, in 15
Figure 2.7. As we will see in the following chapters, generation of such a signal is relatively straightforward for transistors operating entirely in the analog or digital regimes, but becomes more complicated for devices whose region of operation spans these two regimes.
(a)
(b)
Figure 2.7. Block diagrams to provide a conceptual illustration of one approach to reducing the effects of self-heating in BJT circuits. In (a), the power signal from the BJT is filtered and scaled by a compensation signal generator circuit and fed back to be subtracted from the input signal. In (b) the compensation signal is fed forward, to be subtracted from the output signal. CHAPTER 3
SELF-HEATING EFFECTS AND COMPENSATION IN ANALOG CIRCUITS
One of the most common building blocks of high-performance bipolar integrated circuits is the differential pair amplifier, such as the one shown in Figure 3.1(a). Both analog and digital circuits, particularly high speed circuits, are comprised largely of differential pair amplifiers.
Differential pairs are also the primary building block of comparator circuits, so the compensation of self-heating effects in differential pairs will be the focus of this work. Additionally, the remaining introductory chapters in this dissertation proposal will focus on self-heating effects on differential pairs utilized in different types of circuits. The effects of self-heating on linear differential pair amplifiers is addressed in this chapter, while digital circuits, and how they are affected by self-heating, is the topic of Chapter 4.
Self-Heating in Linear Differential Pair Amplifiers
Figure 3.1(b) shows a differential pair circuit with the addition of the dependent voltage sources modeling the self-heating-induced modulation of base-emitter voltages as input-referred offset voltages. For now, considering the case of a differential amplifier operating in the linear region, the following conditions can be assumed:
. (3.1)
2 where is the transconductance of the transistors, and is the thermal voltage. The / thermal offset voltages are signal-dependent, and they appear in series with the amplifier input 17
signal, so it is reasonable to expect that they may have some impact on the overall gain of the amplifier.
(a) (b)
Figure 3.1. (a) Simplified schematic of a differential pair amplifier. Differential pairs are a primary building block of many high-performance analog and digital circuits. (b) The same differential pair with the addition of the dependent voltage sources modeling the effect of self-heating on base- emitter voltage.
The differential input to the linear amplifier in Figure 3.1(b) is . The signal at the input to the diff pair itself, after the addition of the thermal error voltage is , the differential signal between the transistor base terminals:
(3.2) 2 The differential gain between and , , is the gain of the amplifier neglecting the effects of self-heating.
(3.3) The gain of interest is the gain of the amplifier accounting for self-heating effects, the gain between and , which will be referred to as . 18
(3.4) To calculate the small signal gain of the amplifier, accounting for the effect of transistor self-heating in the transistors, it is necessary to account for only the small-signal portion of the self-heating voltage, . (Note that small-signal self-heating voltage is denoted by a lower case with lower case subscripts.) The small-signal self-heating voltage is dependent on small-signal variation in device power dissipation, which is the deviation from the quiescent power dissipation, .
(3.5)
The final term on the right-hand side of (3.5) is typically negligible compared to the other terms,
so the small-signal power dissipation can be approximated as
(3.6) The small-signal component of the transistor’s temperature rise will be its small-signal power
dissipation times its thermal impedance.
(3.7) · The self-heating voltage can then be expressed as
(3.8) · The small-signal collector current in (3.8) is
(3.9) 2 2 Because the emitter voltage is assumed constant during linear operation, the small-signal collector-emitter voltage is equal to the small-signal collector voltage. 19
(3.10) 2 Substituting (3.9) and (3.10) into (3.8) yields the following expression for the small-signal self-
heating voltage:
(3.11) 2 1 The amplifier’s differential output voltage is
2 (3.12)
1 1 The differential gain of the amplifier, accounting for self-heating is
1 1 (3.13)
1 Equation (3.13) shows that the effect of self-heating on the gain of a linear diff pair
amplifier can be interpreted as a frequency-dependent modification of the transconductance. A
modified transconductance, which accounts for self heating, can be defined as
(3.14) 1 Note that, for , the transistors are perfectly power-balanced, and , and . Under these conditions the effect of self-heating on the amplifier’s gain is eliminated. While an interesting result, this is often not a practically achievable condition.
The thermal impedance of the transistors, , is the impedance of the network that was shown in Figure 2.2. 20
(3.15) 1 Substituting (3.15) into (3.13) gives the amplifier’s low-frequency (i.e. relative to the amplifier bandwidth) transfer function, accounting for self-heating:
1 (3.16) 1 Equation (3.16) shows that the result of self-heating is the addition of a pole-zero pair to the amplifier’s transfer function. The pole appears at
1 (3.17) and the higher-frequency zero is located at the thermal bandwidth of the transistors
1 (3.18) The frequency of both the pole and zero are typically much lower than overall signal-path bandwidths, so the result is a mid-band non-flatness in the amplifier’s frequency response. The magnitude of the mid-band dip in the gain response is determined by the spacing of the pole and zero. The amount of non-flatness is the difference between the self-heating-affected DC gain of the amplifier and the amplifier gain at frequencies well beyond the thermal corner frequency.
1 (3.19) % 1 100 % 1 An example mid-band gain response for a diff pair amplifier is shown in Figure 3.2. The operating point parameters that yield this particular response are listed on the phase plot. This case shows a mid-band gain variation due to self-heating of more than . 2 21
Figure 3.2. A mid-band frequency response for a differential pair amplifier, showing a self-heating-induced non-flatness. The operating point parameters for this particular example are listed on the phase plot.
The amplifier’s frequency response in Figure 3.2 shows that, from a frequency-domain perspective, self-heating manifests itself as a mid-band gain non-flatness, resulting from the addition of a pole-zero pair in the neighborhood of the thermal bandwidth of the transistors.
When viewed from a time-domain perspective, self-heating can be seen to result in what is known as a slow tail, or thermal tail, in the amplifier’s step response. A simulated step response of a differential pair amplifier, suffering from the effects of self-heating is shown in Figure 3.3. The step response shown is typical for linear amplifiers in bipolar technologies affected by self- heating. The rate at which the output voltage slowly rises to its final value is dictated by the thermal time constant of the amplifier transistors. 22
Figure 3.3. Normalized step response of a diff pair amplifier, accounting for self-heating. The characteristic slow thermal tail is evident.
It is instructive to consider the effect of self-heating, along with the input-referred,
dependent voltage sources used to model self-heating, from a more qualitative perspective. The
self-heating voltage sources, shown in Figure 3.1(b), are dependent upon device temperature,
which is proportional to power dissipation, and therefore proportional to the input signal, . The self-heating voltage, , appears in series with, and adds to, the input voltage, , as described 2 by (3.2). The effect of the self-heating voltage sources is to provide an increase in signal
amplitude from the input signal, , to the signal seen between the bases of the diff pair transistors, , in Figure 3.1(b). Self-heating therefore results in an increase in amplifier gain. However, the gain between the input signal and the self-heating voltage sources rolls off at the
relatively low thermal bandwidth of the transistors. Beyond the thermal bandwidth, the self-
heating voltage sources no longer add to the input signal, the amplifier gain drops back down to
its nominal value, and a gain mismatch between low and high frequencies results. 23
Compensation of Self-Heating Effects in Linear Amplifiers
Equations (3.17) and (3.18) show that self-heating pole-zero cancellation can be achieved
for . This condition corresponds to power-balanced transistors, whose power dissipation in the linear range is not signal-dependent. If this condition is realized, then the amplifier’s frequency response will exhibit no mid-band non-flatness due to self-heating. If, however, this condition is not realizable, then an alternate approach to self-heating compensation must be pursued. One such approach involves modulating the power of separate compensation transistors with a signal that is proportional to the power dissipation of the amplifier transistors.
For a differential amplifier operating in its linear range, the small-signal collector-emitter voltage, collector current, and therefore power dissipation of each transistor are all proportional to that transistor’s collector voltage. The small-signal, differential power dissipation for the diff pair can be written as
(3.20)
The proportional-to-power signal at the output of the amplifier can be used to modulate the collector-emitter voltage, and therefore power dissipation, of two transistors biased at constant current. The differential base-emitter voltages of these transistors will then vary proportionally to the differential self-heating voltage of the diff pair amplifier, and can therefore be used as a compensation signal. This circuit is shown in Figure 3.4. 24
Figure 3.4. A circuit whose output can be used to compensate for the self-heating error voltage of a linear diff pair amplifier. The input to this circuit is the differential amplifier output. The differential emitter voltage is amplified by a variable-gain amplifier and applied as a compensation signal to the diff pair.
The differential amplifier output, which is proportional to the differential power
dissipation of the amplifier, is buffered by the and emitter followers and applied to the collectors of and . The collector current and base voltage of these transistors is held constant, so their differential power dissipation is proportional to their differential collector
voltages. The differential power dissipation of and will therefore be proportional to the diff pair transistors. Because and each have constant base bias, their differential base emitter voltage is their differential emitter voltage. This voltage, , which is proportional to the differential self-heating voltage of the diff pair, , can then be amplified with a gain of , 2 possibly by a variable-gain amplifier (VGA), and used as a compensation signal.
The transfer function of the compensation signal generator circuit of Figure 3.4 is 25
(3.21)
1 The thermal impedance, , in (3.21) represents the impedance of the thermal network of the transistors in the compensation signal generation circuit of Figure 3.4. In order to achieve optimal
self-heating compensation, it is necessary that the bandwidth associated with this thermal network
match the thermal bandwidth of the amplifier transistors being compensated. In general, this
requires matching the geometries of the compensation devices to the amplifier devices. A
bandwidth mismatch between the amplifier’s self-heating signal and the compensation signal will
result in imperfect compensation in the region surrounding the two thermal bandwidth
frequencies.
Matching the geometries of the devices in the compensation circuitry (i.e. and in 1 2 Figure 3.4) to the geometries of the devices being compensated (i.e. and in the amplifier 1 2 of Figure 3.1) is an effective way to desensitize the compensation circuitry to inaccuracy in the
transistors’ thermal models. This is true whether the thermal model is part of a process design kit
model or is generated as a sub-circuit model as described in Chapter 2. As long as the thermal
behavior of equally-sized transistors is consistent, matching transistor geometries will ensure that
the magnitude and bandwidth of the compensation signal is matched to the magnitude and
bandwidth of the amplifier’s self-heating voltage.
The thermal error voltage, , is amplified by a gain of to generate the signal, , that will be used for compensation of the amplifier. The compensation signal can either be applied to the input of the amplifier or to the output. The block diagram of Figure 3.5 illustrates a
scenario in which the compensation signal is subtracted from the amplifier output. One practical
realization of this block diagram would be to apply a compensating voltage signal to the bases of
transistors connected as cascode loads above the amplifier’s load resistors. 26
Figure 3.5. Block diagrams representing a compensation scheme in which the compensating signal is fed back and subtracted from the amplifier output.
For the case of compensation signal feedback to the amplifier output, the overall transfer
function of the compensated amplifier is
1 (3.22) 1 1 1 The objective of self-heating compensation is for the transfer function of the compensated
amplifier given in (3.22) to equal the amplifier transfer function when the effect of self-heating is
neglected. That is, the desired low-frequency transfer function of the compensated amplifier is
(3.23) There is no value of compensation gain, , for which (3.23) is satisfied, which means that, using the compensation scheme illustrated by Figure 3.5, it is not possible to fully compensate for
the effects of self-heating. It is possible to match the amplifier gain above and below the thermal
bandwidth, by setting the compensation gain to
(3.24) However, a mid-band non-flatness in the response will still exist.
A second approach to compensating the amplifier involves feedback of the compensation signal to the input of the amplifier, as illustrated in Figure 3.6. A possible implementation of this 27
approach involves generation of a compensation current signal, to be fed back to the load resistors of the preceding stage.
Figure 3.6. One approach to compensating the amplifier for the effects of self-heating is to feedback the compensation signal to the input of the amplifier.
With the compensation signal fed back to the amplifier input, the transfer function of the
compensated amplifier is
1 (3.25)
1 1 In this case, (3.23) can be satisfied if the compensation gain is set to
(3.26)
An amplifier compensated for self-heating effects as shown in Figure 3.6, with compensation gain given by (3.26), will be perfectly compensated, and any self-heating-induced non-flatness will be eliminated from its response.
The simulated frequency responses and step responses of a diff pair amplifier with and without self-heating compensation are shown in Figure 3.7 and Figure 3.8. Compensation is achieved through feedback of a compensation signal to the input of the amplifier, as shown in
Figure 3.6. The compensation signal was generated by a thermal voltage generating circuit like that shown in Figure 3.4. 28
The effectiveness of the compensation is clearly visible in both the frequency and time domains. The mid-band gain reduction has been eliminated from the frequency response, and the response of the compensated amplifier is flat across its whole bandwidth. The step response in
Figure 3.8 shows that the slow tail has been completely eliminated from the response of the compensated amplifier.
It is worth noting that, while it appears from both Figure 3.7 and Figure 3.8 that the result of self-heating compensation is an increase in gain above the thermal bandwidth of the transistors, this is due only to the fact that the responses shown have all been normalized. In fact, compensation for self-heating of the amplifier transistors results in a reduction in low-frequency gain to match the higher-frequency gain. This is to be expected, because, as was discussed earlier, it is the low-frequency gain that is augmented as a result of self-heating.
Figure 3.7. Simulated frequency response of a diff pair amplifier, compensated for the effects of self-heating. The mid- band drop in gain has been eliminated from the compensated circuit's response. 29
Figure 3.8. Simulated step response of a diff pair amplifier, compensated for the effects of self-heating. Compensation has eliminated the slow tail from the circuit's step response. CHAPTER 4
SELF-HEATING EFFECTS AND COMPENSATION IN DIGITAL CIRCUITS
Self-Heating in Digital Differential Pair Amplifiers
Digital circuits differ from the analog amplifiers described in the previous chapter in that they have digital input and output signals, and the transistors that comprise the circuit operate in a non-linear region of operation. The digital circuits considered here will be restricted to the simple differential pair amplifier of Figure 3.1, operated in a non-linear, fully-switching mode. This type of circuit is common in high-speed, bipolar digital circuits, such as current-mode logic (CML) circuits.
Figure 4.1. A differential pair amplifier operating as a digital circuit. The amplifier's digital input fully switches the amplifier's bias current from one side of the amplifier (one transistor) to the other. 31
When operating as a digital circuit, the diff pair’s input is large enough to drive the amplifier out of its linear range (i.e. at least several ), switching all of the amplifier’s bias current from one side of the diff pair to the other. Assuming the digital input to the diff pair of
Figure 4.1 switches between two discrete logic levels, , (and ) the collector current in the amplifier transistors will switch between two states, one of which is zero:
0 (4.1)
0 Because the transistors in this circuit are either on or off, with collector current of either
or , the differential output voltage will be binary as well 0 (4.2) as will the power dissipation of each transistor.
0 (4.3) 0
Δ where the power dissipation of an on transistor is
(4.4) in (4.4) is the collector-emitter voltage of the on transistor. The temperature rise of the transistors will be given by the binary power dissipation of
(4.3), filtered by the low-pass thermal impedance network.
(4.5) Δ · The self-heating voltage is proportional to , so it is also a low-pass filtered version of the Δ binary power dissipation signal. 32
(4.6) Δ · The differential self-heating voltage, , is the difference between the two individual self- heating sources. This voltage, , is in series with, and adds to, the differential input signal. (4.7) Because the self-heating voltages are band-limited to the relatively low-frequency
thermal bandwidth, they will reach their steady-state values much more slowly than the digital
amplifier’s input or output signals. Figure 4.2 shows the differential self-heating voltage for a
input signal. The input frequency in this case is well below the thermal corner frequency, 50 so the self-heating voltage has time to settle to a steady-state value each time the input switches.
Figure 4.3 shows the self-heating voltage for a input, which is well above the thermal 500 bandwidth. In this higher-frequency case, , does not have time to reach a steady-state value during each half-period of the input signal. The signals shown in the Figure 4.2 and Figure 4.3,
the differential input signal, , and the differential self-heating voltage, , sum together as described by (4.7) to give the total signal, , that is amplified by the differential pair.
Figure 4.2. The differential self-heating voltage of a digital diff pair amplifier for an input signal, whose frequency is below the thermal bandwidth. 33
Figure 4.3. The differential self-heating voltage of a digital diff pair amplifier for an input signal, whose frequency is above the thermal bandwidth.
For a digital input signal with infinitely-fast transitions between logic states, the addition
of the self-heating offset voltage has no effect on the operation of the amplifier; it serves only to
increase the magnitude of the logic levels at the input. However, for input signals with non-zero
risetimes, the effect of the self-heating voltage is to alter the time at which , the input signal at the base of the transistors in the Figure 4.1, crosses zero volts, thereby altering the time at which
the amplifier will switch in response to the input signal, . The impact of the self-heating voltage on the switching time of the amplifier is illustrated in Figure 4.4. The differential input signal, , has been in a low-level logic state for a long time (relative to the thermal time constant) prior to in the plot. The self-heating voltage has therefore had ample time to reach 0 a steady-state value, which, in this example, is approximately . The self-heating 14.5 voltage, , appears in series with the input voltage, , resulting in a negative shift in , the signal that appears at the bases of the diff pair transistors. The input signal in this example has a risetime of , and a voltage swing of . The slew rate in the vicinity of its zero- 1 200 crossing is roughly . The result, as shown in Figure 4.4, is a zero-crossing time shift, 190 / which can be calculated as 34
(4.8) Δ where is the slew rate of the input signal.
Figure 4.4. The effect of the self-heating offset voltage on the time of the input signal's (V bd 's) zero-crossing. For finite-slew- rate input signals, the self-heating offset voltage results in a time shift of the input zero-crossing and of the amplifier switching instant.
For continuous, 50% duty cycle, digital input signals the self-heating voltage at each zero
crossing will be equal in magnitude, and its polarity will vary with the direction of the input
signal’s transition. The time delay due to self-heating, as described by (4.8), will, therefore, be
equal for each transition of the input signal, and can be modeled as an additional constant delay
through the amplifier. However, for any input signal for which varies from one transition to another, the delay due to self-heating will not be constant. Signals for which the self-heating voltage at the zero-crossing instants will vary include signals with variable or non-50% duty 35
cycles. Many digital signals of interest, such as wireline data signals fall into this category.
Additionally, 50% duty cycle signals that are switched on and off (duty cycle changes from 0% to
50%) may result in variable self-heating voltage for a time period dictated by the thermal time constant after being switched on.
Not all signals with non-50% duty cycles result in variable self-heating voltages and variable delay through the amplifier. Signals of any duty cycle, including variable-duty-cycle signals, that allow the self-heating voltage to reach a steady-state value between each transition of the input signal, will always result in a constant self-heating voltage at the zero-crossing times.
This category of signals is characterized by always remaining in either a low or high state for many thermal time constants (i.e. long enough for the devices to reach a steady-state temperature).
Additionally, signals of any kind whose entire frequency spectrum lies well above the thermal corner frequency will experience self-heating voltages whose magnitudes at the switching instants, while perhaps variable, may be small enough that their effect on delay through the amplifier is negligible. This results from the reduced gain of the input-signal-to-self-heating- voltage transfer function at frequencies above the thermal bandwidth, due to the low thermal impedance at these frequencies.
The example illustrated in Figure 4.4 shows an input signal with a risetime of , 1 which, for on-chip digital signals, is very slow. The timing error that results from self- 75 heating represents an error that is 7.5% of the signal risetime. For a, perhaps more realistic,
risetime, the timing error would be only . In many applications, timing 100 7.5 variations of this magnitude, resulting from the self-heating of a single amplifier, would be
negligible. However, in applications where many similar amplifiers are cascaded, such as
programmable delay lines, cumulative timing errors due to self-heating can become significant. 36
Compensation of Self-Heating Effects in Digital Circuits
The approach to compensating for self-heating effects in digital circuits is similar to that used for linear circuits: use a proportional-to-power signal to modulate the power dissipation of a pair of compensation transistors proportionally to the power dissipation of the transistors to be compensated. When compensating linear diff pair amplifiers, the output voltage provides the proportional-to-power signal, because it is proportional to both collector current and to collector- emitter voltage. Proportionality between the output voltage and the collector-emitter voltage is due to the fact that, in the linear range of operation, the emitter voltage is assumed to be constant.
This is no longer true for diff pair amplifier operating as a digital circuit. However, because the differential power dissipation of the amplifier transistors can assume only two possible states,
, as given by (4.3) and (4.4), and the differential output voltage also can assume only two possible states, , as given by (4.2), the output signal of the digital amplifier will be proportional to the differential power dissipation of amplifier transistors. The output voltage of the digital amplifier can therefore be used as the proportional-to-power signal needed to modulate the power dissipation of the transistors in a compensation voltage generation circuit, such as the one shown in Figure 4.5.
The circuit used to generate the self-heating compensation signal for a digital amplifier is the same circuit as that used for a linear amplifier, and its operation is identical as well. The only difference is the nature of the proportional-to-power signal applied to the input of the compensation circuit, which is, in this case, a digital signal. The proportional-to-power signal at the amplifier output is buffered by and and applied to the collectors of and , which are biased with constant collector current and base voltage. The power dissipation of and is therefore modulated proportionally to the power dissipation of the amplifier transistors, and the differential emitter voltage is proportional to the amplifier’s self-heating voltage. The output of the compensation amplifier in Figure 4.5 can be fed back to the amplifier input, possibly by 37
converting the compensation signal to a current, and applying it to the load resistors of the preceding stage, thereby nulling the effect of the self-heating voltage at the amplifier input.
Figure 4.5. A circuit whose output can be used to compensate for the self-heating error voltage of a digital diff pair amplifier. The input to this circuit is the differential amplifier output signal. The differential base-emitter voltage is amplified and fed back to the diff pair as a compensation signal.
As with the self-heating compensation scheme presented for linear amplifiers, the gain of
the amplifier, , used to scale the differential emitter voltage, , in Figure 4.5, would likely be adjustable. A procedure for calibrating the amplifier gain in order to provide optimal
self-heating compensation would be a necessary component of the design of an overall self-
heating compensation system.
Assessing Self-Heating Effects and Compensation in Digital Circuits
In digital circuits, the signal-dependent input offset voltage manifests itself at the output
of the circuit as signal-dependent delay or inter-symbol interference (ISI). The concept of ISI is 38
typically used to describe the data-dependent timing errors due to signal integrity issues associated with the channel over which data is transmitted. The result, however, is the same as for self-heating; in both cases an additive voltage – whether due to channel-related reflections or ringing or to self-heating-induced signal-dependent modulation – alters the timing of signal transitions relative to some reference. In order to determine the significance of self-heating effects
for digital circuits, as well as to evaluate the effectiveness of attempts to compensate for those
effects, it is necessary to have methods for measuring the errors that result due to self-heating.
Eye Diagrams
Assessing ISI due to self-heating at the output of a digital circuit is similar to assessing
ISI from other sources. One method for measuring ISI is to generate an eye diagram referenced to
the input signal, in order to measure the amount of jitter between input and output transitions.
Figure 4.6 shows an eye diagram of the output signal from a digital circuit suffering from self-
heating-induced ISI. The input signal to the diff pair in the example of Figure 4.6 is initially low
for a long time (long relative to the transistors’ thermal time constant) – long enough for the
transistors to reach thermal equilibrium and for to reach its maximum steady-state value. The input then begins switching at a frequency much higher than the thermal bandwidth, with a 50%
duty cycle. An eye diagram of the output signal is generated using the input signal as a timing
reference. Because the input is a continuous 50% signal, and the input signal is used as the timing
reference, the eye diagram differs from the typical eye diagram generated by digital data, or by a
pseudo-random binary sequence (PRBS) signal, in that only a single rising edge is shown. In each
case, however, the effect is the same: the eye diagram reveals any variation – jitter, or drift – in
the timing of the output transitions.
As the input begins to switch the transistor that was initially off begins to heat, while the
initially-on transistor begins to cool. The self-heating voltages for each transistor both converge
to an equilibrium value, and as they do the timing of the output signal transitions drifts as well. 39
The eye diagram of Figure 4.6 shows that for an input signal risetime of , the timing of 100 the output signal drifts by a total of . The observed timing drift only accounts for ~7.5 timing error due to the self-heating voltage varying over a range from its negative maximum value to zero – half of its total range. The total self-heating-induced ISI for this circuit is, therefore, twice what is observed in this eye diagram, or . ~15
Figure 4.6. An eye diagram representation of the output signal from a digital circuit suffering from self-heating-induced ISI. The input to the circuit in this example had been sitting in a low state for a long time (relative to the thermal time constant), and then began switching with a 50% duty cycle. The input signal risetime of results in of self-heating- induced ISI. ~
Eye diagrams provide a useful tool for measuring the effect of self-heating on a digital
circuit, both in simulation and when measuring real hardware. In the simulation domain, if the
self-heating voltage is accessible through the simulation models, the total self-heating-induced ISI
can, instead, simply be calculated using the relationship given in (4.8) as 40
(4.9) 2Δ where is the range of the self-heating voltage over the time period for which the ISI is Δ calculated.
Duty-Cycle Distortion
A second method for assessing the effects of self-heating on the performance of digital circuits involves measuring the amount of duty-cycle distortion (DCD) at the output of the circuit.
DCD is the difference between the input and output pulse widths or duty cycles. It is typically used to characterize clock and data jitter [8], but also provides an effective tool for characterizing the timing errors resulting from self-heating at the output of digital circuits. When used as a measure of clock and data jitter, DCD is expressed as a fraction of a unit interval (UI), or bit period. In this work, where DCD is used to characterize timing variation or jitter due to self- heating, it will be expressed with units of seconds, and can be calculated as
(4.10) | | where and are the signal pulse widths at the amplifier output and input, respectively. The same input and output signals used to generate the eye diagram of Figure 4.6, can also be used to calculate the amount of DCD present at the output signal. The difference between input and output pulse widths can be measured and plotted as a function of time, as seen in Figure
4.7. The input signal used for this example is initially low for a period of time sufficient for the transistors to reach thermal equilibrium. The input then begins to switch at a frequency well above the thermal bandwidth, with a 50% duty cycle and risetimes. The DCD at the 100 output is at its maximum value on the first input-output transition, when is at its maximum value. This maximum DCD value is , which agrees with the total ISI value illustrated ~15 by the eye diagram of Figure 4.6. 41
After the input signal begins switching with a 50% duty cycle, begins to decay toward its equilibrium value, and the difference between input and output pulse widths – the DCD introduced by the circuit – decays toward zero. The rate of decay of DCD from its initial maximum value toward zero is determined by the transistors’ thermal time constant, which for the transistors modeled here (IBM BiCMOS8HP) is . ~1.15
Figure 4.7. Self-heating-induced duty-cycle distortion for a digital differential pair amplifier. The DCD in this example is due to application of the same input signal used to generate the eye diagram of Figure 4.6: V id is initially low for a period of time sufficient for the amplifier transistors to reach thermal equilibrium, then begins switching with a 50% duty cycle at a frequency much higher than the thermal bandwidth, with 100 psec risetimes.
This scenario, in which the input signal is initially constant for a period of time long enough to allow the transistors to reach thermal equilibrium (a thermal soaking period), then begins switching at a frequency much higher than the thermal bandwidth, represents a worst-case 42
situation for ISI or DCD. It is a worst-case scenario, because the thermal soaking period ensures that the self-heating voltage reaches its maximum possible value for the given DC bias conditions of the amplifier.
Assessing the effects of self-heating at the output of digital circuits is of particular interest for this work, because, regardless of the nature of the input signal, the output of a comparator circuit is a digital signal. The evaluation of self-heating induced errors at the output of comparator circuits as well as the effectiveness of efforts to compensate for those errors, will be assessed using the methods presented here for purely digital circuits. CHAPTER 5
SELF-HEATING EFFECTS AND COMPENSATION IN COMPARATORS
The previous two chapters have addressed the effects of and methods of compensating for self-heating in purely analog and purely digital circuits. Self-heating effects and compensation in comparator circuits becomes more complicated, because, instead of behaving as purely analog or purely digital circuits, comparators are mixed-signal in nature – their inputs are analog, and their outputs are digital. Even in the case of a digital input signal, such as a serial data transmission, the input to a comparator is treated as an analog signal; that is, the nature of its transition between logic levels ultimately affects the output of the comparator circuit. Due to their mixed-signal characteristics, self-heating affects comparator circuits differently than it does purely analog or purely digital circuits, and the compensation schemes applied to analog or digital circuits are inadequate for optimal compensation of comparator circuits.
A simplified schematic of a typical bipolar comparator circuit is shown in Figure 5.1. The comparator comprises several cascaded differential pair gain stages. The comparator circuit shown in Figure 5.1 also includes circuitry to provide adjustable hysteresis (varying bias current,
, adjusts hysteresis), as is commonly employed in instrumentation applications (e.g. oscilloscopes and logic analyzers). In some applications the comparator circuit shown might be preceded by a linear preamplifier, perhaps with variable gain.
In many comparator applications the differential input signal may have a very large dynamic range, meaning that the input stage may operate entirely within its linear range for small input signals, and may behave as a non-linear amplifier – switching completely – for large input signals. For moderate input amplitudes, the first stage may operate between the two extremes: 44
outside its linear range, but not fully switching. Because the output signal is digital, the comparator circuit would be designed with adequate gain to ensure that the output gain stage switches completely for even the smallest expected input signal. With exception of the output stage, which always behaves as a purely digital amplifier, each of the amplifier gain stages may behave as either a purely linear amplifier, purely digital amplifier, or somewhere in between these two regimes.
Figure 5.1. A simplified schematic of a typical bipolar comparator circuit. This comparator consists of three cascaded differential gain stages, and circuitry to provide adjustable hysteresis.
Because the output of a comparator circuit is a digital signal, self-heating of the
transistors in any of the comparator gain stages, regardless of the region of operation of those
gain stages, will be manifested as a timing error and characterized as ISI or DCD at the output of
the comparator. However, the individual self-heating mechanisms that contribute to ISI or DCD
at the comparator output may differ from stage to stage and as a function of the differential input
signal amplitude. Regardless of the operating region of a particular stage, the effect of self-
heating for that stage can always be modeled as an input-referred self-heating offset voltage. For
a diff pair stage behaving as a linear amplifier, that offset voltage will be amplified and will 45
appear as a time-varying offset voltage at the input to the following stage, adding to its input- referred self-heating voltage. For an amplifier driven hard enough to switch completely, its input- referred self-heating voltage will translate to a timing error in the transition of the signal at the output of that stage and the input to the following stage.
Compensation of Self-Heating Effects in Comparators
There are several ways to approach the compensation of self-heating effects in
comparator circuits. As with all circuits susceptible to the effects of self-heating, comparators can
benefit from an overall reduction in absolute power dissipation of their transistors. Because the
amplifier stages are, in general, non-linear and may be fully-switching, it is not possible to power
balance the comparator amplifiers as can occasionally be done for linear amplifiers. However,
any reduction in power dissipated in the transistors will reduce the differential power dissipation
between transistors and will alleviate self-heating-induced errors. Power dissipation may be
reduced by measures such as reducing the collector-emitter voltage of on-transistors, or by
reducing amplifier bias current. Such measures can only reduce, not eliminate, self-heating
effects, and because reduction in power dissipation is typically correlated to reduction in
bandwidth, reducing power dissipation is often not a viable approach to reducing self-heating
effects. Previous works have sought to reduce differential heating in amplifiers used in sampling
comparator applications by applying either switched [9] or variable [10] bias current to the
comparator amplifiers.
Alternatively, compensation of self-heating effects in comparator circuits can be
approached in a manner similar to that employed for purely analog or digital circuits: use a signal
that is proportional to the differential power dissipation of the transistors to be compensated to
modulate the power dissipation of similar transistors, whose differential base-emitter voltages can
then be amplified, fed back, and used as a compensation signal. The goal of this approach is not
to prevent the occurrence of differential self-heating, but rather to compensate for it. It is this 46
approach of generating and feeding back a compensation signal that is the focus of this work. It will be discussed in detail following the next section, which will first address prior works that have sought to alleviate comparator self-heating effects.
Prior Works Addressing Self-Heating in Comparators
Switched-Bias Comparators for Sampling-Comparator Systems
A sampling comparator system (SCS) is a successive-approximation ADC feedback loop
used for equivalent-time sampling of periodic signals [11]. A typical SCS is illustrated
schematically by the block diagram of Figure 5.2. Because sampling comparator systems are
often used to precisely measure the step response settling times of electronic instruments and
circuits, such as signal generators, opamps, and digital-to-analog converters (DACs) [11], it is
imperative that the SCS itself exhibit fast settling behavior. Slow thermal tails due to self-heating
in the comparator circuit in the SCS loop, must therefore be reduced to levels that do not
adversely impact measurement accuracy.
Figure 5.2. Block diagram of a switched-comparator system used for equivalent-time sampling of periodic signals.
Timing of the comparator clock in the SCS is synchronous to the input signal, and its
delay is precisely adjustable, allowing the sampling instant to be varied relative to the timing of
the input signal. The successive approximation procedure operates over N periods of the input 47
signal in order to digitize a sample to N-bit precision, after which the programmable delay line is adjusted, the sampling instant is incremented relative to input-signal timing, and the digitizing of the next sample begins. The comparator circuit in this system is particularly susceptible to self- heating-induced errors when digitizing samples in the short time period (short relative to the transistors’ thermal time constants) immediately following input-signal transitions, because during the acquisition of these samples, the output of the DAC (the comparator threshold input) is at a high voltage, while the input voltage is low (prior to the input transition). This condition at the comparator input results in large thermal differentials between comparator transistors. For an
SCS used for highly-accurate step response settling measurements, the time period immediately following transitions of the input signal is the worst possible time to suffer from self-heating.
Laug et al. [9] address this problem by applying a switched bias current to the latching comparator of the SCS, as shown in Figure 5.3.
Figure 5.3. A simplified schematic of the switched-bias-current latching comparator designed by Laug et al. [9] to reduce self- heating effects in a sampling comparator system. 48
The bias current for the tracking differential pair of the latching comparator shown in
Figure 5.3 is enabled for only a short period of time – , just long enough to accurately ~2 track the input signal – prior to strobing the comparator latch. Because the tracking diff pair is on for such a short period of time, relative to the thermal time constant, the transistors do not have time to heat up enough to result in significant differential heating, regardless of the state of the input.
This switched-bias approach works well in applications where the comparator is used for sampling and need only be active for short periods of time at fixed (and relatively slow – 30 in [9]) sampling intervals. For comparators used in non-sampling applications, such as the trigger
comparator in an oscilloscope or digitizer, a switched-bias approach to reducing self-heating
effects is not feasible. In these applications, the comparator is used to detect input-signal
threshold crossings, and to determine the timing of these threshold crossings; it must therefore be
always active and ready to switch at any instant in response to the input signal.
Dynamically-Biased Comparators for Sampling-Comparator Systems
Bergman and Waltrip [10] improve on the switched-bias technique employed in [9] by
using a comparator bias current that is dynamically-controlled by the magnitude of the
differential input voltage signal. This dynamic bias approach can be understood by again
referencing Figure 5.3, where, now, the bias current is not switched on and off by a binary enable
signal, but is, instead, continuously varied based on the magnitude of the differential input
voltage. For large differential input voltages – for which the comparator is not near its switching
threshold, and differential self-heating is at its worst – the bias current to the comparator is
reduced to its minimum level. For small differential inputs – for which the comparator is near its
switching threshold, and differential self-heating is at a lower level – the bias current is increased
to a level sufficient to provide the bandwidth and noise performance required for the application. 49
The idea here is to bias the comparator for desired performance only when it is likely to switch, and when self-heating is at a minimum.
As with the switched-bias technique, the dynamically-biased comparator targets high- accuracy, equivalent-time sampling applications, and is particularly well-suited for precision settling-time measurements. It is not well-suited to applications in which a primary function of the comparator is to provide accurate timing information for input-signal threshold crossings for a wide range of input signals (i.e. wide range of amplitude, frequency, and slew rate). To achieve the desired accuracy of threshold crossing detection, the comparator transistors should be biased at sufficiently-high at the time of threshold crossings. Relying on the input-signal threshold crossings themselves to increase comparator bias to the requisite level for accurate detection of
those threshold crossings poses an obvious problem.
Feedback of a Self-Heating Compensation Signal
The approach pursued in this work for the reduction of self-heating effects in comparator
circuits is similar to that described in previous chapters for purely analog and purely digital
differential pair amplifiers. A signal that is proportional to the differential power dissipation of
the transistors affected by self-heating is used to modulate the power dissipation of a pair of
compensation transistors, whose differential base-emitter voltage is amplified and fed back to the
amplifier to be compensated. For purely linear or purely digital differential pair amplifiers, the
differential input and output voltages can serve as the proportional-to-power signal (so long as
input common-mode voltage remains constant). For a differential pair, whose operation spans the
two regimes (e.g. a diff pair in a comparator circuit), the differential output voltage no longer
provides a signal that is proportional to the differential power dissipation of the transistors.
The relationship between the differential power dissipation for a diff pair amplifier and
the differential output voltage is illustrated by Figure 5.4 for all three categories of amplifier
operation (i.e. a linear amplifier, a digital amplifier, and an amplifier whose region of operation 50
spans the two regimes). For a linear amplifier the differential input voltage is restricted to a small region, over which the differential output voltage and power dissipation both vary continuously and linearly and are proportional to one another. A digital amplifier is characterized by switching between two discrete states, corresponding to positive and negative differential input voltages.
These two states are symmetrically located about the origin, but may lie anywhere along the fully-switched region (i.e. constant- region) of the transfer characteristic. For the example shown, both the input and output signals switch between . Because power dissipation 250 and output voltage at each of the two digital amplifier states can be considered to be points on two lines, both crossing through the origin, the output voltage is a proportional-to-power signal for the digital amplifier.
Figure 5.4. Large-signal transfer characteristic of a differential pair amplifier for both differential output voltage and differential power dissipation. A linear amplifier operates in the region shown, where V id is restricted to small values. Also noted are the two discrete states, between which a digital amplifier switches based on input voltage polarity. 51
The operating region of an amplifier, whose input signal can vary over a wide range, such as an amplifier in a comparator circuit, may span the full range illustrated by Figure 5.4. For such an amplifier, the differential output voltage is no longer everywhere proportional to the differential power dissipation of the amplifier’s transistors, as is clear from the figure. In the presence of significant input common-mode voltage variation the situation becomes worse than what is depicted in Figure 5.4. While it is possible to use the differential output voltage from the amplifier as an approximation to a proportional to power signal in order to achieve imperfect compensation for a fixed input common-mode voltage, as that common-mode level varies, the corresponding self-heating variation is not tracked by the amplifier’s output voltage. That is, while the differential output voltage may provide a reasonable approximation to a proportional- to-power signal for a comparator diff pair amplifier at a fixed input common-mode voltage, it is unable to accommodate any variation in that voltage. This is illustrated in Figure 5.5, which compares the large-signal transfer characteristic for a diff pair output voltage with the differential self-heating transfer characteristic at three different input common-mode levels. While the output voltage can be seen to provide a reasonable approximation to a proportional-to-power signal at any one input common-mode voltage (after appropriate amplification), it is unable to track common-mode variation at the input.
If optimal self-heating compensation is to be achieved using a technique similar to that applied for the compensations of purely linear or purely digital circuits (i.e. feed back of a self- heating voltage cancellation signal), then a signal other than the differential output voltage will be required to serve as a proportional-to-power signal. The desired signal is one that is not only proportional to differential power dissipation over the full range of differential input voltage, but over the full range of common-mode input voltage as well. Generation of such a signal is discussed in the following section. 52
Figure 5.5. Large-signal transfer characteristic of a differential pair amplifier showing the variation in differential power dissipation as a function of input common-mode voltage.
Generation of a Proportional-to-Power Signal
The differential power dissipation between the transistors of a differential pair amplifier operating over any portion of the region depicted in Figure 5.4 is
(5.1) Δ A signal proportional to the differential power dissipation of the amplifier transistors can be generated by monitoring the collector currents and collector emitter voltages of the transistors and performing the operations specified by (5.1). The diff pair of Figure 5.6 illustrates how the current and voltage values that comprise (5.1) can be obtained from the circuit.
A portion, , of the load total resistance, , is used as a current sense resistor, allowing the collector currents to be expressed in terms of the voltage across that resistor as
(5.2) 53
The collector-emitter voltages in (5.1) can be measured directly between the output nodes and the coupled emitter node as
(5.3)
Figure 5.6. Diff pair amplifier with a portion of the load resistors dedicated to sensing collector current. The relevant node voltages used to monitor differential power dissipation are labeled.
Substituting (5.2) and (5.3) into (5.1) yields
(5.4) Δ Because the resistance term in (5.4) appears in all terms, it can be eliminated, and the resulting signal will still be proportional to differential power dissipation.
(5.5) Δ 54
Equation (5.5) can be rearranged into a more meaningful form:
(5.6) Δ which shows that a proportional-to-power signal can be obtained as the difference between two
products of the voltages labeled on the circuit of Figure 5.6. Generation of the proportional-to-
power signal described by (5.6) is illustrated by the block diagram shown in Figure 5.7.
Figure 5.7. Block diagram illustrating the generation of a proportional-to-power signal described by (5.6).
As will be seen in the following chapter, the proportional-to-power signal, , can be generated by two multiplier circuits with cross-coupled outputs. The signal can then applied to
the same thermal voltage generator circuit described for use in compensating linear and switching
circuits and reproduced here in Figure 5.8. 55
Figure 5.8. The proportional-to-power signal given by (5.6) is buffered by the and emitter followers and applied to the collectors of and , thereby modulating their power dissipation proportionally to the transistors in the comparator diff pair. The thermal voltage between the emitters of and is amplified and fed back to the input of the diff pair to cancel its self-heating voltage.
The output of the compensation voltage generator is amplified by a variable gain
amplifier and fed back to the input of the amplifier to be compensated. The compensation signal
can be fed back as a current to the load resistors of the stage preceding the amplifier to be
compensated. For each diff pair amplifier in the comparator circuit – there are three in the
example comparator of Figure 5.1 – there must be circuitry to generate the proportional-to-power
signal for that amplifier, as well as a thermal voltage generating circuit and a compensation-signal
amplifier.
The gain, , of each compensation-signal VGA must be set during a calibration procedure. Because there is a compensation circuit with a VGA for each diff pair in the comparator it is conceivable that each compensation amplifier gain would need to be adjusted individually. However, as long as measures are taken to ensure adequate matching between 56
individual amplifiers, a single calibration procedure, in which all VGA gains are set identically, will provide adequate compensation for each individual amplifier and for the comparator circuit as a whole. This is an important concern that has been addressed in simulations accounting for device mismatches, as will be discussed in Chapter 7.
Assessing the Effectiveness of Comparator Self-Heating Compensation
Because the output of a comparator is a digital signal, self-heating effects manifest
themselves there as signal-dependent timing errors, as described for purely digital circuits in the
previous chapter. The same tools described for assessing self-heating effects and compensation in
purely digital circuits, namely eye diagrams and DCD measurements, are applicable to
comparator circuits as well.
In many applications, comparator inputs are not well-defined and may vary greatly in
terms of voltage swing, frequency, duty cycle, common-mode level, and slew rate. The self-
heating behavior of each stage in the comparator varies along with the input signal, and that
behavior must be accommodated by the compensation scheme employed, as it is for the method
described here. It is important to verify the effectiveness of the compensation circuitry over a
wide range of inputs, both in the simulation domain during the design phase, and with
measurements when evaluating the resulting hardware. CHAPTER 6
TEST CHIP CIRCUIT DESIGN
A test chip comprising a comparator circuit and circuitry to implement the self-heating compensation scheme detailed in the previous chapter has been designed in IBM’s BiCMOS8HP process and fabricated through The MOSIS Service. This is a BiCMOS process featuring
, trench-isolated, heterojunction bipolar transistors (HBTs), along with 200 0.13 CMOS devices. Trench isolation makes BiCMOS8HP an attractive process for the evaluation of self-heating compensation circuitry, because it increases the thermal isolation between HBTs on the chip, thereby increasing their susceptibility to the effects of self-heating.
Also included on the test chip is a linear amplifier, which, like the comparator circuit, also includes self-heating compensation circuitry. The linear amplifier was included on the chip as a means of reducing the risk associated with the comparator circuit. The amplifier circuit is smaller and less complex than the comparator circuit, and, more significantly, measurement of the effectiveness of the self-heating compensation of the amplifier circuit would require significantly less sophisticated, more readily available test instruments than is the case for the comparator circuit. The comparator circuit and its compensation circuitry did prove to be functional and were successfully evaluated, so the linear amplifier will not be discussed further in this dissertation.
The remainder of this chapter will detail the design of the comparator circuit and of the circuitry included to compensate the comparator for the effects of self-heating. 58
Top-Level Comparator Design
A top-level block diagram of the comparator portion of the chip is shown in Figure 6.1.
Though not explicitly shown in the block diagram, this is a fully-differential comparator; the
input, output, and all internal signals are differential. The comparator comprises input and 50 Ω output amplifiers, both of which are designed to be inherently immune to the effects of self-
heating, along with the comparator core. The comparator core is a cascade of four differential pair
amplifier stages, represented as DP i in the block diagram. Also shown is the positive feedback
path used to generate adjustable hysteresis, along with its control input, .
Figure 6.1. Top-level block diagram of the comparator portion of the test chip.
Because each differential pair gain stage will, in general, experience a different degree of
self-heating, each amplifier is accompanied by a separate block of self-heating compensation
circuitry, labeled ShComp i in Figure 6.1. In each of the four individual self-heating compensation blocks, a proportional-to-power signal is generated, which is used to generate the self-heating compensation signal that is fed back to the amplifier input. These feedback signals, labeled in the block diagram, are currents generated by variable-gain transconductance amplifiers in the
compensation blocks. The gains of these amplifiers are set by individual control signals, , which are analog control voltages generated off chip. 59
Input Amplifier
Because the purpose of the test chip was to allow for evaluation of the self-heating
compensation of the comparator core, the input amplifier was designed to be inherently
insensitive to the effects of self-heating, not requiring any compensation of its own, so as not to
affect measurement of the self-heating effects of the comparator. A top-level block diagram of the
input amplifier is shown in Figure 6.2. The two phases of the differential input signal are inputs to
separate, single-ended common-base amplifier stages. Also included is circuitry to allow for
nulling of any offset voltage resulting from component mismatch in comparator signal path.
Offset voltage nulling is performed during the calibration procedure, which will be discussed later
in this chapter.
Figure 6.2. Top-level block diagram of the 50 Ω differential input amplifier, comprising two common-base stages, as well as an offset-nulling block.
A schematic of the common-base amplifiers is shown Figure 6.3. The input is terminated
in 50 Ω to the emitter of the common-base transistor, . This node is held one base-emitter drop above ground by transistor , so the amplifier is designed to be driven by a differential signal with a common-mode voltage of approximately . The feedback provided by transistor 700 helps maintain a low impedance at the emitter of over a wide frequency range. The transistors 60
of this amplifier are made large in order to keep their thermal resistances, , and therefore their self-heating, as low as possible. The nearly negligible self-heating of the input amplifier is due
almost entirely to self-heating in the feedback transistor, , which results in a slight non-flatness of the feedback path gain, in turn resulting in mid-band variation of the input impedance, and therefore the overall amplifier gain. The large size of helps insure that self-heating effects for this amplifier are negligible.
Figure 6.3. Common-base input amplifier schematic.
The pseudo-differential (only purely differential if the input signal is purely differential)
output current from the two common-base amplifiers goes to a pair of load resistors at the 100 Ω input of the comparator core, where it is converted to the voltage input to the comparator. The
gain of the input amplifier stage is approximately two.
In order to eliminate any voltage offsets due to component mismatch in the comparator
signal path, an offset-nulling block is included with the input amplifier. This circuit,
InputOffsetNull in Figure 6.2, is controlled by a voltage input signal, VinOffNull, which steers a
differential current between the two common-base amplifier outputs, allowing for elimination of
offset voltages over the range of . The offset-nulling control voltage is adjusted during a 20 calibration procedure, which will be described later in this chapter. 61
Output Amplifier
The output amplifier consists of a pair of cascaded emitter-follower amplifiers. The
output amplifier schematic is shown in Figure 6.4. As with the input amplifier, the output
amplifier is designed to be inherently insensitive to self-heating. The resistor between the 1.9 Ω emitters of the first pair of emitter followers provides self-heating compensation for these transistors by power balancing them. Simulation indicates that the compensation provided by this resistor is effective over a full range of potential process variation. The second pair of emitter followers are power balanced by the resistors in their collectors. The compensation 130 Ω provided by these resistors was observed in simulation to be slightly susceptible to process variation, so an adjustable positive supply, , was provided for these devices. A dummy output amplifier, whose inputs and outputs are pinned out from the chip, was included for the calibration of this supply voltage. Again, this calibration procedure will be described later. The output amplifier is designed to drive load-terminated transmission lines. 50 Ω
Figure 6.4. Output amplifier schematic. 62
Comparator Core
The core of the comparator chip is illustrated at a block diagram level in Figure 6.1, and at the schematic level in Figure 6.5. The comparator circuit consists of four cascaded gain stages, each with its own self-heating compensation circuitry. An additional diff pair is included to provide hysteresis that is adjustable over a range of . 0 … 75
Figure 6.5. Schematic of the comparator core.
The self-heating compensation blocks, ShComp in Figure 6.5, share bias current with the diff pair transistors in an effort to conserve power. Input signals for these compensation circuitry blocks are picked off from nodes of the comparator gain stages. These input signals, which provide measures of the collector-emitter voltage and collector current for each transistor, are used in the ShComp blocks to generate proportional-to-differential-power signals for the diff pair amplifiers’ transistors. Those signals are then used to generate the compensation signals, differential currents, which are fed back to the load resistors preceding the diff pair being compensated. Load resistors are broken into two segments, with the voltage drop across the 20 Ω segment used as a measure of the collector current in the corresponding transistor. The compensating feedback current is injected into the intermediate node, so as not to affect the 63
collector-current-sense voltage across the resistor. The gain of each compensation block is 20 Ω individually-programmable, and each gain-control voltage, , is pinned out from the chip. However, simulation indicated that it is sufficient to program all gains equally, even when accounting for variations due to mismatch. When testing the chip, as will be described in a subsequent chapter, all signals were adjusted together with a single voltage. The load resistors for the common-base input amplifiers are included in the comparator
core schematic of Figure 6.5. These load resistors are broken into two segments, equal to those of
the following diff pair amplifiers, with the compensation current for the first differential pair gain
stage in the comparator being fed back to the intermediate node. Ensuring that all self-heating
compensation currents are fed back to equal-valued load resistors enables the gains of all four
compensation paths to be calibrated together.
The input amplifier load resistors connect to their own adjustable power supply, , which provides a way to vary the common-mode voltage present at the input to the comparator, in
order to assess the effectiveness of the self-heating compensation over a range of input common-
mode levels.
Self-Heating Compensation Circuitry
The self-heating compensation circuit, ShComp, shown in the block diagram of Figure
6.6 and the schematic of Figure 6.7, consists of three main functional blocks: a power-to-voltage
converter (PVC), the thermal voltage generation transistors, and a variable-gain transconductance
amplifier (VTA). 64
Figure 6.6. Block diagram of the self-heating compensation block. The comparator circuit includes four of these blocks - one for each diff pair amplifier.
The input signals to the compensation block are those required for the generation of a
signal that is proportional to the differential power dissipation of the diff pair amplifier
transistors, as described by (5.6). These inputs are the amplifier node voltages shown on the
schematic of Figure 5.6 and Figure 6.5. The proportional-to-power signal, generated by the PVC,
is applied to the collectors of the thermal voltage generation transistors, and in Figure 6.7, modulating their power dissipation proportionally to that of the diff pair transistors, so that they experience a differential self-heating voltage proportional to that of the diff pair transistors. This thermal voltage, , picked off from between the emitters of and is amplified and converted to a current by the variable-gain transconductance amplifier, and is fed back to the load resistors at the input of the diff pair amplifier being compensated. 65
Figure 6.7. Top-level schematic of the self-heating compensation circuit.
Power-to-Voltage Converter
The function of the PVC block is to generate a signal that is proportional to the differential power dissipation of the amplifier by performing the mathematical operation described by (5.6). The top-level schematic of the PVC block, Figure 6.8, shows that the PVC comprises a pair of cross-coupled multiplier cells, followed by a fixed-gain amplifier stage. Each multiplier block, PVCmult, is a four-quadrant Gilbert multiplier cell. Cross-coupling the outputs provides an output signal that is the difference of the multiplication product of each individual multiplier circuit. 66
Figure 6.8. Top-level schematic of the power-to-voltage converter circuit.
The top multiplier in the Figure 6.8 block diagram computes the power dissipation of one
of the diff pair transistors, by performing the following multiplication:
(6.1) The second multiplier computes the power of the other diff pair transistor:
(6.2) The input signal to the amplifier circuit, PVCamp, is the difference between (6.1) and (6.2),
(6.3) Δ which, of course, is the same as (5.6) and is proportional to the differential power dissipation of the diff pair transistors. This signal is amplified by the PVCamp block, whose output is used to modulate the power of the thermal voltage generator transistors.
A schematic of the four-quadrant multiplier cell used for the PVCmult block is shown in
Figure 6.9. Emitter follower transistors, – provide buffering and level-shifting for the input signals, which come from the diff pair node voltages indicated in Figure 6.5. The node voltages
on either side of the current-sense portion of the diff pair’s load resistors connect to inputs and . This differential current-sense voltage is buffered and amplified to a differential current by the differential pair. Diode-tied load transistors and convert the current to a / 67
voltage that is then applied to the cross-coupled diff pairs of – . The collector-emitter voltage of the diff pair transistor provides the input to the PVCmult cell. The collector-emitter voltage is buffered and then applied to the heavily-degenerated diff pair, to be multiplied / with the current-sense voltage.
Figure 6.9. Schematic of the four-quadrant multiplier circuit used in the power-to-voltage converter.
The signal at the input, the collector-emitter voltage from the diff pair, is always positive by a significant amount, so the polarity of the input to the diff pair in Figure 6.9, / as well as its output current is always positive. The current-sense signal at the input is a smaller signal, and can be zero, but it too will never be negative. The result is that the four-
quadrant multiplier is never used outside of the first quadrant. Two-quadrant multiplier circuits
were evaluated for use as the PVCmult cell, but the four-quadrant multiplier circuit of Figure 6.9
was found to exhibit superior performance in terms of linearity and, most significantly, in terms 68
of offset. Because the collector-emitter voltage input to the multiplier circuit is typically a fairly large voltage (e.g. ), the multiplier circuit will always operate in a significantly unbalanced 1 state. For the two-quadrant multiplier architectures evaluated, this fact resulted in an unacceptable offset in the circuits’ transfer characteristics.
Each of the two multiplier circuits in the power-to-voltage converter generates a signal that is proportional to the power dissipation of a single transistor. What is needed at the output of the PVC block is a signal that is proportional to the differential power dissipation of the two diff pair transistors. A signal that is proportional to differential power dissipation is obtained by cross- coupling the outputs of the PVCmult blocks, as shown in Figure 6.8, yielding an output that is the difference between the two proportional-to-power signals. This proportional-to-differential-power signal, , is amplified by by the simple, fixed-gain amplifier, PVCamp. The output of 12 the amplifier is the output of the PVC, which is applied to the collectors of the thermal voltage
generation transistor, as shown in Figure 6.7.
An additional input to the PVCmult circuit is a digital control signal, , which, when set high during the calibration procedure, forces the differential output of the PVC block to zero.
Thermal Voltage Generator
As seen in Figure 6.7, the output of the power-to-voltage converter, , drives the thermal voltage generation circuit, whose function has been described in previous chapters. The proportional-to-power signal is applied to the collectors of the thermal voltage generation transistors, and . These transistors are each connected to a constant base voltage to bias them at a current of approximately . Ideally, the bias current for these transistors would be 1 provided by transistor current sources. However, because the thermal voltage generation transistors also function as the current sources for a diff pair amplifier of the comparator circuit, there is insufficient voltage headroom to include an active current source between their emitters and the negative supply. Instead, they are simply connected to the negative supply through 69
emitter degeneration resistors. It is important to consider the effect of this configuration on the differential thermal voltage generated between the emitters of transistors and . Equation (3.21) gives the transfer function of the thermal voltage generation circuit as
(6.4) where is the thermal gain factor for the transistors, is their thermal impedance, and is the thermal voltage generation transistors’ collector current, which is now denoted with a lower- case variable to indicate the inclusion of a small-signal component of the current. The Figure 6.10 schematic of the thermal voltage generator, including the voltage sources to model the effect of self-heating-induced base-emitter voltage modulation, illustrates that, neglecting base current, the bias current can be expressed as function of the voltage across the emitter resistor:
(6.5) Any change in collector current will be small, so it is reasonable to approximate the self-heating
voltage, , as solely a function of the signal applied to the collectors of the transistors. Equation (6.5) shows that collector current will vary somewhat as the applied signal modulates transistor power dissipation. The term in (6.5) represents the base-emitter voltage, independent of any self-heating effects. The base-emitter voltage, , has a non-linear relation to collector current described by
(6.6) ln The negative sign on the term in (6.5) represents the stabilizing effect of the negative feedback provided by the emitter degeneration resistance, . 70
Figure 6.10. The thermal voltage generator with self-heating voltage sources shown to illustrate their effect on bias current.
What needs to be considered is if and how the variation in bias current will affect the
thermal voltage generated between the emitters of the transistors. That is, whether or not the
additional, non-linear terms in (6.5) will result in a non-linear transfer characteristic of the
thermal voltage generator. Collector current can be expressed as a sum of its DC and time-
varying components as
(6.7) If the time-varying terms in (6.7) can be made negligible compared to the DC terms, then the
effect of bias current variations can be assumed to be negligible as well. For a given DC collector
current, , the last term on the right-hand side of (6.7) can be made negligible if , the emitter degeneration resistor, and the DC voltage across it are made large enough. In other words, as long as the degeneration voltage is sufficiently large, transistors and will behave like constant current sources. A degeneration resistance of corresponding to a degeneration voltage of 400 Ω 71
has been found, through simulation, to result in a thermal voltage generator with a 400 sufficiently linear transfer characteristic.
A second non-ideality associated with the thermal voltage generator circuit to consider is
the effect of the finite output resistance of transistors and . As the collector voltages of these transistors is modulated by the proportional-to-power signal, , finite output resistance results in a modulation of their bias currents. This bias current modulation manifests itself at the emitters of the transistors as a signal that is linearly proportional to the proportional-to-power signal applied to the collectors. While this may at first appear to be a favorable result, increasing the thermal gain of the transistors, the component of that is due to finite output resistance of the transistors results from electrical behavior of the transistors, as opposed to thermal behavior.
This component of the signal is not band-limited by the transistors’ thermal bandwidth, but by the electrical bandwidth of the proportional-to-power signal, which lies somewhere between
the thermal bandwidth of the transistors and the signal path bandwidth of the comparator. It is
therefore desirable to maximize the ratio of the thermally-generated to electrically-generated
components of the differential voltage appearing between the emitters of and . An approximation of the electrical component of can be obtained by considering the circuit of Figure 6.10 and making two simplifying assumptions: neglect the effect of self-heating of and , and assume that bias current, , is constant. Under these assumptions, the output of the circuit becomes
,
(6.8) , ln ln
, ln 72
where the subscript of denotes the electrical portion of the output voltage. is the Early , voltage, representing the finite output impedance of the transistors. The collector-emitter voltages
in (6.8) include a DC bias voltage and the applied power signal, .
2 (6.9)
2 Equation (6.8) then becomes
(6.10) 2 , ln 2 The electrical gain of this circuit is found by differentiating (6.10) with respect to the proportional-to-power input voltage, . (6.11) , 4 4 8 4 Typically,
(6.12) 4 8 4 so (6.11) simplifies to
, 4 4 8 4 (6.13)
, This implies that the electrical gain through the thermal voltage generator circuit can be reduced
by increasing the DC collector-emitter voltage. However, because is typically negligible relative to , (6.13) shows that the circuit’s electrical gain is largely independent of the DC bias point of the transistors. However, as described by (3.21), the thermal gain of the circuit in Figure
6.10 is proportional to DC bias current, so the ratio of thermal signal to electrical signal appearing at the output of the circuit, , can be increased by increasing DC bias current, . Increasing the 73
DC bias current of the thermal voltage generator transistors, thereby increasing their power-to- voltage gain, has the added benefit of relaxing the gain requirement for the following variable- gain transconductance amplifier. In order to bias the thermal voltage generator at an adequately high current level, while limiting the additional power cost associated with the compensation circuitry, bias current is shared between the thermal voltage generator and the diff pair amplifier it helps to compensate.
Also included with the self-heating compensation circuit is a block whose function is to allow for the nulling of any offset voltages in the compensation signal path. This block,
VCSgenVthermNull, provides the bias voltages for the thermal voltage generation transistors, and in Figure 6.7. These nominally-equal bias voltages, and , are adjustable to allow for the introduction of an offset voltage between the emitters of and , as will be described in a subsequent section.
The bandwidth of the self-heating offset voltage experienced by the transistors in the diff pair amplifier and the bandwidth of the thermal voltage generated by the circuit of Figure 6.7 is determined by the thermal bandwidth of the respective transistors. In order to achieve optimal compensation, it is important that the bandwidth of these two signals, and therefore the thermal bandwidth of the two pairs of transistors be matched. Because thermal bandwidth is likely a function of transistor geometry, transistors and in Figure 6.7 have been designed with geometries equal to those of the diff pair amplifier transistors.
Variable-Gain Transconductance Amplifier
The thermal voltage generated by the circuit of Figure 6.7 is amplified and converted to a
current by a variable-gain transconductance amplifier, VthermVTA, whose top-level schematic is
shown in Figure 6.11. The first stage in the VthermVTA block is simply a voltage amplifier with
a fixed gain of . The second stage is a transconductance stage, comprising both a fixed 28 transconductance amplifier and a variable transconductance amplifier, as shown in Figure 6.12. 74
Figure 6.11. Top-level schematic of the variable-gain transconductance amplifier.
Figure 6.12. Top-level schematic of the variable portion of the variable transconductance amplifier.
The amplifier has two separate differential outputs as shown in Figure 6.11 and Figure
6.12: the compensation current, , that gets fed back to the diff pair input, and a voltage output, , which is used during the calibration procedure. The calibration voltage signal is generated by steering the feedback compensation current to a different pair of resistors, 80 Ω shown in Figure 6.12, instead of those at the diff pair input. The schematic of the circuit that provides both the variable transconductance and the steering of the compensation current for calibration, VthermVTAgmVariable, is shown in Figure 6.13. The transconductance of this stage is adjusted by the control voltage, which is generated off-chip. A pair of complementary calibration control signals, and , which are generated on-chip from the chip input 75
signal , control whether the compensation current is steered to the load resistors at the input of the amplifier being compensated, or to the load resistors shown in Figure 6.12 for calibration.
When the compensation current is to be steered for calibration, pulls the base of high, and pulls the base of low, turning on the - cross-coupled quad, while cutting off - , thereby directing the differential current from the amplifier to the calibration / resistors, where the current is converted to a voltage that can be measured off-chip at the outputs.
Figure 6.13. VthermVTAgmVariable circuit schematic. This circuit provides variable transconductance gain and also redirects the compensation current for generation of the calibration voltage.
The combination of the three separate gain blocks in the variable-gain transconductance
amplifier – the fixed-voltage-gain amplifier and the fixed- and variable-gain transconductance
amplifiers – provides an adjustable transconductance range of . 46 … 100 A control signal input to the chip, , allows for the comparator’s self-heating compensation circuitry can be disabled entirely. This is accomplished by switching off all bias currents in the variable-gain transconductance amplifier, ensuring that no compensation current is 76
generated or fed back to the amplifier input. Additionally, when disabling the compensation circuitry, the input can be switched high, to zero the differential PVC output, ensuring that no differential self-heating voltage is generated by the thermal voltage generation transistors.
Calibration Procedure
The self-heating voltage generated by the thermal voltage generation transistors is on the
order of only several millivolts at full-scale, necessitating a significant amount of gain in the
transconductance amplifier that amplifies it. The compensation signal path is therefore very
susceptible to mismatch-induced offset voltages, which may be of the same order of magnitude as
the thermal voltage itself, necessitating a procedure to null out any such offsets. This calibration
procedure begins by setting the digital input signal high, which puts the chip into calibration mode. When configured for calibration mode, two things happen: the differential output of the
PVC block is set to zero (Figure 6.9), and the compensation current generated by the variable-
gain transconductance amplifier is redirected to the output (Figure 6.13). With the PVC output zeroed, the output of the variable-transconductance amplifier that appears at the output should be zero. Any non-zero voltage at this output is due to offset voltages in the
calibration signal path. The first step in the calibration procedure is to null out these offsets,
thereby forcing the differential voltage at the output to zero. Each of the four self-heating compensation blocks on chip includes a circuit block,
VCSgenVthermNull (as seen in the self-heating compensation circuit schematic of Figure 6.7), which is controlled by an external analog input voltage, , to allow for the nulling of the offset voltage that appears at the respective output when in calibration mode. The offset nulling circuit is shown in simplified form in Figure 6.14. The control voltage input,
, differentially steers current between two diode-tied PMOS transistors in the VthermNull block shown in Figure 6.15. That current is scaled and mirrored in the 77
VCSgenVthermNull block of Figure 6.14. These circuits allow for steering bias current between the thermal voltage generation transistors and introducing an offset nulling voltage to the thermal voltage, while maintaining constant total tail current for the diff pair amplifier.
Figure 6.14. The VCSgenVthermNull circuit, which generates the bias voltages for the thermal voltage generation transistors. These bias voltages are adjustable, allowing for cancellation of offset voltages in the compensation signal path.
Figure 6.15. The VthermNull circuit, in which the control voltage, VthermOffNull steers current differentially between two current mirrors in order to adjust the bias voltage of the thermal voltage generation transistors. 78
In this first calibration step the control voltage associated with each of the four compensation blocks is adjusted until the differential voltage at the corresponding output is zero.
In addition to offsets in the compensation signal paths, there may also be mismatch-
induced offset voltages in the comparator signal path. The second step of the calibration
procedure is to null these offsets. This is accomplished by taking the chip out of calibration mode,
by setting the input signal low, and adjusting the analog control voltage until the differential comparator output is balanced. The signal controls the injection of a differential offset current at the output of the common-base input amplifiers, as shown in Figure
6.2.
After all offsets have been nulled, the third and final step of the calibration procedure is
to calibrate the gains of the variable-gain transconductance amplifiers in the self-heating
compensation blocks. These gains are controlled by externally-generated analog control voltage
inputs, . While the gain of each of the four amplifiers is individually-programmable, it is adequate to set all four gains to the same value. While evaluating the test chip a single gain-
control voltage, , has been used for all four variable-gain amplifiers. This final step of the calibration procedure involves adjusting the compensation path gain, in order to optimize the self-
heating compensation. The method used to assess the effectiveness of the compensation, thereby
allowing for adjustment of the input, will be described in the following chapter.
Power Supplies
The power supply voltages for the chip are , and ground. 2.5 2.5 On-chip bypassing, utilizing the MIM capacitors available in the 8HP process, is included from both and to ground. Damping resistors are included in series with all on-chip bypass capacitors in order to dampen any resonance between the on-chip bypassing and the inductance of 79
the bond wires bringing the power supplies onto the chip. Four separate package pins are dedicated for connecting each of the supplies, as well as ground, to the chip. There are 44 damped bypass capacitors on both the and supplies, 22 on the supply, and 26 on the supply, as illustrated in Figure 6.16.
Figure 6.16. On-chip power supply bypassing, including series resistors to dampen any resonance with bond wire inductance.
Power consumption of the different functional blocks in the comparator circuit is
summarized in Table 6.1. The table indicates the presence of only a single output amplifier
instance, when, in fact, a second output amplifier has been included on the chip to allow for the
calibration of the output supply voltage. The assumption made here is that, while not done on this
test chip, the dummy output amplifier could very easily be designed to be disabled whenever the
input is low. In other words it would only consume power when the chip was configured in CAL calibration mode.
The power consumption breakdown given in Table 6.1 clearly indicates the significant
power cost associated with this self-heating compensation scheme. As will be made clear in the
following section, there is a significant cost in terms of chip area associated with the
compensation circuitry as well. The table entries highlighted in gray represent circuit blocks
added to the comparator circuit in order to provide self-heating compensation. The incremental
power cost associated with these blocks is of a total for the entire comparator. 216 437 80
Table 6.1. Comparator power dissipation broken down by functional block.
Power/Instance Circuit Block Instances Total Power [mW] [mW] Input amplifier 37 1 37 Output amplifier 90 1 90 Comparator diff pairs 22 4 88 Bias generation 6 1 6 PVC 26 4 104 Compensation path 15 4 60 nulling circuitry VTA 13 4 52 Total self-heating - - 216 compensation circuitry Full comparator - - 437
Layout
The dimensions of the entire test chip, designed in the IBM8HP process, are 3.6 . As mentioned at the beginning of this chapter, the chip also includes a linear amplifier, 2.8 included as a risk mitigation measure, which will not be discussed here. The portion of the chip occupied by the self-heating-compensated comparator is for a total chip area 3.5 1.8 dedicated to the comparator circuit of . The entire chip layout, with functional blocks 6.3 labeled, is shown in Figure 6.17. The layout clearly illustrates the significant real estate cost associated with this self-heating compensation scheme, with the majority of the chip area dedicated to the four blocks of compensation circuitry. A photomicrograph of the full test chip is shown in Figure 6.18.
It is the transistors of the diff pair amplifiers that are responsible for the self-heating induced errors experienced by the comparator. When laying out the chip, an effort was made to layout the diff pair transistors in such a way that the differential self-heating experienced by the emitter-coupled transistors would be minimized. Each of the two transistors in each differential 81
pair amplifier is actually two transistors connected in parallel. The four transistors of each amplifier were laid out about a common centroid, as shown in Figure 6.19.
Figure 6.17. Layout of the full test chip, with the functional blocks labeled.
The layout used for the diff pair transistors, with the devices arranged about a common centroid, was also used for the thermal voltage generation transistors. This layout configuration has several advantages. First, dividing the transistors into multiple devices and placing them at a minimum spacing helps to reduce their differential thermal resistance as much as possible. Also, the layout arrangement helps desensitize the amplifier to thermal gradients that may be present across the chip due to high power dissipation in other circuits, by equalizing the effect of those gradients on both transistors of the diff pair. Similarly, mismatch due to process variation across 82
the surface of a wafer, and the chip on that wafer is minimized by ensuring that both transistors are evenly distributed along any process variation gradient.
Figure 6.18. Photomicrograph of the full test chip, shown in the same orientation as the layout of Figure 6.17.
Figure 6.19. An example of differential pair amplifier transistors laid out about a common centroid, in an effort to reduce both thermal effects and mismatch. 83
Package
The test chip has been packaged in an open-cavity, plastic, 52-pin, , QFN 8 package. The chip is bonded to a die paddle inside the package, which is exposed through the bottom of the package to be soldered to the substrate bias, . The chip is connected to the package lead frame through bond wires. Figure 6.20 shows two photographs of the QFN package.
(a) (b) Figure 6.20. Two views of the 52-pin, open-cavity, QFN package, (a) from the bottom, and (b) from the top with the lid removed, showing the bond wires connecting the chip to the lead frame.
CHAPTER 7
SIMULATION RESULTS
Simulation of the comparator circuit design, presented in the previous chapter, has been conducted with the Spectre circuit simulator in the Cadence IC design environment. Device models from IBM’s BiCMOS8HP process design kit obtained from MOSIS have been used for simulations. Two main categories of simulations have been performed to verify the performance of the self-heating compensation circuitry. First, simulations using the nominal models, that is models representing the nominal device characteristics for the process, were conducted to assess the effectiveness of the compensation circuitry at reducing self-heating-induced duty-cycle distortion (DCD) at the output of the comparator. The second main category of simulations utilized statistical process models for both worst-case corner analysis and monte-carlo statistical mismatch analysis.
This chapter will first discuss the 8HP transistor models, and, specifically, how they account for self-heating of the devices. Next, the types of simulations conducted and how the output from those simulations has been processed to evaluate the effectiveness of the self-heating compensation will be detailed, followed by a comparison of simulation results illustrating the self-heating effects experienced by the comparator with and without self-heating compensation.
Finally, the use of statistical simulations to ensure the design included adequate gain and offset adjustment ranges will be discussed briefly. 85
BiCMOS8HP HBT Self-Heating Model
The 8HP design kit utilizes VBIC (vertical bipolar inter-company) models for the npn
HBT transistors, which account for self-heating in the manner described in Chapter 2. That is, the
models use a thermal impedance network calculated for the particular device along with that
device’s power dissipation to determine the device’s temperature rise. The self-heating-induced
temperature rise is then used to modulate the transistor’s base-emitter voltage, , as shown in Figure 7.1. A transistor’s thermal bandwidth is determined by its thermal resistance, , and its thermal capacitance, . The values of and calculated by the models are dependent upon transistor geometry, as shown in Figure 2.4, however the resultant thermal time constant is
modeled by the 8HP design kit to be a constant , independent of geometry. This 1.15 corresponds to a geometry-independent thermal bandwidth of . 138.4
Figure 7.1. The IBM BiCMOS8HP transistor models treat the thermal behavior of the transistors as a first-order RC network.
As discussed in the previous chapter, optimal self-heating compensation requires that the
bandwidth of the self-heating offset voltage experienced by the transistors to be compensated be
matched by the thermal bandwidth of the compensation signal. The assumption of constant
thermal bandwidth for transistors of any geometry implies that the bandwidths of these two
signals will be matched by default. However, even if the assumption of geometry-independence
used by the models were invalid, setting the geometry of the amplifier transistors and the thermal
voltage generation transistors equal ensures that the bandwidth of the compensation signal and
that of the self-heating offset voltage are matched by design. 86
Simulation Setup
Simulations have been performed to measure the worst-case duty-cycle distortion (DCD)
at the output of the comparator circuit for a range of input signal swings and common-mode
voltages at the input to the comparator block (i.e. input amplifier output). In order to determine
the worst-case DCD, an input signal similar to that illustrated in Figure 7.2 was applied to the
input of the comparator test bench circuit. This signal is initially low for a sufficiently long period of time (i.e. many thermal time constants), to allow the circuit to reach a state of thermal equilibrium. Because this state of thermal equilibrium corresponds to the maximum differential input voltage, it also corresponds to the worst-case differential self-heating between diff pair transistors in the comparator circuit, and therefore to the worst-case self-heating-induced offset voltages for each of the circuit’s diff pair amplifiers.
Figure 7.2. Input signal used in simulation to determine worst- case duty-cycle distortion.
Following the initial thermal soaking period, the input signal begins switching with a
50% duty cycle at a frequency of , which was arbitrarily selected as a frequency that is 50 well above the thermal corner frequency of . The input signal continues to switch with a 138 50% duty cycle for many thermal time constants – long enough for the circuit to reach thermal equilibrium. Now, the state of thermal equilibrium corresponds to zero differential self-heating and zero self-heating-induced offset voltages. Once this state has been achieved, the input signal switches high and remains high for another thermal soaking period – this time in the opposite direction. By the end of this second soaking period the transistors have again reached a state of 87
worst-case differential self-heating, along with the corresponding worst-case self-heating voltages, now with opposite polarity compared to the end of the initial soaking period. Following the second soaking period, the input again begins switching at with a 50% duty cycle 50 until the transistors have once again reached a state of thermal equilibrium.
This input signal results in self-heating-induced offset voltages that sweep over their entire range for the given input signal amplitude. Following the initial soaking period, the differential self-heating voltages for each of the comparator’s diff pairs are at their maximum negative value. As the input signal switches with a 50% duty cycle, the self-heating voltages exponentially decay toward zero at a rate dictated by the thermal time constant of the transistors.
The second soaking period results in a maximum positive self-heating voltage, which also exponentially decays toward zero as the input resumes switching. The circuit behaves symmetrically following the two soaking periods, with all self-heating-related quantities having equal magnitude but opposite polarity. In practice, it is therefore not necessary to apply both soaking periods and subsequent switching periods to the input in order to characterize the circuit; applying either half of the signal depicted in Figure 7.2 is sufficient. The first half of the signal, including the negative soaking period, was the input signal used for assessing self-heating effects through simulation.
The input and output signals shown in Figure 7.3 correspond to the first few switching periods following the initial thermal soaking period illustrated in Figure 7.2. This is the point at which the self-heating offset voltages are at their maximum negative values, which, as illustrated in Figure 4.4 results in a delay of the switching instant corresponding to a rising edge and an advance of the switching instant corresponding to a falling edge. The result of the combined timing shifts is a shrinking of the positive pulse widths and the corresponding reduction of the duty cycle at the output (i.e. duty-cycle distortion). 88
Figure 7.3. Input and output signals corresponding to the first few periods following the initial soaking period illustrated in Figure 7.2.
Figure 7.3 illustrates how the output signal obtained from simulation is used to calculate
duty-cycle distortion. The input signal duty cycle is 50%, so all input pulse widths – both positive
and negative – are the same, . The output signal’s duty cycle is initially less than 50%, and the positive pulse widths are less than the negative pulse widths. DCD is calculated pulse-by- pulse. That is, for each output pulse – both positive and negative – the current DCD value is computed as
(7.1) Because the positive output pulses are narrower than those at the input, and the negative output
pulses are wider, the calculated DCD values oscillate between negative and positive values while
decaying from a maximum initial amplitude toward zero as the circuit moves toward thermal
equilibrium. This behavior is illustrated in Figure 7.4, which shows the simulated DCD at the
output of a comparator circuit without any self-heating compensation. The input signal in this
case was the first half of the signal shown in Figure 7.2. That is, after an initial thermal soaking,
the input began switching at with a 50% duty cycle and risetimes, and 50 200 continued to switch for several (roughly seven, in this case) thermal time constants. The second
soaking period and subsequent switching period have been excluded from this simulation. 89
Figure 7.4. Duty-cycle distortion at the output of an uncompensated comparator, showing oscillation between negative and positive values, as well as the exponential decay toward zero as the transistors approach thermal equilibrium.
The initial DCD value observed for this simulation is , corresponding to the 40 amount by which the first positive pulse width at the output differs from the input pulse widths.
The measured DCD values alternate between negative and positive, corresponding to positive and negative pulse widths, respectively. The exponential decay of the output DCD magnitude, as the transistors approach thermal equilibrium, is clearly visible in Figure 7.4. The rate of this decay is determined by the thermal time constant of the transistors, which, for the transistor models used here, is . In fact, the thermal time constant of the transistors can be inferred from the ~1.15 exponential envelope of the DCD plot. This illustrates how DCD measurements can be used as a means of characterizing the thermal behavior of a circuit, by providing an indirect measurement of the circuit’s thermal step response.
Even though the simulation that produced the DCD plot of Figure 7.4 only included a single, negative thermal soaking period, it does, in fact, account for the full range of self-heating- 90
induced timing error experienced by the comparator. Because each DCD measurement is a pulse width error measurement, it takes into account the timing errors associated with both the positive- and negative-going edges, the former being delayed, and the latter advanced. The maximum total
DCD-related timing error that will be observed at the output of the comparator will, therefore, be the maximum absolute value DCD values shown on the plot. This worst-case value will always be the DCD value calculated for the initial pulse following a thermal soaking period, which corresponds to the worst-case self-heating experienced by the circuit.
(7.2) | | For the example shown, the total DCD is . Because the worst-case DCD is determined ~40 by the error of the first pulse width following a thermal soaking period, not only is it possible to apply only half of the signal shown in Figure 7.2, in order to determine worst-case DCD it is only necessary to apply a single input pulse following an initial soaking period.
In addition to computing and plotting DCD, it is also illustrative to view the effect of self-heating at the comparator output in the form of an eye diagram, for which the input signal is used as the timing reference. If the full input signal shown in Figure 7.2 is applied to the circuit, and all transitions of the input and output signals are superimposed, an eye diagram plot is generated that shows the full range of timing drift observed at the comparator output. Figure 7.5 shows an example eye diagram generated with the same uncompensated comparator circuit used to generate the DCD plot of Figure 7.4. Because the input signal is used as the timing reference for the generation of the eye diagram, its timing is invariant from cycle to cycle, and it exhibits no drift. The output signal, however, displays significant timing drift relative to the input signal. The total DCD can be measured from this plot as the full range of timing drift at the transitions. For this example, the eye diagram shows the total DCD to be , which agrees with the value ~40 obtained from the DCD plot of Figure 7.4. 91
Figure 7.5. Eye diagram of the output from an uncompensated comparator circuit. Total DCD can be measured from the eye diagram as shown.
Simulation Suite
The assessment tools presented in the preceding section, DCD and eye diagrams, have
been applied to evaluate the effectiveness of the comparator’s self-heating compensation circuitry
for a range of input signal swings and common-mode voltages. Peak-to-peak differential voltage
swing at the input has been varied over a range of . The common-mode input 20 … 500 voltage has been varied not at the input to the input amplifier model, where it would have little effect on the common-mode level at the output of that model, but at the input to the comparator block itself. This was accomplished by varying the input supply voltage, , over the range of , resulting in a common-mode range at the input to the comparator block of 2.1 …2.6 . While the common base input stage minimizes common-mode variation at its 1.5 …2.0 output, an effort was made to intentionally vary the common-mode voltage at that point in the
circuit in order to assess the ability of the compensation circuitry to accommodate such variation. 92
This is particularly important for applications where the comparator itself may see widely varying common-mode input levels.
In order to evaluate the self-heating compensation scheme proposed here, the comparator circuit has been simulated in three distinct configurations:
1) NoComp : the comparator’s self-heating compensation circuitry has been
completely disabled
2) FullComp: the comparator circuit is compensated using the technique and
circuits described in the previous chapters
3) SimpleComp: the simplified self-heating compensation scheme described for
use with purely analog or purely digital circuits is applied to the mixed-signal
comparator circuit
The third configuration does not compute a proportional-to-power signal, but instead uses the
output signal from each diff pair as an approximation to the differential power dissipation of that
amplifier’s transistors. In terms of the circuit schematic, this third configuration corresponds to
the power-to-voltage converter (PVC) cell, shown in Figure 6.7, being replaced with a cell that
simply level-shifts and , passes them through to its output, and applies them to the collectors of the thermal voltage generating transistors. This simplified compensation scheme is most representative of the types of compensation typically applied in practice, so it is the comparison between the FullComp and SimpleComp circuits that is most relevant. While the
SimpleComp configuration provides the most relevant comparison to the FullComp configuration, it was not included on the test chip due to die space limitations, and as an effort to limit circuit complexity in order to decrease the risk associated with the chip design.
Each of the three circuit configurations described above has been simulated for the following input signal parameters and ranges of amplitude and input supply voltage: 93
• 50 • 200 • 20 , 50 , 100 , 200 , 500 • 2.1 , 2.35 , 2.6 • 0
Each simulation yielded a maximum DCD value, which was the metric used to assess the effect of self-heating and to judge the effectiveness of the particular self-heating compensation circuitry, if any, applied to the comparator circuit.
Simulation Results
Maximum DCD values versus peak-to-peak input amplitude for three different input
supply voltages are plotted in Figure 7.6 for each of the three circuit configurations. Note that the
DCD axis is logarithmic in order to accommodate the large reduction in DCD resulting from the
addition of self-heating compensation circuitry. The input rise time in all simulations is held
constant at . Input slew rate is therefore proportional to input amplitude, resulting in all 200 three circuit configurations following a general trend of decreasing DCD with increasing input
amplitude. Duty-cycle distortion for the uncompensated comparator circuit ranges from 4.3 to over all simulated cases. Addition of the full compensation circuit reduces DCD to a 53 range of only to , representing a reduction of DCD by a well over an order of 264 1.53 magnitude. The simplified compensation scheme also displays markedly lower DCD than the
uncompensated circuit, with a range of to over all simulations. 289 6.6 94
Figure 7.6. Maximum DCD vs. peak-to-peak input amplitude for each of the three circuit configurations at three input common-mode levels. The DCD values that correspond to the input signals used for calibration of each of the compensated circuits are indicated on the plot.
Both configurations of the comparator circuit that include self-heating compensation circuitry require calibration of the variable-gain amplifier in the thermal compensation signal feedback path. For both the full compensation and simplified compensation cases, calibration was performed to minimize the DCD present at the output for a input signal with a 200 common-mode input voltage of . The simulated DCD points resulting from the same input 1.75 signal used for calibration are indicated on the Figure 7.6 plot. The comparator circuit utilizing 95
the simplified compensation scheme exhibits DCD performance comparable to that of the fully- compensated circuit for the input signal condition at which it was calibrated – but not consistently over a range of input conditions. As the input signal characteristics deviate from the calibration point, performance of the circuit utilizing the simplified compensation scheme degrades significantly. The simulated DCD for the fully-compensated comparator circuit is significantly lower over the full range of input signals, demonstrating its superior ability to accommodate input signal variation.
The simulation results presented as maximum DCD values in Figure 7.6 can alternatively be viewed as eye diagrams, in order to illustrate the effect of self-heating on the timing of the output waveform. Each of the following eye diagrams corresponds to an input signal with an amplitude of and a rise time of at a particular common-mode voltage. Figure 200 200 7.7 compares the output eye diagram of a fully-compensated comparator to that of an
uncompensated comparator. This figure clearly illustrates both the need for self-heating
compensation in a comparator circuit of this type, as well as the effectiveness of the
compensation circuitry at reducing timing variation at the output. Addition of the compensation
circuitry to the comparator circuit reduces output DCD from to (for 13.43 354 ). 1.75 The eye diagrams in Figure 7.8 through Figure 7.10 compare the effectiveness of the full
self-heating compensation circuit (FullComp), using the proportional-to-power signal generated
by the PVC cell, to that of the greatly simplified compensation circuit (SimpleComp), which uses
the diff pair’s output voltage as an approximation of its differential power dissipation. Figure 7.8
shows the output eye diagrams for both compensation circuits with an input common-mode
voltage of , which is the point at which both compensation circuits were calibrated. The 1.75 simplified circuit in this case performs nearly identically to the FullComp circuit, reducing DCD 96
to only , compared to , a difference considered negligible and attributable to 458 354 the manual and, therefore, imperfect calibration of both circuits.
Figure 7.7. Comparator output eye diagram for an uncompensated comparator and a comparator utilizing the self-heating compensation scheme presented here.
Figure 7.8. Output eye diagram for comparators utilizing the full compensation circuitry and the simplified compensation circuitry. The input common-mode voltage is 1.75 V, which is the voltage at which each comparator was calibrated. 97
The eye diagrams of Figure 7.9 and Figure 7.10 illustrate how the performance of the simplified compensation circuitry degrades significantly as the input common-mode voltage moves away from the point at which the compensation circuitry was calibrated. The full compensation circuit proves to be significantly better at accommodating common-mode variation, though its performance does degrade slightly as the input common-mode varies. Sensitivity to input common-mode voltage for the FullComp circuit is due primarily to nonlinearity in the PVC cell, and could be improved at the expense of increased power dissipation.
Figure 7.9. Comparator output eye diagram for comparators utilizing the full compensation circuitry and the simplified compensation circuitry with an input common-mode voltage of 1.5 V. 98
Figure 7.10. Comparator output eye diagram for comparators utilizing the full compensation circuitry and the simplified compensation circuitry with an input common-mode voltage of 2 V.
Simulations Accounting for Process Variation and Mismatch
The 8HP device models include statistical information, allowing for simulations that predict circuit performance while accounting for both process variation (i.e. variation from one die, wafer, or fabrication run to another) and mismatch (i.e. variation between nominally-matched components on a single chip). To ensure functionality of the test chip, it was necessary to design all adjustable circuitry, namely the variable-gain transconductance amplifiers (VTAs) and the offset-nulling circuits in the compensation paths and at the input amplifier, with sufficient range to accommodate both worst-case process variation and worst-case mismatch conditions.
Simulations over Process
The variable-gain transconductance amplifiers are the adjustable circuit blocks most susceptible to process variation, particularly resistivity variation of the resistors, as that affects the bias currents in the amplifiers, thereby affecting their gains. Simulations over all worst-case process corners were performed, and in each case the VTAs were calibrated to provide optimal 99
self-heating compensation; that is, VTA gain was adjusted to minimize DCD at the comparator output. The gain range of the VTAs was designed such that the gain control signal did not need to be set to its upper or lower limits at any worst-case process corners.
Monte-Carlo Mismatch Simulations
The offset-nulling circuitry, both in the self-heating compensation blocks and in the input
amplifier, is provided to eliminate voltage offsets in both the compensation and signal paths that
result from mismatch between nominally-matched components, transistors and resistors, on the
chip. In order to assess whether these circuits are designed with sufficient adjustable range,
statistical Monte-Carlo simulations were performed, in which component model parameters were
varied randomly according to their statistical models. For all simulations, a sample size of 200
randomly generated mismatch corners was used. Monte-Carlo simulations don’t necessarily
identify the absolute worst-case mismatch corner, however, such a worst-case matching analysis
would tend to over-predict the effects of mismatch, resulting in significantly over-designed
circuitry. Monte-Carlo simulations provide a more realistic prediction of the range of mismatch
likely to be seen on any given chip. Additionally, layout techniques employed to improve
matching, such as laying out matched devices about common centroids, ensures that statistical
Monte-Carlo simulations provide an adequately conservative prediction of the effects of
mismatch.
Prior to Monte-Carlo mismatch analysis, simulations were run using the nominal device
models (i.e. perfectly matched devices), in order to calibrate the gain of the VTAs such that DCD
calculated at the output of the comparator was minimized. Once calibrated at the nominal corner,
200 Monte-Carlo simulation runs were performed. For each of the 200 Monte-Carlo runs, DCD
was calculated at the output of the comparator. The maximum DCD results from one set of 200
Monte-Carlo simulations are shown in Figure 7.11. From these DCD results, several Monte-
Carlo corners corresponding to the worst-case calculated DCD values, circled in Figure 7.11, 100
were selected, and the model parameters used during those runs were saved as a unique Monte-
Carlo corner, or model parameter set, that could be used for further simulations. For each of these
selected corners, a simulated calibration of the comparator circuit was performed. This calibration
entailed three separate simulations, each of which swept a particular control voltage (or voltages)
over its range, allowing the identification of the value of that voltage that eliminated the relevant
offset.
Figure 7.11. DCD results from 200 Monte-Carlo simulations. The model sets corresponding to the circled cases were saved for simulated calibration of the self-heating compensation circuitry.
The purpose of the first calibration simulation step was to null out any offset voltages
present in each of the four self-heating compensation paths. In this simulation, the input was set high and each of the four signals was swept over their full range. 2 Monitoring the outputs allowed the value of the voltage that eliminated any compensation-path offset to be identified. These were the calibrated values of the
control voltages, and the voltages that these inputs were set to for any further simulations using the models of that particular Monte-Carlo corner. Each of the four outputs over the full range of the control voltages for one of the Monte-Carlo corner 101
simulations are shown in Figure 7.12. The value of each control voltage that nulled the mismatch-
induced offset is indicated on each plot.
Figure 7.12. Mismatch corner simulation of the calibration of the voltages. The calibrated values of each of the control voltages are shown.
The purpose of the second calibration simulation step was to eliminate any offset voltage
present in the comparator signal path. In this second calibration simulation, the output is brought low, and the voltages were set to their calibrated values determined in the previous calibration simulation. In this step of the simulated calibration, the control signal was swept over its full range, while monitoring the comparator output. The value of
the voltage that resulted in a balanced comparator output was identified as the calibrated value for the control voltage, and that voltage was set to this value for 102
any further simulations using this model set. The result of this simulation, with the calibrated
value of indicated on the plot, is shown in Figure 7.13.
Figure 7.13. Mismatch corner simulation of the calibration of the VinOffNull voltage. The calibrated value of the control voltage is indicated on the plot.
The final step in the simulated calibration of the comparator was to adjust the control voltage, setting the gain of the VTAs to minimize the DCD calculated at the comparator output. This was an iterative procedure, in which successive sets of transient simulations were run, where, for each set, the control voltage was stepped over successively smaller ranges, allowing the optimal value of the voltage to be approximated. Figure 7.14 shows the result of calibration for one of the Monte-Carlo corner cases. The DCD calculated at the output of the comparator is plotted as a function of the gain control voltage, . What is important here is that an optimal value lies within the adjustable gain range, as is true of the case
shown in Figure 7.14. 103
Figure 7.14. Simulated calibration of the self-heating compensation path amplifiers at a selected Monte-Carlo mismatch corner. An optimum lies well within the adjustable gain range.
This three-step, simulated calibration procedure was repeated for each of the selected
Monte-Carlo corner cases. The purpose being to ensure that, at least over the selected mismatch cases, all adjustable offset nulling and gain blocks had sufficient range to allow for calibration of the comparator’s self-heating compensation circuitry.
CHAPTER 8
MEASUREMENT RESULTS
The comparator test chip was mounted on a printed circuit board and duty-cycle distortion (DCD) measurements were taken to evaluate the effectiveness of the self-heating compensation circuitry. The measurement setup used, including the printed circuit board and the measurement instruments used will be detailed in the first section of this chapter. Next, DCD measurements of the uncompensated comparator circuit will be presented, followed by the initial
DCD measurements made of the comparator with the compensation circuitry enabled. Initial measurements indicated that the gain of the variable-gain amplifiers in the compensation paths was too high, even when adjusted to its minimum value. A hypothesis as to why this was the case will be discussed, and the technique used to force the gain of the variable-gain amplifiers below their adjustable range will be explained. Finally, DCD measurements for the compensated comparator chip with the gains of the compensation-path amplifiers adequately reduced will be presented.
Measurement Setup
A four-layer printed circuit board (PCB) was designed and fabricated for the evaluation of the test chip. The test board, shown in Figure 8.1, includes all necessary circuitry for providing power supplies, analog control voltages, digital control signals, and connection of input and output signals to the chip. The two outer layers of the board are both used for signal routing, the second layer from the top is a ground plane, and the third layer down is dedicated for power 105
planes for each of the chip’s four required supplies: , , , and . Comparator inputs and outputs, as well as inputs and outputs to the calibration output amplifier, and to the
linear amplifier, connect to the chip through edge-launch SMA connectors and transmission 50Ω lines. The transmission lines are on the outer layer of the board and are referenced to a ground
plane on the second layer in from the top of the board. These transmission lines are widely
spaced, and mostly uncoupled, at the SMA connectors at the edge of the board. However, the
pin pitch on the QFN package requires the spacing of these lines to reduce down 0.5 significantly, resulting in tight coupling between the transmission lines in the vicinity of the chip.
ADS Momentum was employed in the design of these transmission lines to ensure that, when driven differentially, there were no significant impedance discontinuities to cause reflections of signals on the lines.
Figure 8.1. Test board used for the evaluation of the comparator IC. 106
The test setup used for evaluation of the comparator chip is depicted by the block
diagram of Figure 8.2. A differential input signal was provided by an Agilent 8131A 50 pulse generator, whose output was gated by a low-frequency square wave, coming from a
function generator. Gating the output of the 8131A provided an input signal similar to the first
half of the signal shown in Figure 7.2. When the gate signal input to the pulse generator is low, its
differential output is held in a low state, providing the comparator with a thermal soaking period.
Pulse generator outputs connected to the board via low-loss SMA cables.
Figure 8.2. Test setup used for characterization of the comparator chip.
Both the input and output signals to the comparator chip were measured with an Agilent
DSO91304A , real-time oscilloscope. The differential input signal was 13 40 / measured near the chip using an Agilent 1169A differential active probe amplifier with 12 an N5381A solder-in probe tip, as shown in Figure 8.3. The output signals were cabled directly to
the scope through low-loss SMA cables, where the differential output signal was calculated as the
difference between channel 2 and channel 4. The entire test setup is shown in Figure 8.4. 107
Figure 8.3. The differential comparator input signal was probed with an Agilent N5381A solder-in probe tip connected to an 1169A active probe amplifier.
Figure 8.4. Test setup used for characterization of the comparator IC.
The oscilloscope was set to trigger on the first rising edge of the input signal following the thermal soaking period. Following this trigger event, of differential input and output 10 108
signal data were acquired at a sample rate of . For a input signal, a 40 / 50 10 acquisition corresponds to periods. Waveform data were averaged on the scope over 256 500 consecutive acquisitions, saved to a file, and imported into MATLAB where they were used to
calculate the DCD present at the output of the comparator.
To determine DCD from measured input and output signals, the width of each of the
roughly acquired positive and negative pulses had to be calculated for both the input and 1000 output signals. Calculating pulse widths required accurately determining the times of each of the signals’ zero-crossings, which was done by linearly interpolating between the near-zero samples in the waveform data. Pulse widths were calculated as the time difference between adjacent zero- crossings, and DCD was calculated as the difference between each input and output pulse width, as illustrated in Figure 7.3.
Uncompensated Comparator
Using the method described above, DCD was measured for the comparator circuit with
its self-heating compensation circuitry disabled. Measured DCD corresponding to a 200 input signal and an input common-mode voltage of is shown in Figure 8.5. The maximum 1.75 DCD for this case is . The measured DCD shows the characteristic polarity oscillation 13.2 as well as the expected exponential decay toward zero as the chip approaches thermal
equilibrium. The polarity oscillation of the measured DCD is due to a self-heating-induced duty
cycle reduction; the negative thermal soaking period induces negative self-heating voltages,
resulting in a decrease in positive pulse widths and a corresponding increase in negative pulse
widths. 109
Figure 8.5. Measured DCD for the uncompensated comparator circuit.
Figure 8.6. Approximation of the thermal time constants by fitting a sum of exponentials to the envelope of the measured DCD. 110
The envelope of the decaying DCD plot of Figure 8.5 provides insight into the thermal
behavior of the transistors on the chip. Equations (4.4), (4.6), and (4.8) show that the DCD
resulting from a differential pair experiencing self-heating is proportional to the differential
temperature between the two amplifier transistors. So, the transient response of the measured
DCD shown in Figure 8.5 will be proportional to the differential self-heating experienced by the
comparator transistors. The transistor models of the 8HP design kit set the thermal time constant
to a constant , independent of geometry or interconnect, which implies that the measured 1 DCD and the differential self-heating could be expressed as
(8.1) Δ | | . Fitting a curve to the envelope of the DCD decay, as is done in Figure 8.6, showed that for the particular transistors used in the comparator circuit, a second-order, dual-time-constant model provided a better fit to the observed behavior.
(8.2) Δ | | Time constants of and , significantly faster than suggested by 36 147 the models, provide a good fit to the observed behavior.
Figure 8.7 compares the maximum measured and simulated DCD values for the
uncompensated comparator for a range of input signal swings and common-mode voltages. The
maximum DCD value, which occurs immediately following a thermal soaking period, when
transistor self-heating has reached steady state, so the reasonably good agreement between
measurement and simulation indicates similar agreement between the modeled and actual thermal
resistances of the diff pair transistors. The thermal time constant is determined by the product of
the thermal resistance and capacitance, so, while the agreement shown in Figure 8.7 suggests
reasonable agreement between modeled and actual thermal resistances, the large time-constant
discrepancy implies a significant mismatch between modeled and actual thermal capacitances. 111
Figure 8.7. Comparison of maximum measured vs. simulated DCD for the uncompensated comparator.
Compensated Comparator – Initial Measurements
As described in the previous two chapters, the variable-gain transconductance amplifiers
(VTA) in each compensation path were designed to have more than enough adjustable gain range
to accommodate any potential process variation. However, initial DCD measurements for the
self-heating-compensated comparator indicated that, even with the gain-control voltage, , set to its minimum level, the compensation path gain was too high. Figure 8.8 compares measured
DCD from the uncompensated comparator to both measured and simulated DCD for the compensated comparator. DCD for the compensated comparator in Figure 8.8 was measured with
at its minimum setting. The opposite polarity of the measured DCD for the compensated and uncompensated comparators indicates that, even at the minimum gain setting, the circuit is over-compensated, suggesting that the gain of the compensation paths was higher than intended. 112
Figure 8.8. Comparison of measured DCD for the uncompensated and compensated cases, along with the DCD predicted by simulation for the compensated comparator.
Measurements of the DC transfer characteristic between the inputs and the corresponding outputs indicated that the adjustable gain range of the VTAs was as designed for. The other two gain components in the compensation path are the power-to-voltage converter (PVC) and the thermal-voltage-generation transistors. While the gain of the PVC is not directly observable, all other observable amplifiers on the chip had gains within the expected range, giving no reason to believe that the PVC gain was significantly higher than intended.
It is suspected that the excessively-high compensation path gain can be attributed to a thermal gain mismatch, that is, a thermal resistance mismatch, between the diff pair transistors and the thermal-voltage-generation transistors. The over-compensation observed in Figure 8.8 suggests that the thermal resistance of the thermal-voltage-generation transistors is higher than that of the diff pair transistors. 113
To test this hypothesis, simulations were conducted in which the thermal-voltage- generation transistors were assigned a modified transistor model, in which the thermal resistance had been increased. It was found that a 40% increase in the thermal resistance of the thermal- voltage-generation transistors did a reasonable job of explaining the measured DCD values, as is illustrated by the plot of Figure 8.9.
It is suspected that, while the geometries of the diff pair and thermal-voltage-generation transistors are identical, a thermal resistance mismatch could easily be explained by different layout configurations, and, in particular, the different metal-layer connections of the different transistors. The layouts of these two pairs of transistors are shown in Figure 8.10 and Figure 8.11.
The second-metal-layer wiring connecting the emitters of all four diff pair transistors is highlighted in magenta on the layout of Figure 8.10. In contrast, the layout in Figure 8.11 shows that the emitters of the thermal-voltage-generation transistors, whose connections are highlighted in magenta and yellow, are not connected together. It is believed that the direct and substantial emitter connection between transistors in the diff pair results in a reduction in differential thermal resistance between these transistors as compared to the thermal-voltage generation transistors. 114
Figure 8.9. Disagreement between measured and simulated DCD values for the compensated case explained by a simulation in which the thermal resistances of the thermal-voltage- generation transistors is increased by 40% relative to the diff pair transistors.
A differential thermal resistance mismatch between diff pair transistors and thermal- voltage-generation transistors equates to a thermal gain mismatch between these devices. Higher thermal resistance of the thermal-voltage-generation transistors means that the nominal compensation path gain will be higher than necessary to compensate the self-heating of the differential pair. If the adjustable gain range is not sufficient to accommodate the thermal resistance discrepancy, the diff pair amplifier will be over-compensated against self-heating, even at the minimum gain setting, as the measured DCD in Figure 8.8 and Figure 8.9 shows. 115
Figure 8.10. Layout of the diff pair transistors showing direct connection of all four emitters with metal-layer-2 interconnect, highlighted in magenta.
Figure 8.11. Layout of the thermal-voltage-generation transistors with emitter connections highlighted. There is no direct connection between the emitters of these devices. 116
The difference in emitter wiring between the two pairs of transistors shown in Figure
8.10 and Figure 8.11 is also illustrated in Figure 8.12 with a simplified cross-sectional view of each pair of transistors. It is reasonable to suspect that the direct coupling of the emitters through second-layer metal would significantly reduce the differential thermal resistance between the transistors of the diff pair amplifier.
(a)
(b)
Figure 8.12. Simplified cross-sectional representation of (a) transistors in the diff pair amplifier and (b) the thermal- voltage-generation transistors.
Compensated Comparator – Reduced Gain
A digital control input to the chip, , allows for the self-heating compensation circuitry to be completely disabled by controlling the CMOS switch shown in Figure 8.13. When is 117
low ( ), a bias voltage is connected to the base of a current source transistor, as shown in 2.5 Figure 8.13, and the VTA is biased on. When is high ( ), the base of the current source 0 transistor is switched to the negative supply, and the VTA is powered down. By varying the signal applied to the input between its logic low and logic high levels, it was possible to pull the VTA bias voltage partially toward the negative supply, reducing the bias of the VTA gain stages, thereby reducing the compensation path gain to a level that allowed for calibration of the self-heating compensation circuitry. In addition to the desired gain reduction obtained by decreasing the VTA bias, the linearity of the VTA amplifier stages can be expected to decrease as well, affecting the performance of the self-heating compensation circuitry for large signal swings.
Because the signal swing at the inputs of all but the first diff pair in the comparator is limited, any reduction in linearity would be expected to have the most significant impact on compensation of the first diff pair in the comparator circuit.
Figure 8.13. Disable switch for the VTA current sources.
After reducing VTA gain to an acceptable level by appropriately adjusting the voltage, the comparator was calibrated to null out any offsets and to fine tune the VTA gain to optimize compensation. A full suite of DCD measurements were then acquired for the compensated comparator. An example of one DCD measurement is shown in Figure 8.14, which 118
compares DCD for the compensated and uncompensated comparators for a input and an 50 input common-mode voltage of . 1.75
Figure 8.14. Comparison of measured DCD for the uncompensated and compensated comparators for a input and a input common-mode voltage. .
Measured DCD results for the full suite of input signal parameters are summarized in
Figure 8.15. It can be seen that the compensation circuitry is effective at significantly reducing
self-heating-induced timing errors, and at maintaining effective compensation over a range of
input common-mode voltages. Note that, as for the simulation results in the previous chapter,
DCD is plotted on a logarithmic scale. The self-heating compensation circuitry reduces maximum
DCD by more than at the smallest input signal amplitude of , where input signal 80% 20 slew rate is lowest. At the calibration point of a input, DCD is reduced by 200 approximately . At the largest input signal of , where DCD naturally decreases, 75% 500 due to increased input slew rate, maximum DCD for the compensated comparator is observed to 119
actually increase a bit above DCD at the calibration point. This increase is attributable to the fact
that the compensation circuitry was calibrated for inputs, combined with some non- 200 linearity of the PVC and compensation path amplifiers. This effect was not observed in simulation, and is likely due to the reduction in linearity of the VTA resulting from lowering the bias current of these amplifiers in order to decrease their gain. Even with the decreased effectiveness of the self-heating compensation for larger input signals, the compensated comparator still reduces maximum DCD at this input amplitude by approximately . 40%
Figure 8.15. Summary of maximum measured DCD at the output of the comparator over a range of input signal swings and common-mode voltages.
The DCD values reported in Figure 8.15 were each calculated from an average of 16
separate DCD measurements. The variability of these measurements is illustrated in the plots of
Figure 8.16 through Figure 8.18. The error bars represent one standard deviation of DCD 120
variability. As can be expected, measurement uncertainty decreases for larger input signal swings, as input signal-to-noise ratio increases.
Figure 8.16. DCD vs. input signal amplitude for Vincm = 1.5 V.
Figure 8.17. DCD vs. input signal amplitude for Vincm = 1.75 V. 121
Figure 8.18. DCD vs. input signal amplitude for Vincm = 2.0 V.
As was illustrated with the simulation data of the previous chapter, the comparator output
can be used to generate an eye diagram as a means to illustrate the effectiveness of the self-
heating compensation. Eye diagrams comparing the self-heating-induced timing variation
measured at the output of the comparator for the compensated and uncompensated cases are
shown in Figure 8.19 and Figure 8.20. In both cases, the output signal is plotted using the input
signal as a timing reference. The eye diagram corresponding to a input, Figure 8.19, 50 shows that the self-heating compensation reduces total DCD from to . At 38 5.3 , Figure 8.20, compensation reduces DCD from to . 200 13.2 2.4 122
Figure 8.19. The output of the uncompensated and compensated comparator circuits plotted as an eye diagram, using the input signal as a timing reference. Input signal amplitude is .
Figure 8.20. Output eye diagram for the uncompensated and compensated comparators for a input signal. CHAPTER 9
CONCLUSION AND FUTURE WORK
A self-heating compensation scheme for bipolar integrated comparator circuits has been designed, simulated, and implemented in a SiGe HBT process. This compensation scheme differs from prior work addressing self-heating-induced errors in comparator circuits, in that it is applicable to asynchronous, i.e., non-clocked, comparator circuits. It also represents an improvement over simpler compensation schemes commonly applied to non-clocked comparators, in that it is insensitive to input signal swing and common-mode variation. The key element of the compensation circuitry presented here that enables these improvements is a power- to-voltage converter (PVC) circuit. The proportional-to-differential-power signal generated by the
PVC enables the generation of a self-heating compensation signal that provides effective compensation over a large range of input signal conditions.
A test chip, including a comparator circuit and the self-heating compensation circuitry, has been fabricated in IBM’s BiCMOS8HP SiGe process. Evaluation of the test chip revealed that, even at the minimum compensation-path gain setting, the comparator circuit was over- compensated. It is suspected that the over-compensation is due to thermal resistance mismatch between the amplifier transistors and the compensation transistors. Simulations with selectively modified transistor self-heating models have been presented which support this hypothesis. It is suspected that thermal resistance mismatch is due to different interconnect configurations of the two pairs of transistors.
A work-around was identified to reduce the compensation path gain below the lower end of its adjustable range, allowing for calibration of the self-heating compensation circuitry. 124
Measurements of DCD at the comparator output, presented for the circuit with compensation path gain adequately reduced, have shown that the compensation scheme provides effective self- heating compensation over a wide range of input signal swings and common-mode levels. While costly in terms of both power and chip area, the compensation circuitry presented here could enable the design of comparator circuits with unprecedented immunity to the timing errors caused by self-heating.
Future Work
Self-heating models included with the design kit transistor simulation models utilize thermal resistances and capacitances that vary with device geometry. The models do not, however, account for the thermal effects of the metal-layer interconnects between transistors. It is suspected that metal interconnect between pairs of transistors would significantly lower the differential thermal resistance between those devices, effectively lowering the amount of differential self-heating they experience. This is the explanation proposed here for the excessive self-heating compensation initially measured. This hypothesis has been supported by simulations, but has by no means been verified with certainty, suggesting an opportunity for future research in this area.
Future work to investigate the effects of transistor interconnect on differential self- heating could provide valuable knowledge for circuit designers implementing self-heating- compensated circuits, while relying on incomplete self-heating models. There is opportunity for both computational and experimental work in this area. Computationally, much insight could be gained from transient thermal simulations of pairs of transistors connected in various configurations. Such simulations could be performed in a simulator such as COMSOL
Multiphysics. The computational work could be paired with experimental work comprising the design of a test chip, possibly in the BiCMOS8HP process, on which the same suite of transistor 125
pairs in various configurations would be fabricated, allowing for the evaluation of the effects of interconnect on differential self-heating and comparison to numerical findings. 126
REFERENCES
[1] Robert M. Fox, Sang-Gug Lee, and David T. Zweidinger, "The Effects of BJT Self-Heating
on Circuit Behavior," IEEE Journal of Solid-State Circuits , vol. 28, pp. 678-685, June 1993.
[2] David T. Zweidinger, Sang-Gug Lee, and Robert M. Fox, "Compact Modeling of BJT Self-
Heating in SPICE," IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems , vol. 12, pp. 1368-1375, September 1993.
[3] Kamal R. Sinha, Ronald L. Carter, Howard T. Russell, and Alan W. Davis, "Impact of Self-
Heating on Frequency Response of Current Mirrors in Bipolar Technology," in 2008 IEEE
Region 5 Conference , Kansas City, MO, 2008.
[4] Kamal R. Sinha, Xuesong Xie, Ronald L. Carter, W. Alan Davis, and Howard T. Russell,
"Thermal Effects in Current Feedback Operational Amplifiers in Bipolar Technology," in
2008 IEEE Region 5 Conference , Kansas City, MO, ? 2008.
[5] Paul R. Gray and Meyer Robert G., Analysis and Design of Analog Integrated Circuits , 3rd
ed. New York: John Wiley & Sons, 1993.
[6] Keh-Chung Wang et al., Heating Effects on the Accuracy of HBT Voltage Comparators,
August 1987.
[7] Pankaj Kataria, "Thermal Tail Compensation," US 7,504,886 B2, March 17, 2009.
127
[8] Mihai Marcu, Sriram Durbha, and Sanjeev Gupta, "Duty-Cycle Distortion and
Specificatinos for Jitter Test-Signal Generation," in IEEE International Symposium on
Electromagnetic Compatibility , Detroit, 2008, pp. 1-4.
[9] Owen B Laug, T. Micheal Souders, and Donald R. Flach, "A Custom Integrated Circuit
Comparator for High-Performance Sampling Applications," IEEE Transactions on
Instrumentation and Measurement , vol. 41, pp. 850-855, December 1992.
[10] D. I. Bergman and B. C. Waltrip, "A Low Thermal Error Sampling Comparator for
Accurate Settling Measurements," in IEEE International Symposium on Circuits and
Systems , Vancouver, B.C., 2004, pp. 521-524.
[11] Colin Gyles, "Repetitive Waveform High Frequency, High Precision Digitizer," IEEE
Transactions on Instrumentation and Measurement , vol. 38, pp. 917-920, August 1989.
[12] R. T. Dennison and K. M. Walter, "Local Thermal Effects in High Performance Bipolar
Devices/Circuits," in Proc. IEEE Bipolar Circuits and Technology Meeting , Mineapolis,
MN, 1989, pp. 164-167.
[13] P. R. Ganci et al., "Self-Heating effects in High-Performance Bipolar Transistors Fabricated
on SOI Substrates," in Proceedings of IEEE International Electron Devices Meeting , San
Francisco, CA, 1992, pp. 417-420.
[14] Jonathan S. Brodsky, David T. Zweidinger, and Robert M. Fox, "Physics-Based Multiple-
Pole Models for BJT Self-Heating," in IEEE 1993 Bipolar Circuits and Technology
Meeting , 1993, pp. 249-252.
128
[15] Nebojsa Nenadovic et al., "Extraction and Modeling of Self-Heating and Mutual Thermal
Coupling Impedance of Bipolar Transistors," IEEE Journal of Solid-State Circuits , vol. 39,
pp. 1764-1772, October 2004.
[16] Kenneth G. Schlotzhauer, "Overdrive Thermal Distortion Compensation for a Quinn
Cascomp Amplifier," 4,528,517, July 9, 1985.
[17] Shaun Simpkins and Winthrop Gross, "Cascomp Feedforward Error Correction in High
Speed Amplifier Design," IEEE Journal of Solid-State Circuits , vol. SC-18, pp. 762-764,
December 1983.
[18] Colin C. McAndrew, "A Complete and Consistent Electrical/Thermal HBT Model," in
Proc. IEEE 1992 Bipolar Circuits and Technology Meeting , 1992, pp. 200-203.
[19] Kiyoshi Fukahori and Paul R. Gray, "Computer Simulatino of Integrated Circuits in the
Presence of Electrothermal Interaction," IEEE Journal of Solid-State Circuits , vol. SC-11,
no. 6, pp. 834-846, December 1976.
[20] Yu Zhu, John K. Twynam, Motoji Yagura, Masatomo Hasegawa, and Takao Hasagawa,
"Self-Heating Effect Compensation in HBTs and its Analysis and Simulation," IEEE
Transactions on Electron Devices , vol. 48, no. 11, pp. 2640-2646, November 2001.
[21] Jiann-Shium Yuan, "Thermal and Reverse Base Current Effects on Heterojuction Bipolar
Transistors and Circuits," IEEE Transactions on Electron Devices , vol. 42, no. 5, pp. 789-
794, May 1995.
129
[22] Colin C. McAndrew, "A Complete and Consistent Electrical/Thermal HBT Model," IEEE
1992 Bipolar Circuits and Technology Meeting , pp. 200-203, 1992.
[23] S. Russo, V. d'Allesandro, L. La Spina, N. Rinaldi, and L. K. Nanver, "Evaluating the Self-
Heating Thermal Resistance of Bipolar Transistors by DC Measurements: A Critical
Review and Update," in IEEE Bipolar Circuits and Technology Meeting , 2008, pp. 95-98.
[24] Sergey V. Cherepko, James C. M. Hwang, and Walter R. Curtice, "Effects of Bias and Load
Conditions on Dynamic Self Heating of Bipolar Transistors," in Microwave Symposium
Digest, 2004 IEEE MTT-S International , 2004, pp. 47-50.
[25] Benoit Barbalat, Thierry Schwartzmann, Pascal Chevalier, Thierry Jagueneau, and Benoit
Vandelle, "Deep Trench Isolation Effect on Self-Heating and RF Performances of SiGeC
HBTs," in Proceedings of ESSDERC , Grenoble, 2005, pp. 129-132.
[26] Niccolo Rinaldi, "Theory of Electrothermal Behavior of Bipolar Transistors: Part I - Single
Finger Devices," IEEE Transactions on Electron Devices , vol. 52, no. 9, pp. 2009-2021,
September 2005.
[27] M. Hossain, Mingsheng Peng, Alan Davis, Howard T. Russell, and Ronald L. Carter,
"Thermal Effects on Current Mirrors for High Speed Opamps in Dielectrically Isolated
Technology," in IEEE Region 5 Technical Conference , Fayetteville, AR, 2007, pp. 445-448.
[28] Sang-Gug Lee, "A Review of Self-Heating Effects on Bipolar Circuits," in Southcon/94.
Conference Record , 1994, pp. 138-142.
130
[29] Yang-Hua Chang and Jia-Shiou Cai, "Simulation of self-heating effects on heterojunction
bipolar transistors," in Next-Generation Electronics (ISNE), 2013 IEEE International
Symposium on , Kaohsiung, Taiwan, 2013, pp. 383-385.
[30] A.A.L. de Souza, J-C Nallatamby, M. Prigent, and R. Quere, "Dynamic impact of self-
heating on input impedance of bipolar transistors," Electronics Letters , vol. 42, no. 13, pp.
777-778, June 2006.
[31] V. D'Alessandro et al., "Impact of layout and technology parameters on the thermal
resistance of SiGe:C HBTs," in Bipolar/BiCMOS Circuits and Technology Meeting
(BCTM), 2010 IEEE , Austin, TX, 2010, pp. 137-140.
[32] K.M. Webb and T.S. Kalkur, "A circuit-based approach for the compensation of self-
heating-induced timing errors in bipolar comparators," in Bipolar/BiCMOS Circuits and
Technology Meeting (BCTM), 2012 IEEE , Portland, OR, 2012, pp. 1-4.
[33] S.S. Lee and D.J. Allstot, "Electrothermal Simulation of Integrated Circuits," IEEE J. Solid-
State Circuits , vol. 28, no. 12, pp. 1283-1293, Dec. 1993.
[34] L.K. Nanvar et al., "A Back-Wafer Contacted Silicon-on-Glass Integrated Bipolar Process -
Part I: The Conflict Electrical Versus Thremal Isolation," IEEE Trans. Electron Devices ,
vol. 51, no. 1, pp. 42-50, Jan. 2004.
[35] S. Russo et al., "Thremal Transient Behavior of Silicon-on-Glass BJTs," in Proc. IEEE
EuroSimE , Delft, The Netherlands, 2009, pp. 93-100.
131
[36] S. Russo, L. La Spina, V. d'Allesandro, N. Rinaldi, and L.K. Nanver, "Influence of Layout
Design and On-Wafer Heatspreaders on the Thermal Behavior of Fully-Isolated Bipolar
Transistors: Part I - Static Analysis," Solid State Electron. , vol. 54, no. 8, pp. 745-753, Aug.
2010.
[37] S. Russo, L. La Spina, V. d'Allesandro, N. Rinaldi, and L.K. Nanver, "Influence of Layout
Design and On-Wafer Heatspreaders on the Thermal Behavior of Fully-Isolated Bipolar
Transistors: Part II - Dynamic Analysis," Solid State Electron. , vol. 54, no. 8, pp. 754-762,
Aug. 2010.
132
APPENDIX
CIRCUIT SCHEMATICS
TopLevel
133
Core
134
FullComp
VCSgen
135
InputAmp50ohm
136
CbInputAmp
InputOffsetNull
137
InputAmpVCSgen
138
Comp
139
ThermCompTailSource
PVC
140
PVCmult
141
PVCamp
142
VCSgenVthermNull
143
VthermNull
ThermCompEnable
144
VthermVTA
145
VthermVTAfixed
146
VthermVTAvariable
VthermCalCtrl
147
VthermVTAgmFixed
148
VthermVTAgmVariable
149
HystVCSgen
150
OutputAmp50ohm
151
LinAmp
152
DiffPairAmp
153
IoPadEsd
IoPadEsdCDM
154
GndPadEsd
VccPadEsd
155
VeePadEsd
EsdRCclamp
156
SupplyBypass