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ON a GENERAL PROPERTY of MEMORY MAPPING TABLES Karl ON A GENERAL PROPERTY OF MEMORY MAPPING TABLES Karl Reed Department of Computing Royal Melbourne Institute of Technology G.P.O. Box 2476V Melbourne Victoria 3001 Australia ABSTRACT The paper shows that memory mapping tables can be used to implement the display registers used in providing architectural support for block-structured languages such as Algol 60. This allows full lexieal level addre3sing to be implemented on so-called von-Neuman machines. The problems of fragmentation of the paged address space are explored, and machines with memory mapping schemes capable of supporting the proposals identified. Attention is drawn to the similarity between segmented and paged schemes, and it is suggested that the latter may be used to support the former. Keywords: Memory mapping, page tables, display, segmentation, virtual memory. CR Categories: 4.12, 4.13, 6.21. i. INTRODUCTION two-dimensional (Randell & Kuehner 1968 p.297, Denning 1970, Doran 1979). Logical addresses in It is generally considered that the so- all cases have the form called von-Neuman architectures are different from a lexical level addressed stack architec- A l = (el,e2) (I) ture such as that implemented by Burroughs on where the binary pair (~i,~9) is suitably encoded the B6700 (Doran 1979 page 8, Bishop and Barron in an instruction's address~field. p. 116, Organick 1973 page vii) because display registers (see Dijkstra 1961) and the associated Physical addresses, on a linear address addressing mechanism are not present. space are calculated by a mechanism algorith- mically equivalent to In practice, display registers can be simulated in software on machines with linear Ap = M(~ I) + ~2 (2) address spaces and programs written in languages assuming a linear address space are made to run where M nmps ~I onto a range of physical addresses. on the B6700. The similarities between the three mechan- The fact that there are a number of stack isms can be studied by recognizing that each based computer architectures, the Hewlet Packard consists of two separate components. 3000 (Hewlett Packard 1976B), the ICL2900 (Buckle 1978), the MU5 (Morris and Ibbett 1979) and a a) Operand Access, the algorithm used to machine based upon the PDPiI (Tanenbaum 1978) calculate on operand address, which do not contain display registers is of no relevance to this paper. Our intention is to b) A_ddress Space Maintenance, the steps taken show that it is possible to supportthe display- during procedure call-like operations which based lexical level addressing on a machine with alter the accessible address space, to a paged linear address space. ensure that operand access is valid. (See also Bishop and Barron.) This is because the construction of the linear address of an on-stack operand or pointer We show that operand access equivalence in a lexical-level address architecture such as can be maintained for paged and lexical-level the B6700 involves algorithmic steps identical addressing on a paged machine, and suggest that to those used for a pa~ed linear address space a similar equivalence can be established between even tnough the details of implementatlu. all three on a paged machine. differ. This similarity exists between paged, lexical-level and segmented systems because the operand addresses prior to evaluation are all Permission to copy without ~e all or part of this material is granted provided that the copies are not made or distributed ~r direct comme~ial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association ~r Computing Machinery. To copy otherwise, or to republish, ~quires a ~e and/or specific permission. @ 1982 ACM 0-89791-066-4 82/03/0081 $00.75 81 If fact, we will show that memory mapping The logical address space is contiguous in system3 such as that provided for process space the sense that data structures may cross arbitrary address translation on the Digital Equipment numbers of pages, and indexing across page VAXII/T80 could be used without modification. boundaries is permitted. 2. II~E ADDRESSING SCHEMES 2.1.2 Address Space Maintenance in a Paged Virtual Memory 2.1.1 Operand Access in a Paged Virtual Memory The contents of the page tables are not altered Paged virtual memory systems based upon one-level when procedure calls or exits are performed, the store concept (Kilburn et al 1961) are well known performance of the system being indistinguishable and will not be described in detail here. See from a linear, non-virtual address space. instead any of the following:- Randell & Keuhner (1968), Tanenbaum (1976), or The translation process is shown in Figure I. Denning (1970). 2.2 Lexical Level Addressing A logical address =/consists of the ordered pair (el'l, ="l )- where ~r I is the logical page 2.2.1 O~erand Access in a Lexical Level Stack number, and ~"/ is the word within page. Operands, which may be on stack variables or Because the number of words in a page is pointers to on or off stack items are addressed normally a power of two, and physical pages are with the aid of display registers. The operand allocated sequentially with the first usually address takes the form of an ordered pair (//, £) allocated starting at physical word zero, the where fact that the physical address is obtained by // is the lexical level of the block containing the object, and ~p = T(~'/) + ~"/ (3) is it's position relative to the start of where T is a mapping of logical page number the lexical level. onto physical address is obscured (See Denning, 1970 p.163). The state of a lexical level stack is shown in Figure 2 taken from Doran (Fig.ll.5, p.51), Instead, the physical address is obtained complete with static and dynamic links (see also by physically concatenating the word within page Barron & Bishop). field, ~"p, with the contents of the page trans- lation taNle which provides the most significant The address of the object in the linear bits. Equation (3) is actually address space onto which the stack is mapped is ~p = Tp (~'l) li~"l (4) c~ = D(//) + / (5) where T maps logical page numbers to physical numbers~ I ~g logical address J Virtual Word within page page no. i c~'p --~~agePhysical Physical address I I % Page Table F~. i. Typical Virtual Memory Address Generation 82 begin integer i; (2,2) procedure P (j,k) (2,3) integer j,k; (3,2), (3,3) i F RCW ra M~W ~13]." begin integer re,n; (3,2), (3,3) P (re, i}; l end end a) Skeleton of an Algol program b) Stack while in procedure P Figure 2. Typical lexical level stack with static and dynamic links D or display registers on the B6700 contain 3. USE OF PAGED VIRTUAL MEMORY TO ACHIEVE a 20 bit physical address pointing to the first LEXICAL LEVEL ADDRESSING word of what we will call a lexical stack frame, however, this could have been an address in a 3.1 Equivalence of Paged and Lexical Level linear virtual address space. The maximum Addressing number of items which may appear on a lexical level is 213 , and address couples occupy 14 We have demonstrated the equivalence of these bits (Refer to B6700 reference manual, and two methods from the foregoing. It is necessary Organick 1973 and Doran 1979). A total of now to show that the problems of storage frag- 32 display registers are provided. mentation, space allocation and address space maintenance can be handled at least as well as Consecutive lexical stack frames need not they can on the B6700. be contiguous on the linear address space. Stack frames are variable length. The provision Particular issues are:- of a word address in the D registers reduces fragmentation of the linear address space. a) The need for variable sized lexical stack frames. 2.2.2 Address Space Maintenance in a Lexical b) Variance between optimum page and lexical Level Stack stack frame sizes, and Procedure call and exit operators must adjust c) Minimization of logical and physical the contents of the D registers to ensure that storage fragmentation. operand addressing is correct. The method used on the B6700 (see Organick, Doran & Burrough§ 3.2 An Appropriate Memory Mapping Scheme for details) relies upon the static and dynamic chains passing through the Mark Stack Control Consider a logical-physical page size of p words, Words (MSCW) as shown in Figure 2. The where p is a power of two, with a one word page- algorithms are sufficiently well known not to table-entry (PTE). Further, consider that the warrant further description. page table for any process including the opera- ting system is held in a logical address space 2.3 Segemented Memory called the page-table space (PTS), which is also paged. In other words, the logical to physical The essential similarities between segmented address translation for any process is described and paged address calculations have been noted by a contiguous set of words in the PTS. This elsewhere (Tanenbaum 1976 and Randell and is shown in Figure 3 below. Kuehner 1963), and are clear from Denning's discussion of the two methods (Denning 1970 This is identical to the scheme used on pp.161-164). In the interests of brevity, we the VAXIi/7SO(DEC 1979)for non-system address focus upon the possibility of using a paged translation, and to the two level translation system to achieve lexical level addressing. on the Data General MV/8000 (Data General page 37). It is also similar to a paged segmented system. (See Denning 1970).
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