Semiconductor Test Equipment Development Oral History Panel
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A Labview Research Projects
A LabVIEW Research Projects The brief description of research projects collected from IEEE journals, Research Labs and Universities are given in this appendix. A.1 An Optical Fibre Sensor Based on Neural Networks for Online Detection of Process Water Contamination It is often required to know the contamination of process water systems from known contaminants e.g., oil, heavy metals, or particulate matter. Most of the governments are forcing rules to monitor the output water from all industrial plants before they may be discharged into existing steams or waterways. There is therefore a clear need for a sensor that is capable of effectively monitoring these output discharges. Optical fibers provide a means of constructing such sensors in an effective manner. Optical fibers are passive and therefore do not them selves contaminate the environment in which they are designed to work. The proposed sensor system is to be operated from and LED or broad- band light source and the detector will monitor changes in the received light spectrum resulting from the interaction of the fibre sensor with its environ- ment. The signals arising from these changes are often complex and require large amounts of processing power. In this proposed project it intended to use Artificial Neural Networks to perform the processing and extract the true sensor signal from the received signal. A.2 An Intelligent Optical Fibre-Based Sensor System for Monitoring Food Quality It is proposed to develop an intelligent instrument for quality monitoring and classification of food products in the meat processing and packaging industry. The instrument is intended for use as an effective means of testing food prod- ucts for a wide range of parameters. -
Vlsi Research Inc
FOR IMMEDIATE RELEASE VLSI RESEARCH INC 2007 VLSI Research Inc 10 BEST Awards for Test, Material Handling, and Assembly Equipment - Inovys, SUSS MicroTec, and Orthoydne achieve highest rankings Santa Clara, CA - June 18, 2007 - VLSI Research Inc is pleased to announce the winners of the coveted 2007 10 BEST suppliers for Test Equipment, Material Handling Equipment, and Assembly Equipment. Rankings are based on surveys returned from customers who represent 95% of the world’s total semiconductor market. Customers rated Inovys, SUSS MicroTec, and Orthodyne as the #1 supplier in each of their respective categories. A special mention of Orthodyne and Kulicke & Soffa is warranted since they achieved an average higher than 8.0 in the extremely competitive Assembly segment. In fact, the spread between first and tenth in the Assembly segment is only 0.73 points, compared to well over 1 point in most other 10 BEST lists. 2007 10 BEST TEST EQUIPMENT Overall Rank Company † Rating 1 Inovys Corporation 7.98 2 Nextest Systems Corporation 7.90 3 Advantest 7.49 4 LTX Corporation 7.48 5 Teradyne, Inc. 7.28 6 Verigy 6.94 7 Credence Systems Corporation 6.92 8 Yokogawa Electric Corporation 6.85 9 Eagle Test Systems, Inc. 6.78 10 FEI Company 6.71 2007 10 BEST 2007 10 BEST MATERIAL HANDLING EQUIPMENT ASSEMBLY EQUIPMENT Overall Overall Rank Company † Rank Company † Rating Rating 1 SUSS MicroTec 7.97 1 Orthodyne Electronics 8.36 2 Cascade Microtech, Inc. 7.63 2 Kulicke & Soffa Industries, Inc. 8.02 3 ACCRETECH-Tokyo Seimitsu Co., Ltd 7.63 3 ACCRETECH-Tokyo Seimitsu Co., Ltd 7.95 4 Advantest 7.48 4 HANMI Semiconductor 7.93 5 Seiko Epson Corporation 7.42 5 ICOS Vision Systems 7.93 6 Rasco GmbH 7.29 6 Advanced Dicing Technologies 7.76 7 Tokyo Electron Limited 7.21 7 Dage Precision Industries Ltd 7.73 8 Multitest 7.18 8 Asymtek, a Nordson company 7.72 9 Electroglas, Inc. -
AUTOMATIC TEST ENVIRONMENT SETUP a Project
AUTOMATIC TEST ENVIRONMENT SETUP A Project Presented to the faculty of the Department of Computer Engineering California State University, Sacramento Submitted in partial satisfaction of the requirements for the degree of MASTER OF SCIENCE in Computer Engineering by Trupti Deepak Naik SPRING 2015 AUTOMATIC TEST ENVIRONMENT SETUP A Project by Trupti Deepak Naik Approved by: __________________________________, Committee Chair Fethi Belkhouche, Ph.D. __________________________________, Second Reader Preetham Kumar, Ph.D. ____________________________ Date ii Student: Trupti Deepak Naik I certify that this student has met the requirements for format contained in the University format manual, and that this project is suitable for shelving in the Library and credit is to be awarded for the Project. __________________________, Graduate Coordinator ________________ Nikrouz Faroughi, Ph.D. Date Department of Computer Engineering iii Abstract of AUTOMATIC TEST ENVIRONMENT SETUP by Trupti Deepak Naik Manual verification in industry testing is a very complex and tedious process. Verification test engineers need to carefully go through various application screens, make the correct oscilloscope setups to get the expected results, try various input combinations and compare the results with the expected behavior. Furthermore, this type of testing is repetitive in nature. With the introduction of the new chips and/or new firmware releases, Automatic Test Environment (ATE) is becoming widely used to address the limitations of the traditional verification testing methods. This project focuses on creating an automated test environment for Solid State Devices (SSD) hardware verification testing. The project will contribute in making the tedious process of manual testing simpler and more time efficient for verification engineers. The project is implemented using Python Scripting Language and Test Environment Suite libraries from Agilent Command Expert tool. -
Survey of Electronic Hardware Testing Types, ATE Evolution & Case Studies
Published by : International Journal of Engineering Research & Technology (IJERT) http://www.ijert.org ISSN: 2278-0181 Vol. 6 Issue 11, November - 2017 Survey of Electronic Hardware Testing Types, ATE Evolution & Case Studies Manjula C Dr. D. Jayadevappa Assistant Professor, EEE Dept., Professor, The Oxford College of Engineering, Bangalore Electronics Instrumentation Dept., JSSATE, Bangalore Abstract - I have undertaken exhaustive survey, to bring out this technical paper covering - Testing principle, Levels, Types, Process, VLSI or Chip testing, Automatic Test equipment (ATE) – configuration, evolution, three case studies of FPGA interfaced with ATE, FPGA generating ATG for ATE and FPGA used with PC scope for VLSI / Chip testing etc. Keywords- Types of testing, Principle of testing, Levels of testing, ATE, Evolution of ATE Testing. INTRODUCTION Fig.1: Basic Testing Approach Testing is an experiment in which the system is exercised C. Level of Testing and its resulting response is analyzed to check its behavior Testing a die (chip) can occur at the following levels: [1]. If incorrect behavior is detected, the system is diagnosed Wafer level and locates the cause of the misbehavior. Diagnosis requires Packaged chip level the knowledge of the internal structure of the system under Board level test. System level A. Importance of Testing Field level In Today‘s Electronics world, more time is required for testing rather than design and fabrication. When the D. Types of Testing circuit/device is developed, it is necessary to determine the Manual testing and Automated Testing: functional and timing specifications of the circuit/device. Devices can be tested in two ways, manually and When the multiple copies of a circuit are manufactured, it is automatically. -
CREDENCE SYSTEMS CORPORATION Credence Systems Corporation 2002 2001 2000 1999 1998 for Fiscal Year Ending October 31 (In Thousands, Except Per Share Amounts)
ANNUAL REPORT 2002 ENSURING THE FUTURE CREDENCE SYSTEMS CORPORATION Credence Systems Corporation 2002 2001 2000 1999 1998 For Fiscal Year Ending October 31 (In Thousands, Except Per Share Amounts) Net Sales ..................................................... 164,209 301,718 757,351 253,253 253,500 Operating Income (Loss) ................................. (173,194) (172,942) 225,550 3,361 (47,159) Net Income (Loss) .......................................... (170,481) (98,676) 120,510 4,772 (29,613) Net Income Per Diluted Share (Loss) .................... (2.81) (1.65) 2.00 0.10 (0.59) Number of Shares Used in Computing Per Share Amount .............................. 60,570 59,818 61,892 50,168 49,812 Working Capital .............................................. 234,050 323,946 426,515 188,954 220,014 Total Assets ................................................... 582,249 757,419 983,437 428,799 369,603 Shareholders' Equity ....................................... 519,237 680,940 767,875 243,228 203,559 Credence intends to provide the most cost-effective products and services to move our customers' devices from concept through production. Recognized as the number one North American ATE supplier for customer satisfaction in 2002. TO OUR SHAREHOLDERS STATE OF THE INDUSTRY We are currently experiencing the most prolonged downturn in the history of the semiconductor industry. Electronic sales – the driver of semiconductor consumption – are forecasted to drop yet again in 2002 following a contraction of 14 percent in 2001. This is unprecedented in an industry that has grown every year prior to 2001. In early calendar 2002, the semiconductor capital equipment industry in general, and the automatic test equipment (ATE) industry in particular, began to see an improvement in business conditions and book-to-bill ratios climbed above one for the first time in 18 months. -
Design of Jig for Automated PCB Testimg
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 4, Issue 4, April 2015 Design of Jig for Automated PCB Testimg Nilangi U. Netravalkar Sonia Kuwelkar Microelectronics, ETC dept., Asst. Prof. ETC dept., Goa College of Engineering, Goa College of Engineering Goa University, India. Goa University, India. Abstract— Paper includes hardware designing of PCB II. WHY AUTOMATED TESTING? test jig using Raspberry Pi that will be used for automated Automatic test equipment enables printed circuit board test testing of master card PCB used in X ray machines. and equipment test to be undertaken very faster than if it were Automated Test Euipment (ATE) will verify the PCB’s done manually. As time of production staff forms a major functionality and its behavior. The test procedure includes element of the overall production cost of an item of electronics sending of command frame from test jig to the DUT using equipment, it is necessary to reduce the production times as Raspberry Pi controller and receiving the response frame possible which can be achieved with the use of ATE, from the DUT. The command frame and the response automatic test equipment. frame are then compared which determines the test to be pass or fail. The test procedures includes testing of digital ATE systems are designed to reduce the amount of test time inputs outputs of the DUT and also other functionalities of needed to verify that a particular device works or to quickly the master card. The test is usually performed according find its faults before the part has a chance to be used in a final to the OEM test engineer, who defines the specifications consumer product. -
Test and Characterization Methodologies for Advanced Technology Nodes Darayus Adil Patel
Test and characterization methodologies for advanced technology nodes Darayus Adil Patel To cite this version: Darayus Adil Patel. Test and characterization methodologies for advanced technology nodes. Elec- tronics. Université Montpellier, 2016. English. NNT : 2016MONTT285. tel-01808874 HAL Id: tel-01808874 https://tel.archives-ouvertes.fr/tel-01808874 Submitted on 6 Jun 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Délivré par Université de Montpellier Préparée au sein de l’école doctorale I2S Et de l’unité de recherche LIRMM Spécialité : SYAM Présentée par DARAYUS ADIL PATEL TEST AND CHARACTERIZATION METHODOLOGIES FOR ADVANCED TECHNOLOGY NODES Soutenue le 5 Juillet 2016 devant le jury composé de M. Daniel CHILLET Professeur, Université de Président du Jury / Rennes Rapporteur M. Salvador MIR Directeur de Recherche Rapporteur CNRS, TIMA Mme. Sylvie NAUDET Team Leader, Examinateur STMicroelectronics M. Alberto BOSIO MCF HDR, Université de Examinateur Montpellier M. Patrick GIRARD Directeur de Recherche Directeur de Thèse CNRS, LIRMM M. Arnaud -
United States Securities and Exchange Commission Form
UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 10-K FOR ANNUAL AND TRANSITION REPORTS PURSUANT TO SECTIONS 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 (Mark One) ⌧ ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended October 31, 2004 OR TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to 0-22366 (Commission file number) CREDENCE SYSTEMS CORPORATION (Exact name of registrant as specified in its charter) Delaware 94-2878499 (State or other jurisdiction (I.R.S. Employer of incorporation or organization) Identification No.) 1421 California Circle, Milpitas, California 95035 (Address of principal executive office) (Zip Code) (408) 635-4300 (Registrant’s telephone number, including area code) Securities registered pursuant to Section 12(b) of the Act: Title of each class Name of each exchange on which registered None None Securities registered pursuant to Section 12(g) of the Act: Common Stock, $0.001 par value Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes ⌧ No Indicate by a check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of the registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. -
Electronic Circuit Board Testing Equipment Series Catalog
Electronic Circuit Board Testing Equipment Series Catalog AutomaticAutomatic TestTest EquipmentEquipment FLYING PROBE TESTER IN-CIRCUIT TESTER BARE BOARD TESTER DATA CREATION SYSTEM 2 From Ueda, Shinshu This year, HIOKI marks the 80th anniversary of its establishment in 1935. As a professional electrical measurement tool provider, we will continue to develop products that offer the solutions our customers need. Our factory at HIOKI headquarters integrates all our departments ― development, production, sales and service ― in Ueda City, Nagano Prefecture, widely known as the Shinshu area, abundant with greenery. This factory enables us to promptly respond to customer demand through in-house development and in-house production. SOLUTION FACTORY The HIOKI Solution Factory integrates all our tasks to provide high-quality products to our customers. Nagano Prefecture Measurement Technologies to Support New Testing Frontiers 3 Design Sales Call center Service Development Solution sales helps customers realize their dreams Development Add ever-greater value Repair and calibration by establishing Board design unique development technologies Production The HIOKI production system ensures high product quality, low cost and short lead times Shipment Vacuum deposition Board mounting Printing instruction manuals Assembly Measurement Technologies to Support New Testing Frontiers 4 INDEX Just because you can’t see it, doesn’t mean we can’t test it. Flying Probe Type High-density, Multi-layer Board Solutions ● Assurance of minute via resistance values and -
Integrated Circuit Test Engineering Iana.Grout Integrated Circuit Test Engineering Modern Techniques
Integrated Circuit Test Engineering IanA.Grout Integrated Circuit Test Engineering Modern Techniques With 149 Figures 123 Ian A. Grout, PhD Department of Electronic and Computer Engineering University of Limerick Limerick Ireland British Library Cataloguing in Publication Data Grout, Ian Integrated circuit test engineering: modern techniques 1. Integrated circuits - Verification I. Title 621.3’81548 ISBN-10: 1846280230 Library of Congress Control Number: 2005929631 ISBN-10: 1-84628-023-0 e-ISBN: 1-84628-173-3 Printed on acid-free paper ISBN-13: 978-1-84628-023-8 © Springer-Verlag London Limited 2006 HSPICE® is the registered trademark of Synopsys, Inc., 700 East Middlefield Road, Mountain View, CA 94043, U.S.A. http://www.synopsys.com/home.html MATLAB® is the registered trademark of The MathWorks, Inc., 3 Apple Hill Drive Natick, MA 01760- 2098, U.S.A. http://www.mathworks.com Verifault-XL®, Verilog® and PSpice® are registered trademarks of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, U.S.A. http://www.cadence.com/index.aspx T-Spice™ is the trademark of Tanner Research, Inc., 2650 East Foothill Blvd. Pasadena, CA 91107, U.S.A. http://www.tanner.com/ Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms of licences issued by the Copyright Licensing Agency. -
Test Programming an ATE for Diagnosis by Heng Zhao a Thesis Submitted to the Graduate Faculty of Auburn University in Partial Fu
Test Programming an ATE for Diagnosis by Heng Zhao A thesis submitted to the Graduate Faculty of Auburn University in partial fulfillment of the requirements for the Degree of Master of Electrical Engineering Auburn, Alabama June 1, 2015 Keywords: Diagnostic Tree, stuck-at-fault, Automatic Test Equipment Copyright 2015 by Heng Zhao Approved by Vishwani D. Agrawal, Chair, James J. Danaher Professor of Electrical & Computer Eng. Victor P. Nelson, Professor of Electrical & Computer Engineering Adit D. Singh, James B. Davis Professor of Electrical & Computer Engineering Abstract If we need to test a circuit, we will give the circuit some input logic vectors. Then we will observe its output. A fault is said to be detected by a test pattern if the output for that test pattern is different from the expected output. A defect is an error caused in a device during the manufacturing process. The logic values observed at primary outputs of a device under test (DUT) upon application of a test pattern t are called the output of that test pattern. The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern. However, a large circuit may needs too many vectors to test, which would take lot of time and money. In this way, we may spend much more money in testing than in making the circuit. So if we reduce the number of test vectors, we would save a lot of expense. As we know, even though the circuits were made from the same model, the circuits which made actually are still different. -
Test Coverage Document Aiming to Break Down, Where Possible, Timing and Human Error Barriers
AUTOMATICTOOLINTEGRATIONINTOAN INDUSTRIALELECTRONICBOARDPRODUCTION HARDWAREFAULTCOVERAGEANALYSISPROCESS Luca Ledda Computer Engineering Embedded Systems POLITECNICODITORINO supervisors: Prof. Matteo Sonza Reorda Test Eng. Paolo Caruzzo Test Eng. Roberto Saroglia Test Eng. Paolo Nigro Turin, October 2018 InABSTRACT Magneti Marelli S.p.A. Powertrain very high quality is essential. To achieve such a high quality, the production test must be capable of detecting all potential defects introduced during the production process. The adopted test line involves ICT (In-Circuit Test, Bed of Nails), FT (Functional Test) and AOI (Automated Optical Inspection) strategies. The quality of the test line, which is an indicator of how many defects the line is capable of detecting, is resumed into the coverage document, manually produced by the Magneti Marelli test engineers through the use of personal reasoning and know-how. The purpose of this project is to integrate the hardware fault coverage process with a customized tool in order to obtain as much as possible an automatic flow to generate the final test coverage document aiming to break down, where possible, timing and human error barriers. TheOVERVIEW thesis is organized as follows: In the part, a brief history of the Magneti Marelli S.p.A. is re- ported (chapter 1). After that, the focus is moved to the Powertrain testing team (chapterINTRODUCTION 2) such that highlighting its responsibilities and interactions within the company hierarchy. In the part, an overview of the Magneti Marelli Powertrain production line is reported focusing on all those defects that the final product can be affectedPRODUCTION at the end of TEST manufacturing (chapter 3). Then, the test strategies in the flow impacting on the hardware fault coverage are described (chapter 4), highlight- ing for each technique general theoretical concepts in form of equipment involved, potentialities, limits and possible future improvements.