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Test Programming an ATE for Diagnosis by Heng Zhao a Thesis Submitted to the Graduate Faculty of Auburn University in Partial Fu

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Test Programming an ATE for Diagnosis by Heng Zhao a Thesis Submitted to the Graduate Faculty of Auburn University in Partial Fu Test Programming an ATE for Diagnosis by Heng Zhao A thesis submitted to the Graduate Faculty of Auburn University in partial fulfillment of the requirements for the Degree of Master of Electrical Engineering Auburn, Alabama June 1, 2015 Keywords: Diagnostic Tree, stuck-at-fault, Automatic Test Equipment Copyright 2015 by Heng Zhao Approved by Vishwani D. Agrawal, Chair, James J. Danaher Professor of Electrical & Computer Eng. Victor P. Nelson, Professor of Electrical & Computer Engineering Adit D. Singh, James B. Davis Professor of Electrical & Computer Engineering Abstract If we need to test a circuit, we will give the circuit some input logic vectors. Then we will observe its output. A fault is said to be detected by a test pattern if the output for that test pattern is different from the expected output. A defect is an error caused in a device during the manufacturing process. The logic values observed at primary outputs of a device under test (DUT) upon application of a test pattern t are called the output of that test pattern. The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern. However, a large circuit may needs too many vectors to test, which would take lot of time and money. In this way, we may spend much more money in testing than in making the circuit. So if we reduce the number of test vectors, we would save a lot of expense. As we know, even though the circuits were made from the same model, the circuits which made actually are still different. Testing them with the same vectors will not an efficacious way. The circuits in different situation, should use different vectors and in different sequence. The algorithm, diagnostic tree, will help to choose the vectors and shorter the time. If the vectors fail in this circuit, the diagnostic tree will give another vector, however, if the vectors success in the circuit, it will get a different vector to test. After the algorithm has been finished, we need to use it to see how it works. In this way, we should simulate a benchmark circuit and test it with diagnostic tree in the ATE machine. The ATE machine can test the circuit and we can see its processing in the Flow Edit. ii Acknowledgments I would like to thank so many people who helped me. First and the most, I am grateful to Prof. Vishwani D. Agrawal for all his support. Without his help, I can’t finish the thesis. In his office, I got many ideas about the thesis. His suggestion about using the ATE machine helps me a lot. I am very grateful to be his student. I am also thankful to Prof. Adit D. Singh and Prof. Victor P. Nelson for being on my advisory committee. I have learned a lot from their class about VLSI testing and Computer Aid Design. I would also like to thank my family first, they support me to study in Auburn from China. Furthermore, thanks my friends, Zhao Yang, BaoHu Li , Chaoyi She, JiaLin Ding, Kupeng Zeng, ZeShi Luo, for these years help in study. iii Table of Contents Abstract ......................................................................................................................................................... ii Acknowledgments ....................................................................................................................................... iii List of Figures ................................................................................................................................................ v List of Abbreviations .................................................................................................................................... vi 1 Introduction ........................................................................................................................................... 7 1.1 Organization of Thesis .............................................................................................................. 7 2 Background ....................................................................................................................................... 8 2.1 Stuck at fault ............................................................................................................................. 8 2.2 Diagnostic test .......................................................................................................................... 8 2.3 Diagnostic tree ......................................................................................................................... 8 2.4 ATE tester ................................................................................................................................. 9 2.5 Advantest T2000 .................................................................................................................... 10 2.6 Tessent FastScan .................................................................................................................... 10 2.7 Benchmark Circuit .................................................................................................................. 10 2.8 OTPL ........................................................................................................................................ 10 2.9 ATPG ........................................................................................................................................ 11 3 Prior Work ......................................................................................................................................... 12 3.1 traditional stuck-at-fault simulation ......................................................................................... 12 3.2 use multiplexer to simulate stuck-at-fault ............................................................................... 13 4 Algorithms ....................................................................................................................................... 15 5 Simulation and Result ...................................................................................................................... 17 iv 5.1 Results ..................................................................................................................................... 22 6 Conclusion ....................................................................................................................................... 27 6.1 Future Work .............................................................................................................................. 27 Bibliography ................................................................................................................................................ 29 List of Figures 3.2 multipexer for stuck-at-fault. .. .. .. 13 3.3 orignal signal simulation. .. 13 3.4 Stuck-at-1 model simulation. .. 14 4.1 Diagnostic tree. .. .. 15 4.2 Diagnostic tree in 74182 benchmark circuit. .. .16 5.1 Fault dictionary. 17 5.2 74182 Gate-Level Schematic. .18 5.3 File generated by FastScan . 19 5.4 Faults detect by vector T0 . .. .. 20 5.5 Faults detected by vector T1. .. .. .20 5.6 Fault dictionary for 74182 benchmark circuit. .. .. 21 5.7 Fault free circuit in Flow edit. .. 23 5.8 Traditional way to test circuit. .. 23 5.9 Diagnostic tree to test circuit. .. .24 5.10 Multiple-stuck-at-fault (most common result). .. 25 5.11 Multiple-stuck-at-fault (special result). .. .. 26 6 Full-response fault dictionary. 28 v List of Abbreviations ATE Automatic Test Equipment ATPG Automatic Test Pattern Generation DFT Design for Testability OTPL Test-plan Programming Language ATPG Automatic Test Pattern Generator vi Chapter 1 Introduction There are many circuits made with mistakes. Even though a high proportion of them are good circuits, we still need to test all of them. Therefore, a short time of testing is desirable. There are various ways to reduce the test time. Some people try to use fewer test vectors to test the circuit, but still have high fault coverage. There are other methods too to shorten the test time. In this project, reducing the number of test application clock cycles is the main objective which helps shorten the time of test. Application of an algorithm, called diagnostic tree, is explored. 1.1 Organization of Thesis Chapter 2 introduces various concepts that help understand the proposed work. Chapter 3 gives a brief study of the previous work. Chapter 4 explains the algorithm used in this project. Chapter 5 describes simulation and results with the ATE machine. Chapter 6 gives the conclusion of the project and suggests future work which may be done to optimize the algorithm. 7 Chapter 2 Background This chapter explains some concepts used in this thesis. 2.1 Stuck-at fault A stuck-at fault is a particular fault model used by fault simulators and automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at logical ‘1’, ‘0’ or ‘X’. In this project, I will detect the single stuck-at fault. It assumes that only one line or node in the digital circuit is stuck [12]. Sometimes it will be stuck at logic high, and sometimes it will be stuck at logic low. As this fault model will be easy simulate and detect in an FPGA board, my circuit will only have the single stuck-at fault. 2.2 Diagnostic test The diagnostic test is applied after the circuit has failed. With the diagnostic test, we can figure out the faulty part. 2.3 Diagnostic tree As we know, for large circuits,
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