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WAFER-LEVEL TESTING and TEST PLANNING for INTEGRATED CIRCUITS By WAFER-LEVEL TESTING AND TEST PLANNING FOR INTEGRATED CIRCUITS by Sudarshan Bahukudumbi Department of Electrical and Computer Engineering Duke University Date: Approved: Prof. Krishnendu Chakrabarty, Chair Prof. John Board Prof. Romit Roy Choudhury Prof. Montek Singh Prof. Kishor Trivedi Dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Department of Electrical and Computer Engineering in the Graduate School of Duke University 2008 ABSTRACT WAFER-LEVEL TESTING AND TEST PLANNING FOR INTEGRATED CIRCUITS by Sudarshan Bahukudumbi Department of Electrical and Computer Engineering Duke University Date: Approved: Prof. Krishnendu Chakrabarty, Chair Prof. John Board Prof. Romit Roy Choudhury Prof. Montek Singh Prof. Kishor Trivedi An abstract of a dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Department of Electrical and Computer Engineering in the Graduate School of Duke University 2008 Copyright c 2008 by Sudarshan Bahukudumbi All rights reserved Abstract The relentless scaling of semiconductor devices and high integration levels have lead to a steady increase in the cost of manufacturing test for integrated circuits (ICs). The higher test cost leads to an increase in the product cost of ICs. Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of core-based system-on-chip (SoC) designs. Packaging has also been recognized as a significant contributor to the product cost for SoCs. Packaging cost and the test cost for packaged chips can be reduced significantly by the use of effective test methods at the wafer level, also referred to as wafer sort. Test application time is a major practical constraint for wafer sort, even more than for package test. Therefore, not all the scan-based digital test patterns can be applied to the die under test. This thesis first presents a test-length selection technique for wafer-level testing of core-based SoCs. This optimization technique, which is based on a combination of statistical yield modeling and integer linear programming (ILP), provides the pattern count for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. A large number of wafer-probe contacts can potentially lead to higher yield loss during wafer sort. An optimization framework is therefore presented to address test access mechanism (TAM) optimization and test-length selection for wafer-level testing, when constraints are placed on the number of number of chip pins that can be contacted. Next, a correlation-based signature analysis technique is presented for mixed- signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog iv and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss and packaging cost. Results are presented for a typical mixed-signal “big- D/small-A” SoC from industry, which contains a large section of flattened digital logic and several large mixed-signal cores. Wafer-level test during burn-in (WLTBI) is an emerging practice in the semicon- ductor industry that allows testing to be performed simultaneously with burn-in at the wafer-level. However, the testing of multiple cores of a SoC in parallel during WLTBI leads to constantly-varying device power during the duration of the test. This power variation adversely affects predictions of temperature and the time re- quired for burn-in. A test-scheduling technique is presented for WLTBI of core-based SoCs, where the primary objective is to minimize the variation in power consumption during test. A secondary objective is to minimize the test application time. Finally, this thesis presents a test-pattern ordering technique for WLTBI. The objective here is to minimize the variation in power consumption during test applica- tion. The test-pattern ordering problem for WLTBI is solved using ILP and efficient heuristic techniques. The thesis also demonstrates how test-pattern manipulation and pattern-ordering can be combined for WLTBI. Test-pattern manipulation is car- ried out by carefully filling the don’t-care (X) bits in test cubes. The X-fill problem is formulated and solved using an efficient polynomial-time algorithm. In summary, this research is targeted at cost-efficient wafer-level test and burn-in of current- and next-generation semiconductor devices. The proposed techniques are expected to bridge the gap between wafer sort and package test, by providing cost- effective wafer-scale test solutions. The results of this research will lead to higher shipped-product quality, lower product cost, and pave the way for known good die (KGD) devices, especially for emerging technologies such as three-dimensional inte- grated circuits. v Acknowledgements There are several people who significantly influenced this dissertation - in ways direct and indirect - and I would like to thank them here. My advisor, Dr. Krishnendu Chakrabarty provided me the academic freedom to pursue research problems that truly interested me, and for that I am very grateful. His genuine interest in my progress, technical insights and pursuit of perfection have largely been responsible for making me a better researcher. I thank Dr. Sule Ozev for providing valuable counsel and feedback on the mixed- signal project, and for educating me on the practical aspects of mixed-signal testing. I would also like to thank Vikram Iyengar of IBM Corporation for providing industry- insights on the mixed-signal project and for his help in preparing the mixed-signal manuscript. I thank Rick Kacprowicz of Intel Corporation for being our industrial mentor in the burn-in project, and for providing valuable insights on the implemen- tation aspects of our work. I would like to thank my committee members Dr. Kishor Trivedi, Dr. John Board, Dr. Montek Singh, and Dr. Romit Roy Choudhury for taking time to serve on my dissertation committee, and for providing constructive technical feedback on my work. I would also like to thank Dr. Chris Dwyer for serving on my preliminary examination committee. I would like to thank people in my research group Zhanglei Wang, Lara Oliver, Mahmut Yilaz and Yang Zhao. I have benefited greatly from numerous discussions with Zhanglei and Mahmut on a wide range of topics- from testing to politics. I am also indebted to Mahmut and Hongxia Fang for all their help with data generation for my research projects. Many people in the secretarial and support staff in electrical engineering specifi- vi cally Autumn Wenner and Ellen Currin have helped me on numerous occasions with travel reimbursements, departmental letters and administrative support, making my life around here a lot easier. I am grateful for financial support I received for my graduate studies from the Semiconductor Research Corporation and the National Science Foundation. Finally, I would like to thank my mom, dad and brother for being a constant source of support and comfort in times of need. This dissertation will not be complete without the excellent support system they have provided over the years. vii Contents Abstract iv Acknowledgements vi List of Tables xii List of Figures xiv 1 Introduction 1 1.1Background................................ 4 1.1.1 System-level design-for-test and test scheduling for core-based SoCs................................ 5 1.1.2 Wafer-leveltestduringburn-in................. 7 1.1.3 Scandesign............................ 10 1.2Motivationforthesisresearch...................... 10 1.2.1 Challengesassociatedwithwafersort.............. 11 1.2.2 EmergenceofKGDs....................... 13 1.2.3 WLTBI: Industry adoption and challenges ........... 13 1.3Wafer-leveltestplanningforcore-basedSoCs.............. 18 1.4Wafer-leveldefectscreeningformixed-signalSoCs........... 19 1.5WLTBIofcore-basedSoCs........................ 20 1.6PowermanagementforWLTBI..................... 20 1.7Thesisoutline............................... 21 2 Test-Length Selection and TAM Optimization 24 2.1 Defect probability estimation for embedded cores ........... 26 2.1.1 Unifiednegative-binomialmodelforyieldestimation..... 26 viii 2.1.2 Procedure to determine core defect probabilities . ..... 27 2.2Test-lengthselectionforwafer-leveltest................. 33 2.2.1 Test-length selection problem: PTLS .............. 36 2.2.2 Efficientheuristicprocedure................... 40 2.2.3 Greedyheuristicprocedure.................... 41 2.3Experimentalresults........................... 43 2.4Testdataserialization.......................... 51 2.4.1 Test-length and TAM optimization problem: PTLTWS .... 54 2.4.2 Experimental results: PTLTWS ................. 55 2.4.3 Enumeration-based TAM width and test-length selection . 59 2.4.4 TAM width and test-length selection based on geometric pro- gramming............................. 63 Pr 2.4.5 Approximation error in S .................... 66 2.5Summary................................. 68 3 Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs 71 3.1Wafer-leveldefectscreening:Mixed-signalcores............ 72 3.1.1 Signature analysis: Mean-signature-based-correlation (MSBC) 74 3.1.2 Signature analysis: Golden-signature-based-correlation (GSBC) 75 3.2Genericcostmodel............................ 78 3.2.1 Correctionfactors:Testescapesandyieldloss........
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