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SCAN CHAIN BASED HARDWARE SECURITY Xi Chen, Doctor of Philosophy, 2018 Dissertation Directed B
ABSTRACT Title of Dissertation: SCAN CHAIN BASED HARDWARE SECURITY Xi Chen, Doctor of Philosophy, 2018 Dissertation directed by: Professor Gang Qu Department of Electrical and Computer Engineering Hardware has become a popular target for attackers to hack into any computing and communication system. Starting from the legendary power analysis attacks discovered 20 years ago to the recent Intel Spectre and Meltdown attacks, security vulnerabilities in hardware design have been exploited for malicious purposes. With the emerging Internet of Things (IoT) applications, where the IoT devices are extremely resource constrained, many proven secure but computational expensive cryptography protocols cannot be applied on such devices. Thus there is an urgent need to understand the hardware vulnerabilities and develop cost effective mitigation methods. One established field in the semiconductor and integrated circuit (IC) industry, known as IC test, has the goal of ensuring that fabricated ICs are free of manufacturing defects and perform the required functionalities. Testing is essential to isolate faulty chips from good ones. The concept of design for test (DFT) has been integrated in the commercial IC design and fabrication process for several decades. Scan chain, which provides test engineer access to all the flip flops in the chip through the scan in (SI) and scan out (SO) ports, is the backbone of industrial testing methods and can be found in almost all the modern designs. In addition to IC testing, scan chain has found applications in intellectual property (IP) protection and IC identification. However, attackers can also leverage the controllability and observability of scan chain as a side channel to break systems such as cryptographic chips. -
A Labview Research Projects
A LabVIEW Research Projects The brief description of research projects collected from IEEE journals, Research Labs and Universities are given in this appendix. A.1 An Optical Fibre Sensor Based on Neural Networks for Online Detection of Process Water Contamination It is often required to know the contamination of process water systems from known contaminants e.g., oil, heavy metals, or particulate matter. Most of the governments are forcing rules to monitor the output water from all industrial plants before they may be discharged into existing steams or waterways. There is therefore a clear need for a sensor that is capable of effectively monitoring these output discharges. Optical fibers provide a means of constructing such sensors in an effective manner. Optical fibers are passive and therefore do not them selves contaminate the environment in which they are designed to work. The proposed sensor system is to be operated from and LED or broad- band light source and the detector will monitor changes in the received light spectrum resulting from the interaction of the fibre sensor with its environ- ment. The signals arising from these changes are often complex and require large amounts of processing power. In this proposed project it intended to use Artificial Neural Networks to perform the processing and extract the true sensor signal from the received signal. A.2 An Intelligent Optical Fibre-Based Sensor System for Monitoring Food Quality It is proposed to develop an intelligent instrument for quality monitoring and classification of food products in the meat processing and packaging industry. The instrument is intended for use as an effective means of testing food prod- ucts for a wide range of parameters. -
Design and Implementation of High Speed Scan-Hold Flip Flop Based Shift Registers
e-ISSN (O): 2348-4470 Scientific Journal of Impact Factor (SJIF): 4.72 p-ISSN (P): 2348-6406 International Journal of Advance Engineering and Research Development Volume 4, Issue 12, December -2017 Design And Implementation of High Speed Scan-Hold Flip Flop based Shift Registers Kamal Prakash Pandey1, Gunjan Agrawal2 Department of Electronics and Communication Engg. SIET Allahabad Abstract: There has been a great increase in the number of electronic devices and the requirement of high speed design has been increasing exponentially. Here, thus the design of the flip-flop and the sequential logic devices has been a prime constraint in the overall speed performances. Thus to increase the overall speed performance of the flip-flip design, various methodologies have been proposed. The major shift registers used in various digital devices are Serial-In - Serial-Out, Universal shift registers has been developed. In our proposed work, we have proposed scan mode Flip-Flop and these flip-flop based Shift register design. The proposed modified design of the scan multiplexer based D Flip-Flip has been used for the implementation of various shift registers. Here, the Serial In Serial Out, Parallel In Parallel out, and Universal Shift Register design has been presented. Our proposed design is shown to have lower delay and minimize the gate count. The simulation has been done using Xilinx ISE 9.1 and Target device is to be SPARTAN 3E. Keywords: High speed, D-Flip flop, Shift registers, Scan Flip Flop, Gate count, Propagation delay I. INTRODUCTION Electronics market is leading the share of overall business day by day. -
An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing
An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing Author Ivano Indino Supervisor Dr Ciaran MacNamee Submitted for the degree of Master of Engineering University of Limerick June 2017 ii Abstract An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing Ivano Indino Scan testing has been the preferred method used for testing large digital integrated circuits for many decades and many electronic design automation (EDA) tools vendors provide support for inserting scan test structures into a design as part of their tool chains. Although EDA tools have been available for many years, they are still hard to use, and setting up a design flow, which includes scan insertion is an especially difficult process. Increasingly high integration, smaller device geometries, along with the requirement for low power operation mean that scan testing has become a limiting factor in achieving time to market demands without compromising quality of the delivered product or increasing test costs. As a result, using EDA tools for power analysis of device behaviour during scan testing is an important research topic for the semiconductor industry. This thesis describes the design synthesis of the OpenPiton, open research processor, with emphasis on scan insertion, automated test pattern generation (ATPG) and gate level simulation (GLS) steps. Having reviewed scan testing theory and practice, the thesis describes the execution of each of these steps on the OpenPiton design block. Thus, by demonstrating how to apply EDA based synthesis and design for test (DFT) tools to the OpenPiton project, the thesis addresses one of the most difficult problems faced by any new user who wishes to use existing EDA tools for synthesis and scan insertion, namely, the enormous complexity of the tool chains and the huge and confusing volume of related documentation. -
AUTOMATIC TEST ENVIRONMENT SETUP a Project
AUTOMATIC TEST ENVIRONMENT SETUP A Project Presented to the faculty of the Department of Computer Engineering California State University, Sacramento Submitted in partial satisfaction of the requirements for the degree of MASTER OF SCIENCE in Computer Engineering by Trupti Deepak Naik SPRING 2015 AUTOMATIC TEST ENVIRONMENT SETUP A Project by Trupti Deepak Naik Approved by: __________________________________, Committee Chair Fethi Belkhouche, Ph.D. __________________________________, Second Reader Preetham Kumar, Ph.D. ____________________________ Date ii Student: Trupti Deepak Naik I certify that this student has met the requirements for format contained in the University format manual, and that this project is suitable for shelving in the Library and credit is to be awarded for the Project. __________________________, Graduate Coordinator ________________ Nikrouz Faroughi, Ph.D. Date Department of Computer Engineering iii Abstract of AUTOMATIC TEST ENVIRONMENT SETUP by Trupti Deepak Naik Manual verification in industry testing is a very complex and tedious process. Verification test engineers need to carefully go through various application screens, make the correct oscilloscope setups to get the expected results, try various input combinations and compare the results with the expected behavior. Furthermore, this type of testing is repetitive in nature. With the introduction of the new chips and/or new firmware releases, Automatic Test Environment (ATE) is becoming widely used to address the limitations of the traditional verification testing methods. This project focuses on creating an automated test environment for Solid State Devices (SSD) hardware verification testing. The project will contribute in making the tedious process of manual testing simpler and more time efficient for verification engineers. The project is implemented using Python Scripting Language and Test Environment Suite libraries from Agilent Command Expert tool. -
Anritsu 2002.Pdf
CONTENTS Outline of Anritsu Corporation . 1 How to Use This Catalog . 2 Product Support Literature . 3 Sales, Shipping, and Service Information . 4 Sales Network . 7 Alphabetical Index . 11 Model Number Index . 15 New Products . 23 Quality and Reliability Assurance System . 541 Request for measuring instruments not appearing in this catalog will also be accepted. ................................................. Optical Measuring Instruments 37 • Tunable Laser Source • Optical Component Tester • SLD Light Source • Stabilized Light Source • Optical Power Meters 1 • Multi Channel Box • Optical Loss Test Set • Optical Time Domain Reflectometers • Optical Spectrum Analyzer • WDM Network Tester • Optical Amplifier Test System • Optical Channel Selector • E/O, O/E Converter • Optical Directional Coupler • Others Digital Link Measuring Instruments......................................... 129 2 • Pulse Pattern Generators • Error Detectors • 10 GHz Jitter Analyzer • Digital Data Analyzers • SONET/SDH/PDH/ATM Analyzers • Portable 2.5G/10G Analyzer • Data Quality Analyzer • ATM Quality Analyzer • PCM Channel Analyzer • Digital Transmission Analyzer • STM/SONET Analyzer • PCM Codec Analyzer Data Communications Measuring Instruments .................. 195 3 • Network Data Analyzer • Data Transmission Analyzer Digital Mobile Communications Measuring Instruments ........ 205 4 • Digital Mobile Radio Transmitter Testers • Digital Modulation Signal Generators • Signalling Testers • Radio Communication Analyzers • W-CDMA Area Tester • Radio Communication -
Built-In Self Training of Hardware-Based Neural Networks
Built-In Self Training of Hardware-Based Neural Networks A thesis submitted to the Division of Research and Advanced Studies of the University of Cincinnati in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in the Department of Electrical Engineering and Computer Science of the College of Engineering and Applied Science November 16, 2017 by Thomas Anderson BS Electrical Engineering, University of Cincinnati, April 2017 Thesis Advisor and Committee Chair: Dr. Wen-Ben Jone Abstract Artificial neural networks and deep learning are a topic of increasing interest in computing. This has spurred investigation into dedicated hardware like accelerators to speed up the training and inference processes. This work proposes a new hardware architecture called Built-In Self Training (BISTr) for both training a network and performing inferences. The architecture combines principles from the Built-In Self Testing (BIST) VLSI paradigm with the backpropagation learning algorithm. The primary focus of the work is to present the BISTr architecture and verify its efficacy. The development of the architecture began with analysis of the backpropagation algorithm and the derivation of new equations. Once the derivations were complete, the hardware was designed and all of the functional components were tested using VHDL from the bottom to top level. An automatic synthesis tool was created to generate the code used and tested in the experimental phase. The application tested during the experiments was function approximation. The new architecture was trained successfully for a couple of the test cases. The other test cases were not successful, but this was due to the data representation used in the VHDL code and not a result of the hardware design itself. -
Survey of Electronic Hardware Testing Types, ATE Evolution & Case Studies
Published by : International Journal of Engineering Research & Technology (IJERT) http://www.ijert.org ISSN: 2278-0181 Vol. 6 Issue 11, November - 2017 Survey of Electronic Hardware Testing Types, ATE Evolution & Case Studies Manjula C Dr. D. Jayadevappa Assistant Professor, EEE Dept., Professor, The Oxford College of Engineering, Bangalore Electronics Instrumentation Dept., JSSATE, Bangalore Abstract - I have undertaken exhaustive survey, to bring out this technical paper covering - Testing principle, Levels, Types, Process, VLSI or Chip testing, Automatic Test equipment (ATE) – configuration, evolution, three case studies of FPGA interfaced with ATE, FPGA generating ATG for ATE and FPGA used with PC scope for VLSI / Chip testing etc. Keywords- Types of testing, Principle of testing, Levels of testing, ATE, Evolution of ATE Testing. INTRODUCTION Fig.1: Basic Testing Approach Testing is an experiment in which the system is exercised C. Level of Testing and its resulting response is analyzed to check its behavior Testing a die (chip) can occur at the following levels: [1]. If incorrect behavior is detected, the system is diagnosed Wafer level and locates the cause of the misbehavior. Diagnosis requires Packaged chip level the knowledge of the internal structure of the system under Board level test. System level A. Importance of Testing Field level In Today‘s Electronics world, more time is required for testing rather than design and fabrication. When the D. Types of Testing circuit/device is developed, it is necessary to determine the Manual testing and Automated Testing: functional and timing specifications of the circuit/device. Devices can be tested in two ways, manually and When the multiple copies of a circuit are manufactured, it is automatically. -
Computer Aided Design Solutions for Testability and Security Qihang Shi University of Connecticut - Storrs, [email protected]
University of Connecticut OpenCommons@UConn Doctoral Dissertations University of Connecticut Graduate School 8-18-2017 Computer Aided Design Solutions for Testability and Security Qihang Shi University of Connecticut - Storrs, [email protected] Follow this and additional works at: https://opencommons.uconn.edu/dissertations Recommended Citation Shi, Qihang, "Computer Aided Design Solutions for Testability and Security" (2017). Doctoral Dissertations. 1640. https://opencommons.uconn.edu/dissertations/1640 Computer Aided Design Solutions for Testability and Security Qihang Shi, Ph.D. University of Connecticut, 2017 As technology down scaling continues, new technical challenges emerge for the Inte- grated Circuits (IC) industry. One direct impact of down-scaling in feature sizes leads to elevated process variations, which has been complicating timing closure and requiring classification of fabricated ICs according to their maximum performance. To address this challenge, speed-binning based on on-chip delay sensor measurements has been proposed as alternative to current speed-binning methods. This practice requires ad- vanced data analysis techniques for the binning result to be accurate. Down-scaling has also increased transistor count, which puts an increased burden on IC testing. In particular, increase in area and capacity of embedded memories has led to overhead in test time and loss test coverage, which is especially true for System-on-Chip (SOC) Qihang Shi, University of Connecticut, 2017 designs. Indeed, expected increase in logic area between logic and memory cores will likely further undermine the current solution to the problem, the hierarchical test ar- chitecture. Further, widening use of information technology led to widened security concerns. In today’s threat environment, both hardware Intellectual Properties (IP) and software security sensitive information can become target of attacks, malicious tamper- ing, and unauthorized access. -
Evaluation of Hardware Test Methods for VLSI Systems
Evaluation of Hardware Test Methods for VLSI Systems By Jens Eriksson LiTH-ISY-EX-ET--05/0315--SE 2005-06-07 Evaluation of Hardware Test Methods for VLSI Systems Master Thesis Division of Electronics Systems Department of Electrical Engineering Linköping Institute of Technology Linköping University, Sweden By Jens Eriksson LiTH-ISY- EX-ET--05/0315--SE Supervisor: Thomas Johansson Examiner: Kent Palmkvist 2005-06-07 Avdelning, Institution Datum Division, Department Date 2005-06-07 Institutionen för systemteknik 581 83 LINKÖPING Språk Rapporttyp ISBN Language Report category Svenska/Swedish Licentiatavhandling ISRN LITH-ISY-EX-ET--05/0315--SE X Engelska/English X Examensarbete C-uppsats Serietitel och serienummer ISSN D-uppsats Title of series, numbering Övrig rapport ____ URL för elektronisk version http://www.ep.liu.se/exjobb/isy/2005/315/ Titel Evaluation of Hardware Test Methods for VLSI Systems Title Författare Jens Eriksson Author Sammanfattning Abstract The increasing complexity and decreasing technology feature sizes of electronic designs has caused the challenge of testing to grow over the last decades. The purpose of this thesis was to evaluate different hardware test methods/approaches based on their applicability in a complex SoC design. Among the aspects that were investigated are test implementation effort, test efficiency and the performance penalties implicated by the test. This report starts out by presenting a general introduction to the basics of hardware testing. It then moves on to review available standards and methodologies. In the end one of the more interesting methods is investigated through a case study. The method that was chosen for the case study has been implemented on a DSP, and is rather new and not as prolific as many of the standards discussed in the report. -
Design of Jig for Automated PCB Testimg
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 4, Issue 4, April 2015 Design of Jig for Automated PCB Testimg Nilangi U. Netravalkar Sonia Kuwelkar Microelectronics, ETC dept., Asst. Prof. ETC dept., Goa College of Engineering, Goa College of Engineering Goa University, India. Goa University, India. Abstract— Paper includes hardware designing of PCB II. WHY AUTOMATED TESTING? test jig using Raspberry Pi that will be used for automated Automatic test equipment enables printed circuit board test testing of master card PCB used in X ray machines. and equipment test to be undertaken very faster than if it were Automated Test Euipment (ATE) will verify the PCB’s done manually. As time of production staff forms a major functionality and its behavior. The test procedure includes element of the overall production cost of an item of electronics sending of command frame from test jig to the DUT using equipment, it is necessary to reduce the production times as Raspberry Pi controller and receiving the response frame possible which can be achieved with the use of ATE, from the DUT. The command frame and the response automatic test equipment. frame are then compared which determines the test to be pass or fail. The test procedures includes testing of digital ATE systems are designed to reduce the amount of test time inputs outputs of the DUT and also other functionalities of needed to verify that a particular device works or to quickly the master card. The test is usually performed according find its faults before the part has a chance to be used in a final to the OEM test engineer, who defines the specifications consumer product. -
Test and Characterization Methodologies for Advanced Technology Nodes Darayus Adil Patel
Test and characterization methodologies for advanced technology nodes Darayus Adil Patel To cite this version: Darayus Adil Patel. Test and characterization methodologies for advanced technology nodes. Elec- tronics. Université Montpellier, 2016. English. NNT : 2016MONTT285. tel-01808874 HAL Id: tel-01808874 https://tel.archives-ouvertes.fr/tel-01808874 Submitted on 6 Jun 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Délivré par Université de Montpellier Préparée au sein de l’école doctorale I2S Et de l’unité de recherche LIRMM Spécialité : SYAM Présentée par DARAYUS ADIL PATEL TEST AND CHARACTERIZATION METHODOLOGIES FOR ADVANCED TECHNOLOGY NODES Soutenue le 5 Juillet 2016 devant le jury composé de M. Daniel CHILLET Professeur, Université de Président du Jury / Rennes Rapporteur M. Salvador MIR Directeur de Recherche Rapporteur CNRS, TIMA Mme. Sylvie NAUDET Team Leader, Examinateur STMicroelectronics M. Alberto BOSIO MCF HDR, Université de Examinateur Montpellier M. Patrick GIRARD Directeur de Recherche Directeur de Thèse CNRS, LIRMM M. Arnaud