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Test and Side-Channel Analysis of Asynchronous Circuits Ricardo Aquino Guazzelli

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Test and Side-Channel Analysis of Asynchronous Circuits Ricardo Aquino Guazzelli test and side-channel analysis of asynchronous circuits Ricardo Aquino Guazzelli To cite this version: Ricardo Aquino Guazzelli. test and side-channel analysis of asynchronous circuits. Micro and nanotechnologies/Microelectronics. Université Grenoble Alpes [2020-..], 2020. English. NNT : 2020GRALT070. tel-03206505 HAL Id: tel-03206505 https://tel.archives-ouvertes.fr/tel-03206505 Submitted on 23 Apr 2021 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. THÈSE Pour obtenir le grade de DOCTEUR DE L’UNIVERSITÉ GRENOBLE ALPES Spécialité : Nano Electronique et Nano Technologies (NENT) Arrêtée ministériel : 25 mai 2016 Présentée par Ricardo AQUINO GUAZZELLI Thèse dirigée par Laurent FESQUET préparée au sein du Laboratoire Techniques de l’Informatique et de la Microélectronique pour l’Architecture des systèmes intégrés (TIMA) dans l’École Doctorale Electronique, Electrotecnique, Automatique & Traitement du Signal (EEATS) Test and Side-channel Analysis of Asynchronous Circuits Thèse soutenue publiquement le 3 décembre 2020, devant le jury composé de : Laurent FESQUET Maître de Conférences, Université Grenoble Alpes, Directeur de thèse Bruno ROUZEYRE Professeur des Universités, Université de Montpellier, Examinateur Haralampos STRATIGOPOULOS Directeur de Recherche, Sorbonne Université, Rapporteur Alberto BOSIO Professeur des Universités, École Centrale Lyon, Rapporteur Giorgio DI NATALE Directeur de Recherche, Université Grenoble Alpes, Président "Se eu soubesse antes o que sei agora, erraria tudo exatamente igual." Humberto Gessinger Acknowledgements Acknowledgements I would like to thank to Giorgio Di Natale, Alberto Bosio, Haralampos Stratigopoulos and Bruno Rouzeyre for accepting the invitation to compose my thesis jury. I appreciate the remarks from Alberto and Haralampos, who participated as rapporteurs (referees) in my thesis and all comments and questions invoked during my defense. Here, I take a brief moment to acknowledge the commitment that my advisor Laurent Fesquet put on in order to see this thesis finished. I am quite aware that I allocated a reasonable amount of your time in some moments during this journey and this fact highlights the effort you have gave to help me. Without no doubt, your technical expertise gave me a proper direction, allowing me to pursuit a research with meaning, and your support put on track everything I was doing in the last three years. I really cannot express enough thanks for all the technical and administrative help you gave to me during the last years, and I hope can retributive that someday. Moreover, two other people were extremely important in my professional training and thus must be acknowledged here: Ney Calazans, who introduced to the the research on asynchronous design when I was in engineering school and since then I am trapped; and Matheus Moreira, who was always available to answer my questions and discuss the most wide range of subject. I own you for the microelectronic background I currently have and it was because of that I am here where I am now. Thank you immensely. Obviously, I have to thank my colleges at TIMA, who had to put up with me: Matheus, my bro, for all scientific discussions, ski days, beers, laughs and LAN parties; Thiago, for helping me during the first moments here in France and being such an iconic friend; Leonel, who also was here to help in the beginning, giving me a random nickname; Re- nato, who I did not in fact interact a lot in the first year of the thesis, but destiny brought us together as friends after catastrophic sequence of events; Yoan, who had to work with me to finish a testchip during the first COVID lockdown and spent countless hours with me discussing about asynchronous design, politics, goat cheese; Gregoire, who was vital for the testchip and had the patience to explain to me how LCS works; Pudu (a.k.a. Rodrigo Iga), for your friendship, mindful discussions and all invitations to go to the mountains and go skiing; Mohammed, one of the most interesting PhD students of the CDSI team (and possible of TIMA), for giving to us another perspective of life and providing such unique (and funny) moments during pause-café and happy hours; Medhi, for the advice to calm me down before the defense; Jérémy and its supply of comté; and Assia, Jean, Nils and Liège for all the moments in the lab and good discussions during the pauses-café. I also say thank to my Grenoble friends: Raupp and Vivian, for hosting me at my first day in Grenoble; Katyanne, for being such an incredible friend to me while tolerating my complaints about life; Natália, for the good talks and invitations to eat proper food from Minas, specially pão de queijo; Laura, for all the moments together, being able to talk and laugh even with the curveballs that life keep throwing at us; and Luis (a.k.a. Cocotas), for i Acknowledgements all your stories and sense of humor. I cannot pass this through without saying thank to my friends who accompanied me even thousands of kilometers away: Guilherme (a.k.a Gnomo), for your time, friendship and ability to piss me off; Marcelo (a.k.a Gordo), who started engineering school with me at 2009 and I still can’t get rid of him; and the international couples: Ana and Gibiluka, Douglas and Carol, and Bruno and Karine. Another important person I have to mention here is my lovely Caroline, who helped me go through the final lap of my thesis and has been an incredible partner since the beginning. I thank you for your care and and for being my “guinea pig” when I cook. The best for the last, I would like to express my gratitude to my family: Mom and dad, for all your love and care with me all these years; All my character and moral concepts are inherited from you and I appreciate everything you taught along the years; Gui, for annoying me all the time but also being an unique brother. Your presence in my life surely shaped me in who I am now; and finally, my incredible grandma Teresinha Xavier Aquino, who I had the honor to live with when I moved to Porto Alegre. You are the reason of me chasing a better education and reach objectives I would never think about before. I could say it is not a coincidence that I am living in France now, isn’t it? ii Contents Acknowledgements................................i Contents...................................... iv Introduction1 I Asynchronous Circuits8 1 Asynchronous Design9 1.1 Asynchronous Channels and Handshake Protocols............. 10 1.2 Handshake Implementation Concepts................... 12 1.2.1 The C-element........................... 12 1.2.2 Non-linear Structures........................ 14 1.3 Bundled-Data Channels........................... 15 1.3.1 Bundled-Data Implementations.................. 17 1.4 Quasi-Delay Insensitive Channels..................... 18 1.4.1 The QDI Limitation........................ 20 1.4.2 QDI Implementations........................ 21 1.5 Conclusions................................. 24 II At-speed Test for Asynchronous Bundled-data Circuits 26 2 State-of-the-Art on Digital and Asynchronous Testing 27 2.1 Stuck-at Faults............................... 28 2.2 Path-Delay Faults.............................. 29 2.3 At-speed Testing.............................. 30 2.4 Digital Design-for-Testability and Scan-based Design........... 32 2.5 Asynchronous Testing........................... 35 2.6 Conclusions................................. 38 3 Proposed At-speed DfT Architecture for Bundled-data Design 40 3.1 Problem Statement............................. 41 iv Contents 3.2 Overview Architecture and Testing Signals................ 42 3.3 Test Cycle.................................. 44 3.4 Initialization................................. 44 3.5 Checking Circuit Correctness........................ 46 3.6 Retrieving Path-Delay Information with Local Clock Sets......... 46 3.7 Testing Non-linear Structures........................ 48 3.8 Compatibility with Traditional Stuck-at Testing.............. 49 3.9 Study-case Circuits............................. 50 3.9.1 A simple circuit: 2-bit adder.................... 50 3.9.2 A more complex circuit: 128-bit AES cryptocore......... 58 3.10 Conclusions................................. 62 III Side-channel Analysis of Asynchronous Circuits 64 4 State-of-the-Art on Hardware Trojan Detection 65 4.1 Hardware Trojan Model and Taxonomy.................. 66 4.1.1 Insertion.............................. 67 4.1.2 Abstraction Level.......................... 68 4.1.3 Activation Mechanism....................... 68 4.1.4 Effect................................ 69 4.1.5 Location.............................. 69 4.2 Hardware Trojan Detection......................... 71 4.2.1 Power Consumption Monitoring.................. 74 4.2.2 Delay Monitoring.......................... 74 4.2.3 EM, Thermal and Substrate Monitoring.............. 75 4.2.4 Multi-parameter Monitoring.................... 76 4.3 Conclusions................................. 76 5 Hardware Trojan Detection Technique for Asynchronous Circuits 79 5.1 Exploiting the Current Signatures of Asynchronous Circuits....... 83 5.2 Technique
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