Test and Side-Channel Analysis of Asynchronous Circuits Ricardo Aquino Guazzelli
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TFT Asynchronous Microprocessor on Plastic
7.2 / M. Miyasaka Current Status of Flexible Microelectronics; TFT Asynchronous Microprocessor on Plastic Mitsutoshi MIYASAKA, Nobuo KARAKI 1) and Tatsuya SHIMODA 2) Seiko Epson Corporation Flexible Microelectronics Project 1) Technology Platform Research Center 2) Corporate R&D Tel:81-266-61-1211, Fax:81-266-61-0674, E-mail: [email protected] Thin film transistors (TFTs) are field-effect accordance with the scaling rule for nearly half a transistors that can be used to create large-scale century. Though we hope for further advancement, the integrated (LSI) circuits. The combination of Suftla technology seems to be reaching its limits. technology and high-performance TFTs has the Theoretically the silicon band-gap limits the lowest potential to foster the rise of a new flexible voltage to approximately 0.5 V. In addition, there microelectronics industry. This paper reviews the appear to be serious technical difficulties in achieving history of Suftla technology and discusses the current finer patterning and thinner gate-dielectric. From a status of flexible microelectronics, a TFT business perspective, the advantages gained by further asynchronous microprocessor. We are sure that there scaling are spoiled by the high research, development is a best fit between the advantages of the and fabrication costs. Taking these facts into account, asynchronous circuit and the electrical properties we propose improving semiconductor devices this TFTs possess, because the asynchronous circuit century by eradicating the notion that LSI devices overcomes the deviation of transistor characteristics, must be made on silicon wafers. is free from the signal delay problem and does not Suftla (surface-free technology by laser generate a large amount of heat. -
SCAN CHAIN BASED HARDWARE SECURITY Xi Chen, Doctor of Philosophy, 2018 Dissertation Directed B
ABSTRACT Title of Dissertation: SCAN CHAIN BASED HARDWARE SECURITY Xi Chen, Doctor of Philosophy, 2018 Dissertation directed by: Professor Gang Qu Department of Electrical and Computer Engineering Hardware has become a popular target for attackers to hack into any computing and communication system. Starting from the legendary power analysis attacks discovered 20 years ago to the recent Intel Spectre and Meltdown attacks, security vulnerabilities in hardware design have been exploited for malicious purposes. With the emerging Internet of Things (IoT) applications, where the IoT devices are extremely resource constrained, many proven secure but computational expensive cryptography protocols cannot be applied on such devices. Thus there is an urgent need to understand the hardware vulnerabilities and develop cost effective mitigation methods. One established field in the semiconductor and integrated circuit (IC) industry, known as IC test, has the goal of ensuring that fabricated ICs are free of manufacturing defects and perform the required functionalities. Testing is essential to isolate faulty chips from good ones. The concept of design for test (DFT) has been integrated in the commercial IC design and fabrication process for several decades. Scan chain, which provides test engineer access to all the flip flops in the chip through the scan in (SI) and scan out (SO) ports, is the backbone of industrial testing methods and can be found in almost all the modern designs. In addition to IC testing, scan chain has found applications in intellectual property (IP) protection and IC identification. However, attackers can also leverage the controllability and observability of scan chain as a side channel to break systems such as cryptographic chips. -
Design and Implementation of High Speed Scan-Hold Flip Flop Based Shift Registers
e-ISSN (O): 2348-4470 Scientific Journal of Impact Factor (SJIF): 4.72 p-ISSN (P): 2348-6406 International Journal of Advance Engineering and Research Development Volume 4, Issue 12, December -2017 Design And Implementation of High Speed Scan-Hold Flip Flop based Shift Registers Kamal Prakash Pandey1, Gunjan Agrawal2 Department of Electronics and Communication Engg. SIET Allahabad Abstract: There has been a great increase in the number of electronic devices and the requirement of high speed design has been increasing exponentially. Here, thus the design of the flip-flop and the sequential logic devices has been a prime constraint in the overall speed performances. Thus to increase the overall speed performance of the flip-flip design, various methodologies have been proposed. The major shift registers used in various digital devices are Serial-In - Serial-Out, Universal shift registers has been developed. In our proposed work, we have proposed scan mode Flip-Flop and these flip-flop based Shift register design. The proposed modified design of the scan multiplexer based D Flip-Flip has been used for the implementation of various shift registers. Here, the Serial In Serial Out, Parallel In Parallel out, and Universal Shift Register design has been presented. Our proposed design is shown to have lower delay and minimize the gate count. The simulation has been done using Xilinx ISE 9.1 and Target device is to be SPARTAN 3E. Keywords: High speed, D-Flip flop, Shift registers, Scan Flip Flop, Gate count, Propagation delay I. INTRODUCTION Electronics market is leading the share of overall business day by day. -
One Shots and Alternatives in Synchronous Digital System Design
Lawrence Berkeley National Laboratory Lawrence Berkeley National Laboratory Title ONE SHOTS AND ALTERNATIVES IN SYNCHRONOUS DIGITAL SYSTEM DESIGN Permalink https://escholarship.org/uc/item/7tq8t8hn Author Hui, S. Publication Date 1979 Peer reviewed eScholarship.org Powered by the California Digital Library University of California LBL-8722 UC-37 7"> ONE SHOTS AND ALTERNATIVES IN SYNCHRONOUS DIGITAL SYSTEM DESIGN Steve Hui and John B. Meng January 1979 Prepared for the U. S. Department of Enemy under Contract W-7405-ENG-48 UtitAUigim LBL 8722 ONE SHOTS AND ALTERNATIVES IN SYNCHRONOUS DIGITAL SYSTEM DESIGN Steve Hui 8 John B. Meng January 1979 Prepared for the U.S. Department of Energy under Contract W-7405-ENG-48 NOTICE This re poll was pit pa ted is an account or work sponsored by the United States Government. Neither the United Sulci ooi the Umled Slates Depigment of Energy, nor any of their employees, nor any of their contractor*, lube on Ira clou, oi the If employees, nukes any warranty, express or implied, or auumei any legal liability •( response ill ly for (he accuracy, completene or usefulness of my information, anptiatui, product < process disclosed, c; represents thai ill me would no) infringe privately owned right*. !>TV»U;3 LBL 8722 (i) ONE SHOTS AND ALTERNATIVES IN SYNCHRONOUS DIGITAL SYSTEM DESIGN Steve Hui & John D. Meng The one shot or monostable multivibrator is quite often regarded as a "black sheep" in ditiqai integrated circuits. Its distinctions and versatility are well known and do not necessitate mentioning. Some of the potential problems with this black sheep are summarized as follows: 1. -
An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing
An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing Author Ivano Indino Supervisor Dr Ciaran MacNamee Submitted for the degree of Master of Engineering University of Limerick June 2017 ii Abstract An Open Source Platform and EDA Tool Framework to Enable Scan Test Power Analysis Testing Ivano Indino Scan testing has been the preferred method used for testing large digital integrated circuits for many decades and many electronic design automation (EDA) tools vendors provide support for inserting scan test structures into a design as part of their tool chains. Although EDA tools have been available for many years, they are still hard to use, and setting up a design flow, which includes scan insertion is an especially difficult process. Increasingly high integration, smaller device geometries, along with the requirement for low power operation mean that scan testing has become a limiting factor in achieving time to market demands without compromising quality of the delivered product or increasing test costs. As a result, using EDA tools for power analysis of device behaviour during scan testing is an important research topic for the semiconductor industry. This thesis describes the design synthesis of the OpenPiton, open research processor, with emphasis on scan insertion, automated test pattern generation (ATPG) and gate level simulation (GLS) steps. Having reviewed scan testing theory and practice, the thesis describes the execution of each of these steps on the OpenPiton design block. Thus, by demonstrating how to apply EDA based synthesis and design for test (DFT) tools to the OpenPiton project, the thesis addresses one of the most difficult problems faced by any new user who wishes to use existing EDA tools for synthesis and scan insertion, namely, the enormous complexity of the tool chains and the huge and confusing volume of related documentation. -
An Asynchronous Circuit Design Language System
Scholars' Mine Doctoral Dissertations Student Theses and Dissertations 1972 An asynchronous circuit design language system Gregory Martin Bednar Follow this and additional works at: https://scholarsmine.mst.edu/doctoral_dissertations Part of the Electrical and Computer Engineering Commons Department: Electrical and Computer Engineering Recommended Citation Bednar, Gregory Martin, "An asynchronous circuit design language system" (1972). Doctoral Dissertations. 194. https://scholarsmine.mst.edu/doctoral_dissertations/194 This thesis is brought to you by Scholars' Mine, a service of the Missouri S&T Library and Learning Resources. This work is protected by U. S. Copyright Law. Unauthorized use including reproduction for redistribution requires the permission of the copyright holder. For more information, please contact [email protected]. AN ASYNCHRONOUS CIRCUIT DESIGN. LANGUAGE SYSTEM by GREGORY MARTIN BEDNAR, 1944- A DISSERTATION Presented to the Faculty of the Graduate School of the UNIVERSITY OF MISSOURI-ROLLA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY T2781 in 157 pages ELECTRICAL ENGINEERING c. I 1972 23?261 ii ABSTRACT This paper presents a system for specifying the behavior of asynchronous sequential circuits. The system consists of a special purpose Asynchronous Circuit Design Language (ACDL), a translator and a flow table generation algorithm. The language includes many special features which permit quick and precise specification of terminal behavior. It is best suited for problems originating from a word description of the circuit's operation. The translator is written with the XPL Translator Writing System and is a syntax-directed compilation method. From the translated ACDL specifications, the flow table algorithm generates a primitive flow table which is the required input for the conventional synthesis procedures of asynchronous sequential circuits. -
Built-In Self Training of Hardware-Based Neural Networks
Built-In Self Training of Hardware-Based Neural Networks A thesis submitted to the Division of Research and Advanced Studies of the University of Cincinnati in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in the Department of Electrical Engineering and Computer Science of the College of Engineering and Applied Science November 16, 2017 by Thomas Anderson BS Electrical Engineering, University of Cincinnati, April 2017 Thesis Advisor and Committee Chair: Dr. Wen-Ben Jone Abstract Artificial neural networks and deep learning are a topic of increasing interest in computing. This has spurred investigation into dedicated hardware like accelerators to speed up the training and inference processes. This work proposes a new hardware architecture called Built-In Self Training (BISTr) for both training a network and performing inferences. The architecture combines principles from the Built-In Self Testing (BIST) VLSI paradigm with the backpropagation learning algorithm. The primary focus of the work is to present the BISTr architecture and verify its efficacy. The development of the architecture began with analysis of the backpropagation algorithm and the derivation of new equations. Once the derivations were complete, the hardware was designed and all of the functional components were tested using VHDL from the bottom to top level. An automatic synthesis tool was created to generate the code used and tested in the experimental phase. The application tested during the experiments was function approximation. The new architecture was trained successfully for a couple of the test cases. The other test cases were not successful, but this was due to the data representation used in the VHDL code and not a result of the hardware design itself. -
Test and Testability of Asynchronous Circuits
Test and Testability of Asynchronous Circuits Nastaran Nemati A thesis submitted for the degree of Doctor of Philosophy University of New South Wales June 2017 To Mum and Dad ORIGINALITY STATEMENT ‘I hereby declare that this submission is my own work and to the best of my knowl- edge it contains no materials previously published or written by another person, or substantial proportions of material which have been accepted for the award of any other degree or diploma at UNSW or any other educational institution, ex- cept where due acknowledgement is made in the thesis. Any contribution made to the research by others, with whom I have worked at UNSW or elsewhere, is explicitly acknowledged in the thesis. I also declare that the intellectual content of this thesis is the product of my own work, except to the extent that assistance from others in the project’s design and conception or in style, presentation and linguistic expression is acknowledged.’ Signed ................................................ Date .................................................... COPYRIGHT STATEMENT ‘I hereby grant the University of New South Wales or its agents the right to archive and to make available my thesis or dissertation in whole or part in the University libraries in all forms of media, now or here after known, subject to the provisions of the Copyright Act 1968. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation. I also authorise University Microfilms to use the 350 word abstract of my thesis in Dissertation Abstract International (this is applicable to doctoral theses only). -
Impact of C-Elements in Asynchronous Circuits
Impact of C-Elements in Asynchronous Circuits Matheus Moreira, Bruno Oliveira, Fernando Moraes, Ney Calazans Faculdade de Informática Pontifícia Universidade Católica do Rio Grande do Sul Porto Alegre, Brazil {matheus.moreira, bruno.scherer}@acad.pucrs.br {fernando.moraes, ney.calazans}@pucrs.br Abstract single cell level and the application, or core, level. For the Asynchronous circuits are a potential solution to address former scope, delay and power consumption were measured some of the obstacles in deep submicron (DSM) design. One through electrical simulations at the standard cell level after of the most frequently used devices to build asynchronous electrical extraction of the physical layout. For the latter circuits is the C-element, a device present as a basic building scope, the different C-elements were used to build block in several asynchronous design styles. This work asynchronous implementations of an oscillator ring and an measures the impact of three different C-element types. The RSA cryptographic core. A comparison of performance and paper compares the use of each implementation to build a real required silicon area of the case studies made it possible to case asynchronous circuit, an RSA cryptographic core, and scrutinize the systemic effect of using different C-element reports results of precise electrical simulations of each C- implementations when designing asynchronous circuits in element. Findings in this work show that previous results in DSM technologies. The rest of the paper is organized in seven sections. the literature about C-element implementation types must be Section II describes basic concepts on asynchronous circuits re-evaluated when using C-elements in DSM technologies. -
Asynchronous Control Circuit Design and Hazard Generation: Inertial Delay and Pure Delay Models
oF a9'3-A *l* It Asynchronous Control Circuit Design and Hazard Generation: Inertial Delay and Pure Delay Models by Nozar Tabrizi B.S.E.E (Sharif University of Technology) 1980 M.S.E.E (Sharif University of Technology) 1988 A thesis submitted for the degree of Doctor of Philosophy in the Centre for High Performance Integrated Technologies and Systems (CHiPTec) Department of Electrical and Electronic Engineering The University of Adelaide June 1997 Table of Contents 1 Motivation for Asynchronous Circuits I 1.1 Introduction. .. 1 1.1.1 Clock skew ,.2 1.I.2 Power consumption............. ..5 Ll.3 Variable computation time.. ..6 1.1.4 Modularity and upgradiblity ..8 t.2 Organization ............... 10 2 Delay constraints and Design Techniques of Asynchronous Control Circuits ..................... L3 2.t Introduction t3 2.1.1 Huffman classical method..... 14 2.1.2 Speed independent circuits 14 2.1.3 Delay insensitive circuits 15 2.2 State based techniques .16 2.2.1 Classical Huffman method............ .16 2.2.2 One-hot coding..... t9 2.2.3 Timing requirements in the Huffman methodology.............. ..... 22 2.2.4 Friedman and Menon's methods to design multiple input change asynchronous circuits. 23 2.3 Burst mode or self clocked circuits ....................26 2.3.1 Burst mode circuits using controlled excitation and edge triggered flip-flops..... .26 2.3.2 Locally clocked asynchronous state machines 29 2.3.3 Q-Modules 32 2.3.4 3D Asynchronous circuits...... 35 2.4 Muller's speed independent circuit theory 36 2.4.1 Introduction... 36 2.4.2 Two restricted types of speed independent circuits .39 2.4.3 A flow table based speed independent circuit realization.. -
Computer Aided Design Solutions for Testability and Security Qihang Shi University of Connecticut - Storrs, [email protected]
University of Connecticut OpenCommons@UConn Doctoral Dissertations University of Connecticut Graduate School 8-18-2017 Computer Aided Design Solutions for Testability and Security Qihang Shi University of Connecticut - Storrs, [email protected] Follow this and additional works at: https://opencommons.uconn.edu/dissertations Recommended Citation Shi, Qihang, "Computer Aided Design Solutions for Testability and Security" (2017). Doctoral Dissertations. 1640. https://opencommons.uconn.edu/dissertations/1640 Computer Aided Design Solutions for Testability and Security Qihang Shi, Ph.D. University of Connecticut, 2017 As technology down scaling continues, new technical challenges emerge for the Inte- grated Circuits (IC) industry. One direct impact of down-scaling in feature sizes leads to elevated process variations, which has been complicating timing closure and requiring classification of fabricated ICs according to their maximum performance. To address this challenge, speed-binning based on on-chip delay sensor measurements has been proposed as alternative to current speed-binning methods. This practice requires ad- vanced data analysis techniques for the binning result to be accurate. Down-scaling has also increased transistor count, which puts an increased burden on IC testing. In particular, increase in area and capacity of embedded memories has led to overhead in test time and loss test coverage, which is especially true for System-on-Chip (SOC) Qihang Shi, University of Connecticut, 2017 designs. Indeed, expected increase in logic area between logic and memory cores will likely further undermine the current solution to the problem, the hierarchical test ar- chitecture. Further, widening use of information technology led to widened security concerns. In today’s threat environment, both hardware Intellectual Properties (IP) and software security sensitive information can become target of attacks, malicious tamper- ing, and unauthorized access. -
Evaluation of Hardware Test Methods for VLSI Systems
Evaluation of Hardware Test Methods for VLSI Systems By Jens Eriksson LiTH-ISY-EX-ET--05/0315--SE 2005-06-07 Evaluation of Hardware Test Methods for VLSI Systems Master Thesis Division of Electronics Systems Department of Electrical Engineering Linköping Institute of Technology Linköping University, Sweden By Jens Eriksson LiTH-ISY- EX-ET--05/0315--SE Supervisor: Thomas Johansson Examiner: Kent Palmkvist 2005-06-07 Avdelning, Institution Datum Division, Department Date 2005-06-07 Institutionen för systemteknik 581 83 LINKÖPING Språk Rapporttyp ISBN Language Report category Svenska/Swedish Licentiatavhandling ISRN LITH-ISY-EX-ET--05/0315--SE X Engelska/English X Examensarbete C-uppsats Serietitel och serienummer ISSN D-uppsats Title of series, numbering Övrig rapport ____ URL för elektronisk version http://www.ep.liu.se/exjobb/isy/2005/315/ Titel Evaluation of Hardware Test Methods for VLSI Systems Title Författare Jens Eriksson Author Sammanfattning Abstract The increasing complexity and decreasing technology feature sizes of electronic designs has caused the challenge of testing to grow over the last decades. The purpose of this thesis was to evaluate different hardware test methods/approaches based on their applicability in a complex SoC design. Among the aspects that were investigated are test implementation effort, test efficiency and the performance penalties implicated by the test. This report starts out by presenting a general introduction to the basics of hardware testing. It then moves on to review available standards and methodologies. In the end one of the more interesting methods is investigated through a case study. The method that was chosen for the case study has been implemented on a DSP, and is rather new and not as prolific as many of the standards discussed in the report.