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Hybrid Synchronous / Asynchronous Design HYBRID SYNCHRONOUS / ASYNCHRONOUS DESIGN A Dissertation Presented to the Faculty of the Graduate School of Cornell University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Filipp A Akopyan May 2011 c 2011 Filipp A Akopyan ALL RIGHTS RESERVED HYBRID SYNCHRONOUS / ASYNCHRONOUS DESIGN Filipp A Akopyan, Ph.D. Cornell University 2011 In this new era of high-speed and low-power VLSI circuits, the question of which circuit family is best for a given application has become much more relevant. From a designer's point of view, process technology scaling continues to reveal undesirable device behavior. Thus, a designer has to make decisions not only at the micro-architectural scale, but also at a lower, circuit-level scale. However, common circuit families are not sufficient to solve modern engineering problems in many cases. Our goal is to provide resources that will allow designers to select the circuit family that yields the best results in terms of power, area, and performance metrics for each application, with minimal human input. Using our techniques, this choice can be made in a timely manner without in-depth knowledge of each circuit family. We propose an improved hybrid synchronous / asynchronous toolflow that offers significant reduction in the design cycle time and we advise on how our work can be extended to various types of circuit families for any given technology node. We describe tools that we have developed to allow designers to implement their projects using both synchronous and asynchronous circuit families. We also present the cosimulation environment that we have developed to allow designers to run complex digital and analog simulations of various circuits at different levels of abstraction with minimal setup effort. Finally, we demonstrate a highly optimized synchronous-asynchronous interface that works as a bridge in designs where part of the logic is implemented asynchronously within a globally synchronous system. Biographical Sketch Filipp Akopyan was born in Moscow, Russia, where he grew up and lived until the age of 15. Filipp completed middle school in Russia and high school in the United States (at Spring Valley, NY). Filipp joined Rensselaer Polytechnic Institute (in Troy, NY) in September of 2001 and graduated number one in the School of Engineering with a Bachelor's Degree in Electrical Engineering in May of 2004. His concentrations at RPI included electronic circuit design and signal processing. The author has been enrolled in a joint M.S. / Ph.D. program at Cornell University since September 2004. At Cornell his main interests included high- speed VLSI circuits (including 3-D integrated circuits and neuromorphic systems) that operate under extreme conditions and withstand process variations. He has also developed low-power asynchronous systems for signal processing. Filipp is a part of the Asynchronous VLSI (AVLSI) research group led by Pro- fessor Rajit Manohar. Filipp's office is located in Upson Hall, 358 in the Computer Systems Laboratory. iii \Desire to become the best at what I do drives my life." dedicated to my family and friends; thanks for all the support ...yours truly iv Acknowledgments First of all I would like to thank my advisor, Professor Rajit Manohar, who always offered support and encouragement even in the toughest days of my graduate career. His enormous help, ideas and willingness to discuss my (at times risky and unconventional) ideas, allowed me to think outside of the box and perform the work outlined in this thesis. I thank my close friends and colleagues at AVLSI and the entire CSL staff. Special thanks go to Carlos Tadeo Ortega Otero, Ilya Ganusov, David Fang and Virantha Ekanayake for all the valuable advices that they have offered to me during my studies. I have been lucky to have such loyal and smart friends surround me in graduate school. My appreciation and endless love go to my family (Andrey, Galina, Seva, Alexander and Vera), especially to my mother, Yuliya, who has always been there for me and gave up everything she could in order to make my life better. I would like to thank Sergey Rakov for all of his valuable professional and personal advices throughout my life and for getting me interested in the Electrical Engineering field. My gratitude goes to my lifetime friends: Vadim Zipunnikov, Borjan Gagoski, Peter Paliwoda, Chin-Chen Lee and Jan Kostecki for helping me deal with diffi- culties of graduate life. I would also like to thank Alena for her love and patience through these last few years. This research was supported in part by National Science Foundation and IBM. v Table of Contents 1 Introduction 1 1.1 Motivation . 1 1.2 Background . 3 1.3 Proposed Toolflow Basics . 5 1.4 Asynchronous Design Methods and Challenges . 6 1.5 Toolflow Evaluation . 7 1.6 Organization of This Thesis . 8 2 Toolflow 10 2.1 Toolflow Comparison . 10 2.1.1 Conventional Toolflows . 10 2.1.2 Proposed Toolflow . 12 2.1.3 Proposed Simulator Chain . 14 2.2 Industrial Tools Used in the Flow . 16 2.2.1 Synchronous Digital Simulator . 16 2.2.2 Transistor-Level Analog Simulator . 16 2.3 Cornell AVLSI's Tools Overview . 16 2.3.1 Asynchronous Digital Simulator (PRSIM) . 16 2.3.2 Verilog-to-ACT . 17 2.3.3 Netlist Generator . 19 2.3.4 Automatic Cosimulation Environment Generator . 19 2.3.5 Circuit Family Libraries . 20 3 Automatic Cosimulation Environment Generator 22 3.1 Motivation . 22 3.2 Vision . 24 3.3 Auto Simulation Setup . 25 3.4 Overview . 27 3.5 Functionality . 30 3.6 Common Setup Parameters . 35 3.7 Sources and Sinks Library for Testing Environment . 44 3.8 Global Connections . 50 3.9 Output Files . 52 vi 4 Toolflow Evaluation 54 4.1 Benchmark Considerations . 54 4.2 Throughput Comparison . 56 4.3 Process Variations . 58 4.4 Power Analysis . 60 4.5 Design Space Analysis . 62 4.6 Designer Guidelines . 65 5 Asynchronous-to-Synchronous Interface with Discrete Timing 67 5.1 Motivation and Background . 67 5.1.1 Synchronous-to-Asynchronous Boundary . 68 5.1.2 Asynchronous-to-Synchronous Boundary . 71 5.2 Additional Asynchronous-to-Synchronous Interface Requirements . 72 5.3 Proposed Interface Overview . 74 5.4 Proposed Interface Detailed Description . 76 5.4.1 Input Stage of the Synchronizer . 78 5.4.2 Flip-Flop Implementation Details . 81 5.4.3 Synchronous Circuitry . 86 5.4.4 Synchronous Register Implementation . 89 5.4.5 Synchronizer Output Stage . 92 6 Additional Related Research 94 7 Suggestions for Further Improvements 96 8 Conclusion 99 Bibliography 101 vii List of Figures 1.1 Synchronous and Asynchronous Time Domains . 4 2.1 Industrial Toolflow . 11 2.2 Asynchronous Toolflow . 12 2.3 Proposed Toolflow . 13 2.4 Sample Simulator Chain . 15 2.5 Verilog-to-ACT Conversion Table . 18 2.6 Verilog-to-ACT Synchronous to Asynchronous Transformation . 18 3.1 Overview of COSIM's Functionality . 31 4.1 ITC-99 Benchmarks and their Functionalities . 55 4.2 ITC-99 Benchmarks Structure . 55 4.3 ITC-99 Benchmarks: Synchronous and Asynchronous Implementa- tions in MHz . 57 4.4 ITC-99 Benchmarks: Asynchronous Throughput Normalized . 57 4.5 Process Variations: Synchronous Implementations . 58 4.6 Process Variations: Asynchronous Implementations . 58 4.7 Process Variations: SYNC and ASYNC Implementations . 59 4.8 ITC-99 Benchmarks: PWR break-even frequency in kHz . 61 4.9 Power for b01 in Watts: Asynchronous Implementation . 63 4.10 Power for b01 in Watts: Synchronous Implementation . 63 4.11 Power for b01: Diff between ASYNC and SYNC Implementations . 64 5.1 Two-Way Arbiter Structure with filter . 69 5.2 Mutual Exclusion Element with QDI handshake . 70 5.3 On-chip Globally Synchronous Network . 74 5.4 Synchronizer Overall Diagram . 75 5.5 Synchronizer Detailed Diagram . 77 5.6 Input Stage of the Synchronizer . 78 5.7 Modified PCEHB Element . 80 5.8 C2MOS flip-flop with conditional feedback . 84 5.9 C2MOS flip-flop with full combinational feedback . 85 5.10 Synchronous Comparator and Ouput Stage of the Synchronizer . 86 5.11 A Variant of Synchronous Comparator Implementation . 88 viii 5.12 Synchronous Register / Flip-Flop Control Signals . 90 ix List of Abbreviations ACT Cornell's Asynchronous Circuit Toolkit CHP Communicating Hardware Processes, hardware description language CMOS Complementary Metal-Oxide Semiconductor EDA Electronic Design Automation GND Ground Power Supply Node Netlist circuit description at some level of abstraction HSE Handshaking Expansion NFET n-diffusion Field Effect Transistor PFET p-diffusion Field Effect Transistor PRS Production Rule Set, transistor pull-up and pull-down description QDI Quasi-Delay Insensitive Sink data token consumer Source data token generator SPICE transistor-level circuit description TSMC Taiwan Semiconductor Manufacturing Company VDD Positive Power Supply Node Verilog Hardware Description Language for electronic system modeling VLSI Very Large Scale Integration x Chapter 1 Introduction 1.1 Motivation Complexity of modern integrated circuits continues to increase with shrinking fea- ture size. As a result of that, timing closure, power management and undesirable transistor behavior at high operating speeds have become increasingly important and challenging to deal with [34]. The main purpose of Computer-Aided Design (CAD) tools is to help designers combat these issues. Contemporary industrial design flow is well understood, doc- umented, and constantly being updated and improved by large-scale CAD corpora- tions. However, the limitations of current design flow are also well-understood [6], especially in the current era of low-power/high speed VLSI, where technology scal- ing leads to more parasitic analog effects that are only revealed during low-level simulations at the "end" of the design cycle. Consequently, VLSI design is becoming more complex and more time consum- ing.
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