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Test and Testability of Asynchronous Circuits Test and Testability of Asynchronous Circuits Nastaran Nemati A thesis submitted for the degree of Doctor of Philosophy University of New South Wales June 2017 To Mum and Dad ORIGINALITY STATEMENT ‘I hereby declare that this submission is my own work and to the best of my knowl- edge it contains no materials previously published or written by another person, or substantial proportions of material which have been accepted for the award of any other degree or diploma at UNSW or any other educational institution, ex- cept where due acknowledgement is made in the thesis. Any contribution made to the research by others, with whom I have worked at UNSW or elsewhere, is explicitly acknowledged in the thesis. I also declare that the intellectual content of this thesis is the product of my own work, except to the extent that assistance from others in the project’s design and conception or in style, presentation and linguistic expression is acknowledged.’ Signed ................................................ Date .................................................... COPYRIGHT STATEMENT ‘I hereby grant the University of New South Wales or its agents the right to archive and to make available my thesis or dissertation in whole or part in the University libraries in all forms of media, now or here after known, subject to the provisions of the Copyright Act 1968. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation. I also authorise University Microfilms to use the 350 word abstract of my thesis in Dissertation Abstract International (this is applicable to doctoral theses only). I have either used no substantial portions of copyright material in my thesis or I have obtained permission to use copyright material; where permission has not been granted I have applied/will apply for a partial restriction of the digital copy of my thesis or dissertation.’ Signed ................................................ Date .................................................... Acknowledgments Firstly, I would like to express my gratitude to my supervisor Prof. Mark C. Reed for the continuous support of my PhD study and related research. His steady guidance and motivation helped me greatly at all stages of my work, from early research through to thesis-writing. Besides my supervisor, I would like to give my heartfelt thanks to Prof. Paul Beckett, Mr. Karl Fant and Prof. Sri Parameswaran for their insightful comments and encour- agement, but also for asking me the hard questions which encouraged me to broaden my research. I must thank Ms. Dominique Kazan for her patience, support and advice during my project, Ms. Denise Russell for generously donating her time before my submission to proofreading my thesis, and Ms. Maya Gunawardena, from the Academic Language and Learning Unit of UNSW Canberra, who helped me improve my writing and pre- sentation skills at several stages throughout the project. I would also like to thank my wonderful friends, Mona, Sanaz, Maryam, Negin, Nadia, Mansoureh, Elham and Saba; I’ve known some of you for most of my life and knowing you are always there helps me in difficult times. I am most grateful to my partner John for supporting me during my PhD studies in every possible way, from reviewing my paper while he himself was on a conference trip to spending so many weekends looking after me while I was writing up my thesis. His support, encouragement, patience and unwavering love were unquestionably the bedrock upon which the past couple of years of my life have been built. I would like to thank my parents and my brothers for supporting me throughout writing this thesis and in my life in general. I thank my parents, for their faith in me and for giving me the freedom to be as ambitious as I wished. I thank them for being loving, understanding and patient when I couldn’t look after them as much as I would have liked. I thank my brother and sister-in-law Nima and Homa for being there for me, every single time. I am grateful to my other brother Mani and his wife Arsha, for being such lovely and lively people in my life. I also thank John’s parents, Ian and Jane, and his sister and her partner Katherine and Betsie, who provided me with unending encouragement and support. Through all of this love, patience and support I’ve been able to complete this long dissertation journey. Thank you all. I couldn’t have done it without you. ix Abstract The ever-increasing transistor shrinkage and higher clock frequencies are causing seri- ous clock distribution, power management, and reliability issues. Asynchronous design is predicted to have a significant role in tackling these challenges because of its dis- tributed control mechanism and on-demand, rather than continuous, switching activity. Null Convention Logic (NCL) is a robust and low-power asynchronous paradigm that introduces new challenges to test and testability algorithms because 1) the lack of deterministic timing in NCL complicates the management of test timing, 2) all NCL gates are state-holding and even simple combinational circuits show sequential be- haviour, and 3) stuck-at faults on gate internal feedback (GIF) of NCL gates do not always cause an incorrect output and therefore are undetectable by automatic test pat- tern generation (ATPG) algorithms. Existing test methods for NCL use clocked hardware to control the timing of test. Such test hardware could introduce metastability issues into otherwise highly robust NCL devices. Also, existing test techniques for NCL handle the high-statefulness of NCL circuits by excessive incorporation of test hardware which imposes additional area, propagation delay and power consumption. This work, first, proposes a clockless self-timed ATPG that detects all faults on the gate inputs and a share of the GIF faults with no added design for test (DFT). Then, the efficacy of quiescent current (IDDQ) test for detecting GIF faults undetectable by a DFT- less ATPG is investigated. Finally, asynchronous test hardware, including test points, a scan cell, and an interleaved scan architecture, is proposed for NCL-based circuits. To the extent of our knowledge, this is the first work that develops clockless, self-timed test techniques for NCL while minimising the need for DFT, and also the first work conducted on IDDQ test of NCL. The proposed methods are applied to multiple NCL circuits with up to 2,633 NCL gates (10,000 CMOS Boolean gates), in 180 and 45 nm technologies and show average fault coverage of 88.98% for ATPG alone, 98.52% including IDDQ test, and 99.28% when incorporating test hardware. Given that this fault coverage includes detection of GIF faults, our work has 13% higher fault coverage than previous work. Also, because our proposed clockless test hardware eliminates the need for double-latching, it reduces the average area and delay overhead of previous studies by 32% and 50%, respectively. xi xii Contents Acknowledgments ix Abstract xi List of Figures xvii List of Tables xxi Peer-Reviewed Publications based on this Thesis xxiii Acronyms xxvii 1 Introduction 1 1.1 Roadmap of semiconductor technology . .1 1.2 Past, present and future of asynchronous designs . .5 1.2.1 Processors . .6 1.2.2 System-on-Chips (SoCs) . .9 1.3 Pros and cons of asynchronous design . 10 1.4 Key challenges involved in asynchronous design . 11 1.4.1 CAD tools . 11 1.4.2 Test and testability . 12 1.5 Description of Null Convention Logic (NCL) . 12 1.5.1 Challenges of testing Null Convention Logic (NCL) . 14 1.6 Outline of thesis . 15 1.6.1 Objectives . 15 1.6.2 Implementation and evaluation methods . 15 1.6.3 Contributions of this research . 16 1.7 Previous work . 17 1.7.1 Test and testability of asynchronous circuits . 17 1.7.2 Test and testability of delay-insensitive circuits . 18 1.7.3 Test and testability of Null Convention Logic (NCL) . 18 1.7.3.1 Previous work on IDDQ testing of NCL circuits . 20 1.8 Structure of thesis . 22 1.9 Summary . 22 xiii xiv Contents 2 Background 25 2.1 Null Convention Logic (NCL) . 25 2.1.1 Structure of NCL gates . 26 2.1.1.1 Static NCL gates . 27 2.1.1.2 Semi-static NCL gates . 28 2.1.2 NCL gate library . 28 2.1.3 Timing and control in NCL . 28 2.1.3.1 NCL is hazard-free and glitch-less . 30 2.2 Test and testability . 31 2.2.1 Basics of test . 32 2.2.1.1 Fault, error, failure . 32 2.2.1.2 Cost of test - rule of 10 . 33 2.2.1.3 Fault model - single stuck-at fault . 35 2.2.1.4 Test technique evaluation . 36 2.2.2 Automatic test pattern generation (ATPG) . 37 2.2.2.1 Combinational ATPG . 37 2.2.2.2 Sequential ATPG . 38 2.2.3 Design For Test (DFT) . 39 2.2.3.1 Test point insertion . 39 2.2.3.2 Scan insertion . 40 2.2.3.3 Built-in Self-test (BIST) . 42 2.2.4 IDDQ test . 45 2.3 Summary . 47 3 Automatic Test Pattern Generation for NCL 49 3.1 The number of required test vectors per fault . 50 3.1.1 Fault activation in NCL using one Null or one Data . 50 3.1.2 Fault propagation in NCL using one Null or one Data . 50 3.2 ATPG timing . 55 3.2.1 ATPG timing using a clock . 55 3.2.2 From the DUT . 55 3.2.3 From a golden model . 55 3.2.4 From both the DUT and a golden model .
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