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The Computer-Aided Generation of Flow-Tables for Asynchronous Sequential Circuits

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The Computer-Aided Generation of Flow-Tables for Asynchronous Sequential Circuits View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Missouri University of Science and Technology (Missouri S&T): Scholars' Mine Scholars' Mine Masters Theses Student Theses and Dissertations 1968 The computer-aided generation of flow-tables for asynchronous sequential circuits Ronald Lee Altman Follow this and additional works at: https://scholarsmine.mst.edu/masters_theses Part of the Electrical and Computer Engineering Commons Department: Recommended Citation Altman, Ronald Lee, "The computer-aided generation of flow-tables for asynchronous sequential circuits" (1968). Masters Theses. 5186. https://scholarsmine.mst.edu/masters_theses/5186 This thesis is brought to you by Scholars' Mine, a service of the Missouri S&T Library and Learning Resources. This work is protected by U. S. Copyright Law. Unauthorized use including reproduction for redistribution requires the permission of the copyright holder. For more information, please contact [email protected]. r.CHE CtJ}·lPUTER-AIDED GENERATION OF FLm.:-TABLES ?OR ASYNCHRONOUS SEQlJENTIAL CIRCUITS BY ,.,, ..... RONALD LEE ALTM.A.N / I CJi..f;, --------- A THESIS submitted to the faculty of THE Ul\IVERSITY OF HISSOURI - ROLlA in 1Ja·.:t j_al fi...:il fillrilent of the requirements for tbe Degree of H,.,;.STER OF SCIENCE IN ELECTRICAL ENGINEERING Rolla_, Missouri 1968 -------- Approved by !. ii ABSTRACT One step in the synthesis of asynchronous sequential circuits is the construction of a flow table. This paper discusses the requirements of a computer program to allow on-line generation of flow tables for asynchronous sequential circuits. Such topics as the form of the data entered into the program, the type of terminal required, the routines necessary for the designer to enter and correct data, and the internal data structure are discussed. An e.lgorithm for the generation of these flmv tables is alsc. presented~ iii ACKNOVJLEDGEMENTS The author wishes to express his sincere appreciation to Dr. James H. Tracey for his careful guidance throughout the entire project. The author also wishes to acknowledge the typing efforts of his wife, Barbara. iv TABLE OF CONTENTS ABSTRACT ii ACKNO~~EDGEMENTS iii LIST OF FIGURES v I. INTRODUCTION 1 II. DATA REPRESENTATION 7 III. EXTERNAL FORMAT 16 IV. DATA CORRECTION 19 v. INTERNAL DATA FOID-1AT 21 VI. FLOW TABLE GENERATION ALGORITHM 29 VII. CONCLUSION 37 BIBLIOGRAPHY 38 APPENDIX A, A Description of the Support 39 Routines Necessary for a CRT Terminal VITA 43 v LIST OF FIGURES Figure Page 1 Flow table for an asynchronous 2 sequential circuit. 2 Labled flow table. 3 3 The primitive-form flow table 5 for the DC S-R flip-flop. A typical timing diagram for 9 flow table of Figure 1. 5 The correspondence of the timing 10 diagram with flow table location. 6 Timing diagram information repre­ 12 sented as a sequence of code words. 7 Vertical representation of code 13 ~·JOrd sequence. 3 Sample flow table generation program. 17 9 Typical flow table segment with 24 two inputs and one output that could be generated by this program. 10 The flow table of Figure 9 repre­ 26 sented as a subscripted array. 11 Output don't-care values. 29 12 Flmv table generation algorithm. 32 I. INTRODUCTION Sequential switchin~ circuits are normally divided into two catagories, synchronous and asynchronous. The synchronous circuits make use of a clock which permits the circuit to respond only during certain time intervals as defined by the clock. In an asynchronous circuit there is no clock and the circuits are permitted to fur1ction at the full speed cap~il) i_lity of the gates. This ?aper will deal with asynchronous secp.1cntial circuits. A restriction on the type of asynchronous sequential circuits to be cons:'_dered here is th.:1t they operate in the fundamental mode and that only one input be allmved to change at a time. Circuits whtch operate in the ft_mdamental mode are constrained to operate under the cor:.di_tion that the ir:puts are never ch<~nged unless the cir- c~it is internally stable. Internal stability means that if the present input is maintained, there will be no further changes in the state of any signal lines. One of the Nost important tools in logical design is the floH table which was first of 'Jc-en1-cnt;al 'i .1'- .L. c;.L. rcuits .f ormula ted by Hur'"f man 1 in 1954. The standard representation of a flow table as shmvn in FisPre 1 is an array \.Jith the rm.:s representing the internal states, the colu.r.ms the input combinations, and the entries in the table repre­ senting the next internal state. The stable states are 2 shown in Figure 1 circled. Stable states are states where the next state is the same as the present state. The outputs in Figure 1 aJ..·e shown only with the stable states. XY 00 01 11 10 @YO s2 -- 6f0 1---· (911 (9/1 - sl Figure 1. Flow table for an asynchronous sequential circuit. The dashes in the column under X ~ 1, Y = 1 (Figure 1) aLe called ]on't-cares. Don't-care states are states t~at because of constraints on the inputs will never be entc;·,-,d, or if they are entered the designer does not care 'liJhac the m1tcome will be. With this being the case it is not necessary to specify what will happen under these conditions. To illustrate the operation and meaning of the flow table in F'igure 1 it has been redrawn and labels added in Figure 2. The operation of the flow table can be demonstrated by considering the case where the circnit is in internal state 1 with inputs of 00 (location C Figure 2). The next state is the same as the present state. The circuit is stable and the next state is circled. The output is 0, 3 s 2 H Figure 2. Labled flow table. and .s inc e t h c= c i r cui t is s tab 1 e i t \vi 11 r c rna in a t 0 u n t i 1 there is a change in the input. Now if input X becomes a 1, the inputs are now 10 in internal state s 1 (location D Ftgure 2), the next state is s 1 and the output is 0. If input X becomes a 0 (location C Figure 2L the next state It is a stable state and the output is 0. If the inputs chanse to 01 (location D Figure 2) the next state i.s S,...,. Ti1e next state now becomes the present state (location c: F Figure 2) and the output becomes l. The inputs are still 01 with the present state s2 (location F Figure 2). The next state is s2 : the output is 1 and the circuit is again stable. Thus, the entire operation of the circuit can be specified in flow table form and the output sequences for any given input sequence can be [cund in the manner just described. The flow table can be a ueans of conveying large amounts of information about the circuit in a very compact man~er. For example, the flow table of Figure 1 represents 4 a conventional DC S-R flip-flop. The word description of this flip-flop would be as follows: This circuit has two inputs X and Y and one output z. Z is to be off (at logic 0) vJhenever X but not Y is on (at logic 1). z is to be on \A1cnever Y but not X is on. Z is to remain in its previous condition whenever X and Y are both off. X and Y are never both on at the same time. ~'.'1len a designer begins to fonnulate a description of a circui~ the type of flow table normally used is the primitive-form flow table. A primitive-form flow table is one which contains only one stable state per row. In a primitive flow table the output is a function only of the internJ.l states. Figure 3 is the primitive-form flow table for the example associated with Flgure 1. The primary reason for generating a primitive-form flow table is its simplicity. Other types of flow tables are generally mere compact, that is they have a fewer ntm1ber of internal states_. but they are seldom as easy to formulate as the primitive-form. A second reason for formulating this type of flow table is that it is easy to recognize physically un::calizable machines \vhen generating their primitive-form flow tables. This is not always the case with the other forms of f lc·\v tables. In a primitive-form flow table the mapping of internal states into output states is a simple one-to-one relation. The r.1apping of inputs into internal st3tes is not a simple 5 XY 00 01 11 10 @JYO s2 s4 ~--- - s3 ~1 - - s s 1+ btl 2 - --·---- sl - - ~0 Figure 3. The primitive-form flow table for the DC S-R flip-flop. relation. The primary concern in the generation of p·.cimitive-form flow tables is thr=refore to formulate the mapping of the inputs into the internal states. Once the flow table has been constructed there exist con~put::er programs w}lich \vill accept it as input and yield e1s outpu-:: the complete rainimal and/or near minimal, hazard- free design equations for fundamental mode asynchronous . 1 . 2 sequent~a c1rcu1ts . Programs also exist \vhich will accept these design equations and convert them all the way to the layout of the printed circuit boards for the ~ hardware~ To make use of these programs the logic designer mllSt first convert the formal description of the circuit to be designed into a series of input-output sequences.
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