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Applying Asynchronous Techniques to Architectures Exploiting ILP at Compile Time DSS: Applying Asynchronous Techniques to Architectures Exploiting ILP at Compile Time Wei Shi, Zhiying Wang, Hongguang Ren, Ting Cao*, Wei Chen, Bo Su, and Hongyi Lu School of Computer, *Department of computer science National University of Defense Technology, *Australian National University {shiwei,zywang,ren,chenwei,subo,hylu}@nudt.edu.cn *[email protected] Abstract—Embedded application environments require both network consumed more than 25% of the total power in many high performance and low power. Architectures exploiting applications. Approximately 70% of the power is burned by instruction-level parallelism (ILP) at compile time, such as very the clock distribution and latches in the POWER 4 processor long instruction word (VLIW) and transport triggered archite- [4]. In the Alpha 21264, 32% of the chip power is attributed to cture (TTA), may satisfy the requirements. They can be further the global clock network [5]. In embedded SuperHTM proc- enhanced by using asynchronous circuits to significantly reduce power consumption. As such, we are interested in asynchronous essor core, the clock-tree and Flip-Flops take 35% of the total processors with architectures exploiting ILP at compile time. power [6]. In the VLIW processor core of TMS320C6416T, However, most of the current asynchronous processors are based the clock distribution network contribution percentage to the on RISC-like architectures. When designing asynchronous VLIW total power consumption is about 76% for some simple algor- or TTA processors, the distribution of control introduces some ithms [7]. Instead of being driven periodically by a global serious problems, and errors may occur because of the variable clock, asynchronous circuits work on demand and stop when latencies of operations. This paper investigates the asynchronous processor with architecture exploiting ILP at compile time. In not needed. For this reason, a design utilizing asynchronous order to overcome these problems, we propose a data source circuits produces an effectively power-efficient architecture. selecting (DSS) scheme to guarantee instructions run correctly Moreover, an asynchronous circuit exhibits average-case on asynchronous VLIW and TTA processors. Concretely, an performance rather than the worst-case performance of a asynchronous pipelined processor based on TTA is designed. The synchronous circuit. micro-architecture of the proposed asynchronous TTA processor In the past two decades, many asynchronous processors is presented and an asynchronous processor named Tengyue is implemented using 180nm technology. The experimental results, have emerged. The first asynchronous processor was designed for a range of benchmarks and working modes, show that the at Caltech in 1988 [8], and it was followed by FAM (fully implemented asynchronous TTA processor with DSS scheme asynchronous microprocessor) [9], NSR (non-synchronous support runs correctly and power dissipation is reduced to about RISC) [10], STRiP (self-timed RISC processor) [11], Amulet 43% to 65% of the equivalent synchronous processor. [12], TITAC [13], MiniMIPS [14], ARM996HS [15], and so on. Almost all of the above asynchronous processors are based I. INTRODUCTION on RISC architectures. Nowadays, VLIW and TTA are being As the complexity of embedded applications is growing widely used in the embedded domain for their hardware rapidly, systems in the embedded domain are required to be of simplicity [16], [17]. However, the design methods used for high performance to meet real-time requirements. Exploiting asynchronous RISC-like architectures cannot be directly appl- ILP is an attractive approach to satisfying the high perfor- ied to asynchronous EICT architectures. mance requirements, and two approaches are typically used: In EICT architectures, data and control hazards are over- traditional CPU, such as superscalar processor, can exploit the come at compile time. The compiler knows the latency of each ILP at run time, and we abbreviate this type of architectures to operation, and the latency information is used to schedule EIRT (exploiting ILP at run time) architectures; while others, instructions. Processors run the scheduled program instruction such as VLIW and TTA based processors, exploit the ILP at by instruction and need not to do dependence detection at run compile time and they are abbreviated to EICT (exploiting ILP time. However, EICT architectures cannot tolerate variable at compile time) architectures in this paper. Furthermore, low latencies of operations. When we implement an EICT arch- power consumption is also required for mobile embedded itecture based processor using asynchronous circuits, the environments. In order to improve energy-efficiency, a lot of centralized control becomes distributed because the global techniques are proposed to overcome the power problem at clock is replaced by local handshake signals. The naive different levels ranging from circuits to applications [1]. replacement of the global clock in a synchronous processor The clock related components have become the largest with local handshake signals to produce an asynchronous power consuming part in a processor, and these components processor may result in incorrect behaviors. By removing the include the clock generator, the clock distribution tree, clock global clock, it is no longer possible to use the cycle count to drivers, latches and the clock loading due to all the clocked measure the variable latencies of operations. That is to say, elements [2]. Friedman [3] reported that the clock distribution there has always been a conflict between the indefinite 978-1-4244-8935-0/10/$26.00 ©2010 IEEE 321 k n a b Fig. 1. TTA long instruction format. Fig. 2. Synchronous circuit and its asynchronous equivalent. latencies of asynchronous circuits and the accurate cycle count domain, identifying the source of the data; destination domain, of operations demanded by the compiler. This paper proposes which specifies the target of the transport. a DSS scheme to guarantee programs run correctly on asyn- There are usually 5 kinds of components in a TTA based chronous EICT architectures. In the DSS scheme, the results processor. Those components are the instruction fetch unit, of operations are buffered and then correct results are picked instruction decode unit, interconnection network, register files as inputs of the corresponding operations. In order to elaborate and functional units. All of the register files and functional the DSS scheme, the design of an asynchronous pipelined units are connected by the interconnection network through processor based on TTA employing the DSS scheme is sockets. Data transports are performed through these sockets, presented. and these sockets are controlled by the decode unit. Each The paper is organized as follows. Section II introduces the functional unit contains one or more operand registers, a TTA and asynchronous circuit design method. Section III unique trigger register, and one or more result registers. When presents the asynchronous TTA with DSS scheme. The detail data is written into the trigger register, the functional unit is implementation of the asynchronous TTA is explained in triggered to perform computation using the data in both Section IV. The delay, area and power consumption of the operand registers and trigger register, and then output results proposed asynchronous TTA processor are compared to its are written into the result registers. The pipeline of TTA synchronous counterpart in Section V. Conclusions are given usually contains 4 stages: instruction fetch (IF), instruction in Section VI. decode (ID), transport (MV) and execution (EXE). The EXE stage can be further divided into several pipeline stages. II. PRELIMINARIES B. Asynchronous Design Flow A. The Synchronous Transport Triggered Architecture Synchronous-to-asynchronous circuit conversion methodol- In this paper, we take TTA as an example of EICT archi- ogy [19], which converts synchronous circuits into asynchr- tectures to elaborate the DSS scheme. This is because TTA onous ones using existing EDA tools and flows, is an efficient can be regarded as an extreme example of EICT architectures. design approach for asynchronous circuits. Furthermore, the Actually, some hardware mechanisms such as simplified de-synchronization method proposed in [20] is very popular. scoreboard may also be used by VLIW in some situations, but In this paper, we use a simple design flow which is similar to there are not any hardware mechanisms to do dependence the de-synchronization methodology to implement a TTA detection and hazard elimination in TTA. based asynchronous processor. In our design flow, the global TTA proposed by H. Corporaal [18] can be viewed as a clock network is replaced by local handshake circuits, and the superset of the traditional VLIW architecture. However, TTA Flip-Flops in data paths commonly remain the same as the ori- has unique characteristics compared to conventional processor ginal synchronous processor. The local controller of a control architectures. One of the main features of a TTA processor is path uses redundant four-phase latch control (RFLC) protocol that all the actions are actually side-effects of transporting data which is combined with 2 simple four-phase latch controllers. from one place to another. When the data is written into a The synchronous circuit and its asynchronous equivalent are special register, called a trigger register, execution is triggered. shown in Fig. 2(a) and Fig. 2(b) respectively. Consequently,
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