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Data Transfer Operations in a 68008 Based Microcomputer System

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Data Transfer Operations in a 68008 Based Microcomputer System DATA TRA NSF ER OPERATIONS IN A 68008 BASED MICROCOMPUTER SYSTEM BY ENEFAA GEORGE DOUGLAS Bachelor of Science Oklahoma State University Stillwater, Ok lahoma 1983 Submitted to the Fa culty of the Graduate College of the Oklahoma State University i n par t i a l fulfillment of the requ1rements for the Degree of MASTER OF SCIENCE Ma y, 1985 DATA TRANSFER OPERATIONS IN A 68008 BASED MICROCOMPUTER SYSTEM APPROUED : . i i PREFA CE Understanding the methods of data transfer in a computer system is essential to its maintenance. Different microprocessors transfer data differently. Data is usually transferred between the processor and the system memory or between peripherals and the processor. Three methods of data transfer were examined in this report namely, synchronous data transfer, asynchronous data transfer and a combination of the above two methods. Synchronous data transfer uses the clock to connect sequence and time. Intervals between clock transitions must therefore be such as to permit enough time for the activities planned for that interval. Asynchronous data transfer on the other hand is independent of clock frequency at the system l e vel. Co mmu nication on the system bus -is without a timing signal a llowing any amount of t ime between data bytes or words. To indicate when data has been received or sent, the e xternal dev ice sends a n acknowledgement signal to the processor . Synchronous/Asynchronous mod e of operation allows the synchronous device to be clocke d at its ma x imum operating frequency using an e xternally generated enable CE) clock . This way, the processor runs asynchronously and the acknow ledgement signal is generated synchronously wi th the e xternal enable clock . No one method is superior but the last method is iii recommended. The method to use depends on the application . I wish to express m~ gratitude to all the people who assisted me in this work. In particular, I wo uld like to thank Dr. Neal Willison for his assistance with special t echnical bckground materials, Dr. John Baird for his patience and assistance, Dr. Craig Anderson for serv ing on t he committee, Dr. Larr~ Jones for allowing me to use his t exts for references and Miss Jane Bushaw for her support. iv TABLE OF CONTENT Chapter- Page I INTRODUCTION . 1 Statement of pr-oblem . 1 Objective 2 II SYSTEM DESCR I PI I ON . 3 Cr-iter-ia for choice of hardwar-e . 3 Hardwa r-e descr-iption of processor­ Y: Dat a t ransfer methods and impl em entation . 8 III DATA TRA NSFE R ME THODS COMPA RISON AND CO NCLUSION . 21 As ~nch ronous versus s~ n c h r onous me thods . 2 1 Conclus1on . 2 3 ~~Lt~I LU ~l~LlOGRA P HY . 27 APPE ND I XES . 2 9 APPENDIX A - Glossary of t erms . 29 v Chapte~ Page APPENDIX B - System Block Diagram and P~og~amming model . APPENDIX C - Memory DTACK Generation. 37 APPENDIX D - System Cycle flowcharts . ~0 APPENDIX E - System Circuit and Interfa cing Logic . ~6 APPENDIX f - System Timing And Bus Cycle Operations . APPENDIX G - Input/Output Decoding . 52 vi LIST OF FIGURES Figure Pag e 1. S~ stem Block Diagram . 35 2. Processor ?cogramming ~ od el . 3 6 3. ROM / SRAM OTACK Gerera ~ or . 38 li. DRAM DTACK GeneraLDr . 39 5.1. Read- Mo d if ~-W rite C~c le flowchart lil 5.2. Byte Read C~cle flowchart 5.3. B~te Write C~cle flowchart S.li. Vector Aquisition flowchart . 6 .1. S~nchronous Device C~cl e flowchart 6.2. S~nchronous Circuit Operation and Interfacing '-± 7 7. S~nchronous I As~nchronous Interface Logic . B. MC 68008 and 6800-t~ps Bus Timing for Read Operation . so 9. Read C~ cle Timing Diagram f o r Mc 68008 51 10. Input I Output Decoder . 53 vii CHAPTER ONE INTRODUCTION One of the exciting features of the computer field is that concepts and applications once considered exotic and unattainable can become commonplace almost overnight. This rapid rate of change places a special burden on computer professionals if the~ are to s ta~ up-to-date with the latest developments . The best insurance against becomi ng obsolete is a solid educational.background that la~s a foundatiori for lifelong learning. A major responsibilit~ of the computer educator is to ma ke sure that the educational program prope r !~ prepa ~e students for entrance i nto the computer science and engineering profession. For computer educato~s . developing and maintain1ng an up- to-date curriculum is a major problem . However, these p ~obl ems a re also impo~tant to the indust~ial communit~ , since the e ducational background of recent g~adua tes dete ~min es how well the~ will be able to contribute to future computer developments. The computer societ~ is v er~ fortunate to have a g r oup o f memb e rs from academia, government, and industr~ who, through the parti c ipation of 1 all parties, design a wide range of projects to improve t he educational processes at all levels. Closel~ related to the educational programs in computer science and engineering are the programs in computer technolog~. These programs provide graduates with the understanding and technical background needed to maintain both the hardware and software of modern computer s~stems. Unfortunatel~, many established programs in computer technolog~ lack the depth required to prepare a student with the tools needed to solve real-world problems. The main objective of this report therefore is to devise a step b~ step procedure in designing f or a synchronous/ asynchronous data transfer operation in a 68008 based mi crocomput er system . The dev ised ste ps .to follow a r e : 1 ) c hoosing which processor to use, 2 ) t he pr oces s or's hardwar e des c r iption , 3 ) asynchronous data tran s fer o perations, ~ ) s~ n chronou s data t ransfer o perations and 5 ) synchronous/ asynchronous data transfer operat1o ns. 2 CHAPTER TWO SYSTEM DESCRIPTION CHOOSING THE PROCESSOR As more and more 16-bit microprocessors appear on the market, the question of which one to base an educational s~stem on becomes mo re difficult. Ideall~, most designers wi l l base their decision on thorough hands-on e xperience , but getting hold of an inexpensive s~stem is almost impossible . The S~ste m propose d here is based on an 8 / 16/ 32 b i t processo r C 8 - bit e x ternal data bus ; 8 / 16/ 32- bit internal data bus ), It is the Mo t orola MC68008 microprocessor. There a r e seve ral reasons for choosing this processor , na mel ~ : a ) The 8 - bit e xternal d a t a bus is readil~ i nte rfa c e d t o al r ea d ~ e x ist ing 8-bit processors , memories , and periphera l chi ps . b ) The 68008 is sour ce and obj ect code compat i ble with the 16- bit 68000 processor alre ad ~ used in s uc h 3 microcomputers as the Apple Macintosh, the Altos, the Commodore Amiga, the Atari 520ST , and the Radio Shack TRS-80 Models 16 and 6000. c) The 68008 has a linear address space Cie, a non-segmented addres s space) of one megab~te as compared to the 6~ kilob~tes of standard 8-bit processors. d) The 68008 like all the other of the 68000 fam i ly of processors have powerful addressing modes designed to implement high level languages. e) Proven reliabilit~ and commitment on the part of Motorola to maintain compatibility between its new chips and the 68000 processor. f) Memor~ mapped input/output CI / 0). Thi s I/0 scheme reduces component count CDoughert~, 1986). Hardware Description Of The 68008 Microprocessor The main component of a ny c omputer s~stem is t he Central Processing Unit CCPU ) . It is t he dut~ of the processor to ~ro vi d e o r r eque st data and select pr oper address for this data. In addition , the CPU 1s c a pabl e of performi ng a limit ed set of mathemat1cal a nd logical o pe r ati ons on the data. Proper des ign can r e duce the total chip count i n a mi crocomp uter s~stem withou t i ncreasing cost , limiting e x pa nda b i lit~, o r sacr ificing perf ormance. These goals were 4 accomplished by using the MC68008 microprocessor in combination with four other large scale integrated CLSI) chips and some support chips as shown in the block diagram of Figure 1. The MC68008 has the same internal architecture as, and is fully software compatible with the MC68000 microprocessor unit C MPU), but has an eight bit external data bus. It therefore allows the design of a cost-effective system using an eight bit non-multiplexed data bus. It also provide the benefits of a 32-bit microprocessor architecture. The 68008 is available in two packages C a ~8 DIP and a 52 DIP packages). The ~8 pin package was used for this design. The large non-segmented address space of the 68008 allows large modular proorams to be developed and e xecuted efficientl~. This means the program segment sizes are to be determined b~ the application rather than the designer who rna~ o t herwise be forced to adopt an arbitrary segment size without regard to the application's individual requirements. The programmer's mo del of t he 68008 processor is identical to t hat of the 68000 as shown in Figure 2.
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