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An Efficient Design Methodology for Complex Sequential Asynchronous Digital Circuits San Jose State University SJSU ScholarWorks Master's Theses Master's Theses and Graduate Research Fall 2020 An Efficient Design Methodology for Complex Sequential Asynchronous Digital Circuits Tomasz Chadzynski San Jose State University Follow this and additional works at: https://scholarworks.sjsu.edu/etd_theses Recommended Citation Chadzynski, Tomasz, "An Efficient Design Methodology for Complex Sequential Asynchronous Digital Circuits" (2020). Master's Theses. 5139. DOI: https://doi.org/10.31979/etd.gy4n-x9sz https://scholarworks.sjsu.edu/etd_theses/5139 This Thesis is brought to you for free and open access by the Master's Theses and Graduate Research at SJSU ScholarWorks. It has been accepted for inclusion in Master's Theses by an authorized administrator of SJSU ScholarWorks. For more information, please contact [email protected]. AN EFFICIENT DESIGN METHODOLOGY FOR COMPLEX SEQUENTIAL ASYNCHRONOUS DIGITAL CIRCUITS. A Thesis Presented to The Faculty of the Department of Electrical Engineering San José State University In Partial Fulfillment of the Requirements for the Degree Master of Science by Tomasz Ch ˛adzynski´ December 2020 © 2020 Tomasz Ch ˛adzynski´ ALL RIGHTS RESERVED The Designated Thesis Committee Approves the Thesis Titled AN EFFICIENT DESIGN METHODOLOGY FOR COMPLEX SEQUENTIAL ASYNCHRONOUS DIGITAL CIRCUITS. by Tomasz Ch ˛adzynski´ APPROVED FOR THE DEPARTMENT OF ELECTRICAL ENGINEERING SAN JOSÉ STATE UNIVERSITY December 2020 Tri Caohuu, Ph.D. Department of Electrical Engineering Chang Choo, Ph.D. Department of Electrical Engineering Morris Jones, MSEE Department of Electrical Engineering ABSTRACT AN EFFICIENT DESIGN METHODOLOGY FOR COMPLEX SEQUENTIAL ASYNCHRONOUS DIGITAL CIRCUITS. by Tomasz Ch ˛adzynski´ Asynchronous digital logic as a design alternative offers a smaller circuit area and lower power consumption but suffers from increased complexity and difficulties related to logic hazards and elements synchronization. The presented work proposes a design methodology based on the speed-independent sequential logic theory, oriented toward asynchronous hardware implementation of complex multi-step algorithms. Targeting controller-centric devices that perform data-driven non-linear execution, the methodology offers a CSP language-based controller workflow description approach and the specification of a project implementation template supported by a two-stage design process. First, the CSP layer describes complex speed-independent controller behavior offering better scalability and maintainability than the STG model. Second, the component-oriented design template specifies functional elements’ structural organization and emphasizes the divide-and-conquer philosophy, streamlining large and complex devices’ design and maintenance. Finally, the implementation process is divided into two stages: a rapid development and functional verification stage and a synthesizable codebase stage. Additionally, a case study design of a split-transaction MESI cache coherency controller and its analysis are presented to validate the proposed methodology. The testing phase compares synthesized and routed gate-level asynchronous and synchronous implementations. For models synthesized to work with the same speed, the asynchronous circuit area is 20% smaller with lower power consumption at approximately 18% of the synchronous reference. The synchronous version synthesized for performance is 3.5 times faster, at the cost of a large increase in area and power usage. The results prove the methodology’s ability to deliver working complex asynchronous circuits competitive in the chip area and power characteristics. To my beloved wife Joanna and our daughter Emilia. ACKNOWLEDGMENTS I want to thank Dr. Tri Caohuu for his continuous guidance and support. Professor Caohuu dedicated an enormous amount of time to help me with the research, and thanks to his guidance, this work came into the shape it is today. I would also like to thank Dr. David Parent, Prof. Morris Jones and Audrey Leong for their time spent helping me with the Lab Equipment and Practical portion of the thesis. I am incredibly grateful to Professor Parent for his time spent, ensuring that I have all the required CAD software available to finish this thesis. Additionally, I would like to thank Magdalena Krajewska, Mikayla Hutchinson, Attapol Rutherford, Keith Mueller, Greg Boyd, Bruce Rakes, Curt Kineast and Adam Molzahn, whom in past years, inspired and helped me get to this point. vi TABLE OF CONTENTS List of Tables..........................................................................x List of Figures......................................................................... xii List of Abbreviations.................................................................. xiii 1 Introduction........................................................................1 2 Literature Survey..................................................................6 2.1 General Introductory Literature..........................................6 2.2 Asynchronous Controller Design and Synthesis........................8 2.3 Circuit Level Element Design............................................9 2.4 CSP Language Applications in Asynchronous Logic Design.......... 10 2.5 Multi-Core Systems and Cache Coherency............................. 11 2.6 Practical Applications of Asynchronous Logic Design................. 12 2.7 Null Convention Logic as an Alternative Approach in Asynchronous Logic Design.............................................................. 13 3 Theory of Asynchronous Logic Design Review................................ 15 3.1 The input-output mode asynchronous sequential system............... 15 3.1.1 State Graph representation and Complete State Coding.......... 17 3.1.2 Synthesis to gate level representation.............................. 20 3.2 Handshake protocols and communication between asynchronous modules................................................................... 24 3.3 CSP notation in describing asynchronous sequential transition system 27 4 Complex Sequential Asynchronous Logic Design Methodology.............. 28 4.1 Model template organization............................................. 29 4.2 Part 1: Stage 1 Model for behavioral design and verification.......... 31 4.2.1 Using CSP in modeling sequential behavior of the controller... 34 4.2.2 The Controller....................................................... 38 4.2.3 Flow Support Elements............................................. 44 4.2.4 Additional components............................................. 51 4.2.5 Putting the model together......................................... 53 4.3 Design of the CSP to STG parser........................................ 56 4.3.1 Model representation in CSP....................................... 62 4.3.2 Translation from CSP to STG...................................... 72 4.3.3 Synthesis from the STG model using Petrify..................... 82 4.4 Part 2: Stage 2 Model for logic synthesis............................... 84 4.5 Asynchronous Extension to standard set of ASIC primitives.......... 91 vii 4.6 Model Synthesis and delay matching.................................... 98 4.6.1 Bottom-up selective module synthesis............................. 99 4.6.2 Post-synthesis timing analysis and delay matching............... 104 4.6.3 Post Place and Route delay matching through ECO.............. 108 4.6.4 Synthesis of the Controller Circuit................................. 109 5 Case Study: Asynchronous MESI Cache Coherence Controller with Split Transaction Bus................................................................... 112 5.1 Cache Coherence MESI Algorithm and Split Transaction Bus Review112 5.2 Cache coherency controller design goals................................ 115 5.3 Cache coherency controller design assumptions........................ 118 5.4 Asynchronous Cache Coherence Controller Design.................... 120 5.4.1 Pending Request Log component design.......................... 125 5.4.2 Receiver component design........................................ 128 5.4.3 Responder component design...................................... 135 5.4.4 Sender component design.......................................... 142 5.4.5 Controller module................................................... 162 5.5 Reference synchronous design........................................... 164 5.6 Note on synthesis approach of the Controller circuit................... 166 6 Future Improvements.............................................................. 167 6.1 Improvements to the methodology and tools............................ 167 6.1.1 The FSE completion detection..................................... 167 6.1.2 Difficult syntax of the confusion block............................ 168 6.1.3 Passing CSP fragments as arguments to other CSP fragments... 169 6.1.4 Full support of standard C-implementation synthesis of set and reset Boolean functions............................................. 169 6.2 Improvements to the cache coherency controller design............... 170 6.2.1 Handling main memory regions with different properties........ 170 6.2.2 Implementing cache line size larger than a single word.......... 171 6.2.3 Removing the assumption that memory is always slower than the cores............................................................. 173 6.2.4 The PLOG bottleneck.............................................. 175 6.2.5 Extending the number of cores, asynchronous arbiter bottleneck 177
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